1/*
2 * Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <riscv32-litex-vexriscv.dtsi>
10
11/ {
12	model = "LiteX VexRiscV";
13	compatible = "litex,vexriscv";
14	chosen {
15		zephyr,console = &uart0;
16		zephyr,shell-uart = &uart0;
17		zephyr,sram = &ram0;
18	};
19
20	aliases {
21		watchdog0 = &wdt0;
22	};
23
24	ram0: memory@40000000 {
25		device_type = "memory";
26		reg = <0x40000000 0x10000000>;
27	};
28};
29
30&ctrl0 {
31	status = "okay";
32};
33
34&uart0 {
35	status = "okay";
36	current-speed = <115200>;
37};
38
39&timer0 {
40	status = "okay";
41};
42
43&wdt0 {
44	status = "okay";
45};
46
47&mdio0 {
48	status = "okay";
49};
50
51&phy0 {
52	status = "okay";
53};
54
55&eth0 {
56	status = "okay";
57};
58
59&dna0 {
60	status = "okay";
61};
62
63&spi0 {
64	status = "okay";
65};
66
67&prbs0 {
68	status = "okay";
69};
70
71&i2c0 {
72	status = "okay";
73};
74
75&pwm0 {
76	status = "okay";
77};
78
79&gpio_out {
80	status = "okay";
81};
82
83&gpio_in {
84	status = "okay";
85};
86
87&i2s_rx {
88	status = "okay";
89};
90
91&i2s_tx {
92	status = "okay";
93};
94
95&clk0 {
96	status = "okay";
97};
98
99&clk1 {
100	status = "okay";
101};
102
103&clock0 {
104	status = "okay";
105};
106