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/Zephyr-latest/dts/arm/st/u5/
Dstm32u545Xi.dtsi10 sram0: memory@20000000 {
15 sram1: memory@28000000 {
Dstm32u5a9Xj.dtsi11 sram0: memory@20000000 {
16 sram1: memory@28000000 {
/Zephyr-latest/doc/services/ipc/ipc_service/backends/
Dipc_service_icmsg.rst8 memory footprint. The ICMsg backend is build on top of :ref:`spsc_pbuf`.
13 The ICMsg backend uses shared memory and MBOX devices for exchanging data.
14 Shared memory is used to store the data, MBOX devices are used to signal that
27 * If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
29 You can skip it if none of the communication sides is using data cache on shared memory.
30 * Define two memory regions and assign them to ``tx-region`` and ``rx-region``
31 of an instance. Ensure that the memory regions used for data exchange are
48 reserved-memory {
49 tx: memory@20070000 {
53 rx: memory@20078000 {
[all …]
/Zephyr-latest/dts/xtensa/
Dsample_controller.dtsi21 sram0: memory@60000000 {
22 device_type = "memory";
/Zephyr-latest/tests/kernel/mem_protect/mem_map/boards/
Dup_squared.overlay7 /* there is a memory hole from address 0x10000000-0x12150fff
9 * this range, so limit the memory range below 0x10000000.
/Zephyr-latest/samples/subsys/mgmt/mcumgr/smp_svr/sysbuild/
Dnrf52840dk_nrf52840_mcuboot_ram_load.overlay3 compatible = "zephyr,memory-region", "mmio-sram";
5 zephyr,memory-region = "RetainedMem";
/Zephyr-latest/drivers/firmware/scmi/
DKconfig14 bool "SCMI transport based on shared memory and doorbells"
20 Enable support for SCMI transport based on shared memory
39 bool "SCMI shared memory (SHMEM) driver"
43 Enable support for SCMI shared memory (SHMEM) driver.
46 int "SCMI shared memory (SHMEM) initialization priority"
/Zephyr-latest/dts/arm/gd/gd32l23x/
Dgd32l233rc.dtsi12 sram1: memory@20004000 {
18 sram: memory@20000000 {
37 * for flash memory.
/Zephyr-latest/doc/hardware/peripherals/edac/
Dibecc.rst10 an integrated memory controller with IBECC.
14 of physical memory space. The IBECC is useful for memory technologies that do
17 IBECC adds memory overhead of 1/32 of the memory. This memory is not accessible
42 mode 0 there are more BIOS configuration options such as memory regions.
64 implement desired policy with respect for handling those memory errors. Error
/Zephyr-latest/dts/arm/adi/max32/
Dmax78002.dtsi82 sram1: memory@20008000 {
87 sram2: memory@20010000 {
92 sram3: memory@20020000 {
97 sram4: memory@20030000 {
102 sram5: memory@20040000 {
107 sram6: memory@20050000 {
112 sram7: memory@2005c000 {
Dmax32690.dtsi71 sram1: memory@20020000 {
76 sram2: memory@20040000 {
81 sram3: memory@20060000 {
86 sram4: memory@20080000 {
91 sram5: memory@200a0000 {
96 sram6: memory@200c0000 {
101 sram7: memory@200d0000 {
/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc11u6x.dtsi22 sram0:memory@10000000 {
26 sram1:memory@20000000 {
27 compatible = "zephyr,memory-region", "mmio-sram";
29 zephyr,memory-region = "SRAM1";
32 sram2:memory@20004000 {
33 compatible = "zephyr,memory-region", "mmio-sram";
35 zephyr,memory-region = "SRAM2";
Dnxp_rt118x_cm7.dtsi13 compatible = "zephyr,memory-region", "nxp,imx-itcm";
15 zephyr,memory-region = "ITCM";
19 compatible = "zephyr,memory-region", "nxp,imx-dtcm";
21 zephyr,memory-region = "DTCM";
24 memory: memory@20484000 { label
Dnxp_lpc55S06_ns.dtsi22 compatible = "zephyr,memory-region", "mmio-sram";
24 zephyr,memory-region = "SRAMX";
/Zephyr-latest/arch/arm/core/mpu/
DKconfig45 Enable this to allow MPU RWX access to flash memory
56 MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT(ARMv7-M) sometimes cause memory
57 wasting in linker scripts defined memory sections. Use this symbol
58 to guarantee user custom section align size to avoid more memory used
66 Custom align size of memory section in linker scripts. Usually
67 it should consume less alignment memory. Although this alignment
/Zephyr-latest/boards/nxp/mimxrt595_evk/
Dboard.cmake9 board_runner_args(linkserver "--override=/device/memory/5/flash-driver=MIMXRT500_SFDP_MXIC_OSPI_S.…
10 board_runner_args(linkserver "--override=/device/memory/5/location=0x18000000")
/Zephyr-latest/soc/ti/simplelink/
DKconfig18 Turn on dynamic memory allocation for DPL objects. Reserves
19 extra memory for this.
/Zephyr-latest/boards/st/stm32h7b3i_dk/
Dstm32h7b3i_dk.dts10 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
55 compatible = "zephyr,memory-region", "mmio-sram";
56 device_type = "memory";
58 zephyr,memory-region = "SDRAM2";
59 /* Frame buffer memory cache will cause screen flickering. */
60 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
63 octo_nor: memory@90000000 {
64 compatible = "zephyr,memory-region";
66 zephyr,memory-region = "EXTMEM";
68 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
/Zephyr-latest/doc/hardware/arch/
Dx86.rst17 memory are identity mapped and thus giving the appearance of execution
23 is being placed in the memory, and its counterpart
31 but are still loaded in physical memory. However, during boot, code
39 to the physical memory. Later in the boot process,
42 the identity mapping of physical memory. This unmapping must be done
44 restricted memory via physical addresses. Since the identity mapping
58 (Page Directory Pointer) covers 1GB of memory. For example:
71 (Page Directory) covers 4MB of memory.
83 memory mappings. This is useful for static mappings and/or device MMIO
118 Note that specifying additional memory mappings requires larger storage
[all …]
/Zephyr-latest/doc/develop/languages/c/
Dindex.rst91 C defines a standard dynamic memory management interface (for example,
95 While the details of the dynamic memory management implementation varies across
99 * manage its own memory heap either internally or by invoking the hook
102 * maintain the architecture- and memory region-specific alignment requirements
103 for the memory blocks allocated by the standard dynamic memory allocation
106 * allocate memory blocks inside the ``z_malloc_partition`` memory partition
109 For more details regarding the C standard library-specific memory management
113 Native Zephyr applications should use the :ref:`memory management API
118 C standard dynamic memory management interface functions such as
/Zephyr-latest/boards/st/stm32h745i_disco/
Dstm32h745i_disco_stm32h745xx_m7.dts38 compatible = "zephyr,memory-region", "mmio-sram";
39 device_type = "memory";
41 zephyr,memory-region = "SDRAM2";
42 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
45 ext_memory: memory@90000000 {
46 compatible = "zephyr,memory-region";
48 zephyr,memory-region = "EXTMEM";
50 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
/Zephyr-latest/boards/firefly/roc_rk3568_pc/
Droc_rk3568_pc.dts22 sram0: memory@40000000 {
23 device_type = "memory";
/Zephyr-latest/doc/kernel/usermode/
Dmpu_stack_objects.rst11 For architectures which utilize memory protection unit (MPU) hardware,
13 has implications for the placement of stacks in memory, as well as the
16 requirements for MPU regions. This is discussed in the memory placement
23 to memory. Memory protection units can provide this kind of support.
37 memory. These constraints include determining the alignment of the stack and
41 The main source of the memory constraints is the MPU design for the SoC. The
58 that covers the memory access to determine the enforcement policy. Others may
/Zephyr-latest/boards/digilent/arty_a7/
DCMakeLists.txt7 # Generate zephyr.mem verilog memory hex dump file for initialising ITCM in
25 …message(STATUS "Verilog memory hex dump will be written to: ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_…
27 …bin2hex (${CROSS_COMPILE_TARGET}-bin2hex) utility was not found, verilog memory hex dump file cann…
/Zephyr-latest/doc/hardware/peripherals/
Dbbram.rst6 The BBRAM APIs allow interfacing with the unique properties of this memory region. The following
14 Along with these, the API provides a means for reading and writing to the memory region via
16 succeed if the BBRAM is in a valid state and the operation is bounded to the memory region.

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