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/Zephyr-latest/boards/phytec/phyboard_pollux/
Dphyboard_pollux_mimx8ml8_m7_defconfig14 # y for TCM memory space
17 # y for DDR memory space
/Zephyr-latest/dts/arm/st/l4/
Dstm32l496Xe.dtsi10 sram0: memory@20000000 {
13 sram1: memory@10000000 {
/Zephyr-latest/tests/drivers/retained_mem/api/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay3 compatible = "zephyr,memory-region", "mmio-sram";
5 zephyr,memory-region = "RetainedMem";
Dnrf54h20dk_nrf54h20_cpurad.overlay3 compatible = "zephyr,memory-region", "mmio-sram";
5 zephyr,memory-region = "RetainedMem";
Dnrf54l09pdk_nrf54l09_cpuapp.overlay3 compatible = "zephyr,memory-region", "mmio-sram";
5 zephyr,memory-region = "RetainedMem";
Dqemu_cortex_m3.overlay5 compatible = "zephyr,memory-region", "mmio-sram";
7 zephyr,memory-region = "Retention";
Dnrf54l15dk_nrf54l15_cpuapp.overlay3 compatible = "zephyr,memory-region", "mmio-sram";
5 zephyr,memory-region = "RetainedMem";
Dnrf52840dk_nrf52840_ram.overlay3 compatible = "zephyr,memory-region", "mmio-sram";
5 zephyr,memory-region = "RetainedMem";
Dnrf5340dk_nrf5340_cpuapp.overlay3 compatible = "zephyr,memory-region", "mmio-sram";
5 zephyr,memory-region = "RetainedMem";
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi89 icache0: memory@42000000 {
90 compatible = "zephyr,memory-region";
92 zephyr,memory-region = "ICACHE0";
95 dcache0: memory@3c000000 {
96 compatible = "zephyr,memory-region";
98 zephyr,memory-region = "DCACHE0";
106 sram0: memory@40370000 {
107 compatible = "zephyr,memory-region", "mmio-sram";
109 zephyr,memory-region = "SRAM0";
112 sram1: memory@3fc88000 {
[all …]
/Zephyr-latest/samples/subsys/demand_paging/
DREADME.rst12 can be tagged to be loaded into memory on demand, and also be automatically
13 evicted for more code to be executed when memory is exhausted.
41 Calling huge body of code that doesn't fit in memory
42 free memory pages: from 37 to 0, 987 page faults
44 free memory pages: from 0 to 0, 987 page faults
/Zephyr-latest/tests/drivers/adc/adc_api/boards/
Dnucleo_h743zi.overlay7 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
17 zephyr,memory-attr = < DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) >;
/Zephyr-latest/tests/drivers/flash_simulator/flash_sim_impl/boards/
Dnucleo_f411re.overlay9 compatible = "zephyr,memory-region", "mmio-sram";
11 zephyr,memory-region = "FlashSim";
23 memory-region = <&sram_2001C000>;
/Zephyr-latest/tests/drivers/dma/loop_transfer/boards/
Dstm32h750b_dk.overlay8 zephyr,memory-attr = <DT_MEM_ARM_MPU_RAM_NOCACHE>;
9 zephyr,memory-region = "SRAM4";
/Zephyr-latest/boards/mediatek/mt8196/
Dmt8196_adsp.dts12 sram0: memory@4e100000 {
13 device_type = "memory";
18 dram0: memory@90000000 {
19 device_type = "memory";
24 dram1: memory@90800000 {
25 device_type = "memory";
/Zephyr-latest/samples/subsys/ipc/openamp/boards/
Dlpcxpresso55s69_lpc55s69_cpu0.overlay10 * shared memory reserved for the inter-processor communication
18 sram4duplicate: memory@20040000 {
/Zephyr-latest/samples/subsys/ipc/openamp/remote/boards/
Dlpcxpresso55s69_lpc55s69_cpu1.overlay10 * shared memory reserved for the inter-processor communication
18 sram4duplicate: memory@20040000 {
/Zephyr-latest/dts/arm/st/u5/
Dstm32u5a5Xj.dtsi11 sram0: memory@20000000 {
15 sram1: memory@28000000 {
Dstm32u599Xj.dtsi10 sram0: memory@20000000 {
14 sram1: memory@28000000 {
/Zephyr-latest/samples/net/sockets/echo_client/boards/
Dfrdm_mcxw71.overlay11 compatible = "zephyr,memory-region","mmio-sram";
13 zephyr,memory-region = "RetainedMem";
/Zephyr-latest/samples/net/sockets/echo_server/boards/
Dfrdm_mcxw71.overlay11 compatible = "zephyr,memory-region","mmio-sram";
13 zephyr,memory-region = "RetainedMem";
/Zephyr-latest/samples/userspace/shared_mem/
DREADME.rst4 Use memory partitioning to protect memory between threads.
9 unique memory domains with protected partitions. The
10 application uses memory partitioning with a sample algorithm
53 encrypt thread copies the memory from the common buffer into the
54 encrypted thread's private memory when the flag is set and then clears
57 The CT is copied to a shared memory partition connecting to the third
/Zephyr-latest/doc/services/tfm/
Dintegration.rst42 we can see that the ``ns`` version defines offsets in flash and SRAM memory, which leave
47 reserved-memory {
52 /* The memory regions defined below must match what the TF-M
54 * assumed. Please see the memory layout in:
58 code: memory@100000 {
62 ram: memory@28100000 {
67 This reserves 1 MB of code memory and 1 MB of RAM for secure boot and TF-M,
69 RAM at 0x28100000. 512 KB code memory is available for the NS zephyr image,
72 This matches the flash memory layout we see in ``flash_layout.h`` in TF-M:
/Zephyr-latest/boards/st/stm32h747i_disco/
Dstm32h747i_disco_stm32h747xx_m7.dts10 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
27 compatible = "zephyr,memory-region", "mmio-sram";
28 device_type = "memory";
30 zephyr,memory-region = "SDRAM2";
31 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
34 ext_memory: memory@90000000 {
35 compatible = "zephyr,memory-region";
37 zephyr,memory-region = "EXTMEM";
39 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
/Zephyr-latest/boards/snps/nsim/arc_classic/
Dnsim-flat-mem.dtsi19 ddr0: memory@DDR_ADDR {
20 device_type = "memory";

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