1/*
2 * Copyright (c) 2023 Laczen
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/ {
8	sram_2001C000:sram@2001C000 {
9		compatible = "zephyr,memory-region", "mmio-sram";
10		reg = <0x2001C000 0x4000>;
11		zephyr,memory-region = "FlashSim";
12		status = "okay";
13	};
14
15	soc {
16		sim_flash_controller: sim-flash-controller@0 {
17			compatible = "zephyr,sim-flash";
18			reg = <0x0 0x1>;
19
20			#address-cells = <1>;
21			#size-cells = <1>;
22			erase-value = <0xff>;
23			memory-region = <&sram_2001C000>;
24
25			flash_sim0: flash_sim@0 {
26				status = "okay";
27				compatible = "soc-nv-flash";
28				erase-block-size = <512>;
29				/* the flash_simulator test uses a write block
30				 * size of 4 for alignment test, so set it to 4.
31				 */
32				write-block-size = <4>;
33				reg = <0x00000000 DT_SIZE_K(16)>;
34			};
35		};
36	};
37};
38
39&flash_sim0 {
40	partitions {
41		compatible = "fixed-partitions";
42		#address-cells = <1>;
43		#size-cells = <1>;
44
45		lfsram_partition: partition@0 {
46			label = "lfsram";
47			reg = <0x00000000 DT_SIZE_K(16)>;
48		};
49	};
50};
51