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/Zephyr-latest/boards/nxp/mimxrt1062_fmurt6/doc/
Dindex.rst13 Arm® Cortex-M7® core up to 600 MHz.
272 Run JLink.exe and choose device / core as MIMXRT106A-ALEXA.
352 …tions-processors/i.mx-rt-series/i.mx-rt1060-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1060
/Zephyr-latest/doc/connectivity/bluetooth/
Dbluetooth-dev.rst160 on its network core, or, with the network core running only the controller, the application
161 core running the host and your application, and the HCI transport over IPC.
/Zephyr-latest/boards/adafruit/feather_esp32s3_tft/doc/
Dindex.rst17 - ESP32-S3 mini module, featuring the dual core 32-bit Xtensa Microprocessor
33 multiprocessing. Due to its dual-core architecture, each core can be enabled to
/Zephyr-latest/boards/toradex/verdin_imx8mp/doc/
Dindex.rst35 energy-efficient processor. With four cores in this cluster, each core is equipped with its own L1
127 It is recommended to disable peripherals used by the M7 core on the Linux host.
176 A53 core. The A53 core is responsible to load the M7 binary application into the RAM, put the M7 in
/Zephyr-latest/scripts/west_commands/runners/
Desp32.py12 from runners.core import RunnerCaps, ZephyrBinaryRunner
Dblackmagicprobe.py14 from runners.core import RunnerCaps, ZephyrBinaryRunner
Dnrfutil.py12 from runners.core import _DRY_RUN
/Zephyr-latest/soc/microchip/mec/mec15xx/
DKconfig1 # Microchip MEC1501 MCU core series
/Zephyr-latest/boards/silabs/dev_kits/sim3u1xx_dk/doc/
Dindex.rst12 - CPU core: ARM Cortex®-M3
/Zephyr-latest/boards/silabs/radio_boards/xg24_rb4187c/doc/
Dindex.rst18 - CPU core: ARM Cortex®-M33 with FPU
/Zephyr-latest/boards/seeed/xiao_rp2040/doc/
Dindex.rst17 carries the powerful Dual-core RP2040 processor with a flexible
/Zephyr-latest/boards/weact/stm32g431_core/
Dweact_stm32g431_core.dts15 compatible = "weact,stm32g431-core";
/Zephyr-latest/arch/x86/
Dia32.cmake120 add_subdirectory(core)
/Zephyr-latest/arch/arm/core/cortex_m/tz/
DKconfig1 # ARM TrustZone-M core configuration options
/Zephyr-latest/boards/nxp/mimxrt1160_evk/
Dmimxrt1160_evk_mimxrt1166_cm7.dts100 * timer will be used instead of systick, as allows the core clock to
/Zephyr-latest/boards/renesas/rcar_spider_s4/doc/
Drcar_spider_a55.rst20 * 1.0 GHz Arm Cortex-R52 core (hardware Lock step is supported);
/Zephyr-latest/boards/nuvoton/numaker_pfm_m467/doc/
Dindex.rst8 Ethernet series MCU with ARM® -Cortex®-M4F core.
/Zephyr-latest/boards/beagle/beaglev_fire/doc/
Dindex.rst7 PolarFire® MPFS025T 5x core RISC-V System on Chip (SoC) with FPGA fabric. BeagleV®-Fire opens up new
20 * ``beaglev_fire/polarfire/e51``: Uses only the E51 core
/Zephyr-latest/boards/toradex/verdin_imx8mm/doc/
Dindex.rst85 It is recommended to disable peripherals used by the M4 core on the Linux host.
136 to be started by the A53 core. The A53 core is responsible to load the M4 binary
/Zephyr-latest/boards/silabs/radio_boards/slwrb4180b/doc/
Dindex.rst18 - CPU core: ARM Cortex®-M33 with FPU
/Zephyr-latest/boards/gd/gd32vf103c_starter/doc/
Dindex.rst9 The GD32VF103CB features a single-core RISC-V 32-bit MCU which can run up
/Zephyr-latest/doc/services/debugging/
Ddebugmon.rst10 otherwise crash when the core halts (e.g. applications that need to keep
/Zephyr-latest/boards/starfive/visionfive2/doc/
Dindex.rst7 multi-core 64bit RISC-V SoC.
/Zephyr-latest/arch/x86/core/
DKconfig.intel6429 support limited call-tree depth and must fit into the low core,
/Zephyr-latest/boards/lowrisc/opentitan_earlgrey/doc/
Dindex.rst14 - RV32IMCB RISC-V "Ibex" core

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