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/Zephyr-latest/boards/brcm/bcm958401m2/doc/
Dindex.rst53 Zephyr applications running on the M7 core can also be tested by observing UART console output.
/Zephyr-latest/subsys/debug/coredump/
DKconfig8 Enable core dump so it can be used for offline debugging.
59 minimum core dump.
/Zephyr-latest/boards/phytec/phyboard_lyra/doc/
Dphyboard_lyra_am62xx_a53.rst10 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core.
11 Zephyr OS is ported to run on the Cortex®-A53 core.
/Zephyr-latest/boards/snps/emsdp/doc/
Dindex.rst19 The EM Software Development Platform supports different core configurations, such as EM4,
20 EM5D, EM6, EM7D, EM7D+ESP, EM9D, EM11D. The core must be supplied as the variant of the base
21 board which takes the form ``emsdp/<core>`` whereby core is ``emsdp_em4`` for EM4,
25 The following table shows the hardware features supported for different core configuration:
166 Development Platform board support for Zephyr, note that the core also need to
/Zephyr-latest/boards/st/stm32h747i_disco/doc/
Dindex.rst143 The dual core nature of STM32H747 SoC requires sharing HW resources between the
146 - **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
160 Applications for the ``stm32h747i_disco`` board should be built per core target,
186 The target core is detected automatically.
245 Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
/Zephyr-latest/boards/nxp/mimxrt595_evk/doc/
Dindex.rst8 Cadence Tensilica Fusion F1 DSP core with a next-generation Arm Cortex-M33
9 core. These devices are designed to unlock the potential of display-based applications
20 - MIMXRT595SFFOC Cortex-M33 (275 MHz) core processor with Cadence Tensilica Fusion F1 DSP
176 You can build a Zephyr application for the RT500 DSP core by targeting the F1
177 SOC. Xtensa toolchain supporting RT500 DSP core is included in Zephyr SDK.
178 To build the hello_world sample for the RT500 DSP core:
/Zephyr-latest/doc/develop/west/
Dzephyr-cmds.rst248 …arch_system_halt 65 ../arch/arc/core/fatal.c FUNC_NORETURN void arch_system_halt(unsigned int re…
249 …arch_system_halt 455 ../arch/arm64/core/fatal.c FUNC_NORETURN void arch_system_halt(unsigned int …
250 …arch_system_halt 137 ../arch/nios2/core/fatal.c FUNC_NORETURN void arch_system_halt(unsigned int …
251 …arch_system_halt 18 ../arch/posix/core/fatal.c FUNC_NORETURN void arch_system_halt(unsigned int …
252 …arch_system_halt 17 ../arch/x86/core/fatal.c FUNC_NORETURN void arch_system_halt(unsigned int re…
253 …arch_system_halt 126 ../arch/xtensa/core/fatal.c FUNC_NORETURN void arch_system_halt(unsigned int…
/Zephyr-latest/scripts/west_commands/runners/
Dminichlink.py9 from runners.core import RunnerCaps, RunnerConfig, ZephyrBinaryRunner
Dnsim.py10 from runners.core import RunnerCaps, ZephyrBinaryRunner
/Zephyr-latest/subsys/ipc/ipc_service/backends/
DKconfig.rpmsg11 created in the multi-instance / multi-core RPMsg backend module to
/Zephyr-latest/boards/brcm/bcm958402m2/doc/
Da72.rst49 Zephyr applications running on the Cortex-A72 core can also be tested
Dm7.rst49 Zephyr applications running on the M7 core can also be tested
/Zephyr-latest/soc/st/stm32/stm32h7x/
DKconfig92 bool "Boot M4 core during M7 init independent of option byte BCM4."
/Zephyr-latest/boards/mediatek/mt8195/
Dmt8195_adsp.dts43 compatible = "cdns,xtensa-core-intc";
/Zephyr-latest/tests/ztest/fail/
DREADME.rst10 There's a subdirectory to this test called 'core'. This project builds a sample as a
/Zephyr-latest/boards/nxp/imx93_evk/doc/
Dindex.rst13 Cortex®-M33 core. Zephyr OS is ported to run on one of the Cortex®-A55 core.
109 CPU's UART2 for A55 core and M33 core.
307 on an A55 core using Jailhouse as a way to "take away" one A55 core from Linux and
348 SOF+Zephyr will run as an inmate, alongside Linux, on core 1 of the board. This means that
349 said core will be taken away from Linux and will only be utilized by Zephyr.
/Zephyr-latest/boards/rakwireless/rak11720/doc/
Dindex.rst22 - ARM® Cortex® M4F core
23 - 16 kB 2-way Associative/Direct-Mapped Cache per core
/Zephyr-latest/boards/beagle/beagleplay/doc/
Dbeagleplay_cc1352p7.rst7 quad-core ARM Cortex-A53 SoC with an external TI SimpleLink multi-standard CC1352P7 wireless MCU
20 * Dual-core 32-bit RISC Programmble Real-Time Unit (PRU)
/Zephyr-latest/doc/kernel/services/threads/
Dnothread.rst10 * Examples intended to demonstrate core functionality
21 These core capabilities shall function correctly when
/Zephyr-latest/scripts/
Dlist_hardware.py9 import pykwalify.core
45 pykwalify.core.Core(source_data=data,
217 pykwalify.core.Core(source_data=archs, schema_data=arch_schema).validate()
/Zephyr-latest/boards/silabs/starter_kits/slstk3402a/doc/
Dindex.rst39 Gecko and the Jade Gecko is their core. The Pearl Gecko contains an ARM®
40 Cortex®-M4F core, and the Jade Gecko an ARM® Cortex®-M3 core. Other features
/Zephyr-latest/boards/fanke/fk7b0m1_vbt6/doc/
Dindex.rst9 The FK7B0M1-VBT6 core board by FANKE Technology Co., Ltd. is an advanced microcontroller
10 platform based on the STMicroelectronics Arm® Cortex®-M7 core STM32H7B0VBT6 microcontroller.
87 The default configuration per core can be found in
/Zephyr-latest/arch/arm/core/
DKconfig.vfp7 # indicate that the CPU core can be configured with the specified
26 # type of the VFP core instantiated by the SoC.
198 # specify the type of the VFP core instantiated by the SoC.
/Zephyr-latest/soc/openisa/rv32m1/
Dlinker.ld65 * Each RISC-V core on this chip (RI5CY and ZERO-RISCY) has
69 * (The Arm core vector tables are at the beginning of each
156 /* The vector table goes into core-dependent flash locations. */
/Zephyr-latest/boards/renesas/rzg3s_smarc/doc/
Dindex.rst54 The RZ/G3S-EVKIT allows different applications to be executed in RZ/G3S SoC. With its multi-core ar…
55 each core can operate independently to perform customized tasks or exchange data using the OpenAMP …
121 MACHINE=smarc-rzg3s bitbake core-image-minimal
275 …/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11-ghz-cpu-and-dual-core…

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