Searched refs:core (Results 126 – 150 of 877) sorted by relevance
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| /Zephyr-latest/tests/subsys/fs/littlefs/ |
| D | Kconfig | 4 mainmenu "littlefs core functionality test"
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| /Zephyr-latest/soc/nxp/imx/imx6sx/ |
| D | Kconfig.defconfig | 1 # i.MX 6SoloX core series
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| D | Kconfig.soc | 1 # i.MX 6SoloX core series
19 NXP iMX6 SoloX M4 core
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| /Zephyr-latest/boards/arduino/nicla_vision/doc/ |
| D | index.rst | 7 STM32H747GAII, a dual core ARM Cortex-M7 + Cortex-M4 MCU, with 2MBytes of Flash
55 The dual core nature of STM32H747 SoC requires sharing HW resources between the
58 - **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
70 Applications for the ``arduino_nicla_vision`` board should be built per core target,
114 Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
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| /Zephyr-latest/boards/ti/sk_am62/doc/ |
| D | index.rst | 8 Cortex-M4F MCU core and the following features:
20 cluster and a single Cortex-M4 core in the MCU domain. Zephyr is ported to run on
21 the M4F core and the following listed hardware specifications are used:
62 These cores will then load the zephyr binary on the M4 core using remoteproc.
74 To test the M4F core, we build the :zephyr:code-sample:`hello_world` sample with the following comm…
94 The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot.
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| /Zephyr-latest/soc/adi/max32/ |
| D | Kconfig | 50 bool "Secondary RISC-V core enable"
56 hex "Secondary RISC-V core boot address"
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| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.cavs | 27 external oscillator and is external to the CPU core(s).
28 It is not as fast as the internal core clock, but provides
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| /Zephyr-latest/scripts/west_commands/runners/ |
| D | qemu.py | 7 from runners.core import RunnerCaps, ZephyrBinaryRunner
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| D | __init__.py | 8 from runners.core import MissingProgram, ZephyrBinaryRunner
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| /Zephyr-latest/arch/riscv/ |
| D | CMakeLists.txt | 3 add_subdirectory(core)
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| /Zephyr-latest/subsys/debug/ |
| D | thread_analyzer.c | 172 static void isr_stack(int core) in isr_stack() argument
174 const uint8_t *buf = K_KERNEL_STACK_BUFFER(z_interrupt_stacks[core]); in isr_stack()
175 size_t size = K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[core]); in isr_stack()
184 THREAD_ANALYZER_VSTR("ISR"), core, unused, in isr_stack()
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| /Zephyr-latest/samples/drivers/mbox_data/ |
| D | README.rst | 14 After each core receives data, it increments it by one and sends it back to other core.
78 serial port, one is the main core another is the remote core:
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| /Zephyr-latest/boards/element14/warp7/doc/ |
| D | index.rst | 6 The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7
7 core and Single Cortex M4 core.
8 Zephyr was ported to run on the M4 core. In a later release, it will also
9 communicate with the A7 core (running Linux) via RPmsg.
38 - CPU i.MX7 Solo with a Single Cortex A7 (800MHz) core and
39 Single Cortex M4 (200MHz) core
114 the A7 core. The A7 core is responsible to load the M4 binary application into
180 After powering up the platform stop the u-boot execution on the A7 core and
251 1. Put the M4 core in reset
255 5. Get the M4 core out of reset
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| /Zephyr-latest/soc/nxp/imxrt/ |
| D | Kconfig | 22 # should be set elsewhere, since the determination of which SOC core
146 bool "Dual core operation on the RT11xx series"
149 Indicates the second core will be enabled, and the part will run
150 in dual core mode. Enables dual core operation on the RT11xx series,
157 string "Directory to with output image header from second core"
161 from when launching a second core image
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| /Zephyr-latest/scripts/west_commands/tests/ |
| D | conftest.py | 9 from runners.core import RunnerConfig, FileType
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| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/ |
| D | Kconfig.defconfig | 8 # Zephyr does not support SMP on aarch32 yet, so we default to 1 CPU core
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| /Zephyr-latest/boards/m5stack/m5stickc_plus/doc/ |
| D | index.rst | 6 M5StickC PLUS, one of the core devices in M5Stacks product series, is an ESP32-based development bo…
10 - ESP32-PICO-D4 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi)
26 .. _ST7789v2: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/ST7789V.pdf
27 .. _MPU-6886: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/MPU-6886-00…
28 .. _ESP32-PICO-D4: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/esp32-…
29 .. _SPM-1423: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SPM1423HM4H…
215 - `M5StickC PLUS schematic <https://static-cdn.m5stack.com/resource/docs/products/core/m5stickc_plu…
217 - `M5StickC PLUS docs <https://docs.m5stack.com/en/core/m5stickc_plus>`_
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| /Zephyr-latest/doc/connectivity/networking/ |
| D | network_tracing.rst | 10 User can enable network core stack and socket API calls tracing.
12 The :kconfig:option:`CONFIG_TRACING_NET_CORE` option controls the core network
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| /Zephyr-latest/soc/nxp/kinetis/k8x/ |
| D | Kconfig | 35 int "Freescale K8x core clock divider"
38 This option specifies the divide value for the K8x processor core clock
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| /Zephyr-latest/tests/drivers/can/timing/ |
| D | Kconfig | 11 impose limits on which bitrates can be met due to limitations in the CAN core clock
31 CiA 601-3 recommends the following CAN FD core clock frequencies for good node
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| /Zephyr-latest/snippets/nordic-flpr-xip/soc/ |
| D | nrf54l15_cpuapp.overlay | 12 /* FLPR core code partition */
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| /Zephyr-latest/boards/qemu/xtensa/ |
| D | Kconfig.defconfig | 12 # Must match XCHAL_DCACHE_LINESIZE form core-isa.h
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| /Zephyr-latest/samples/subsys/nvs/boards/ |
| D | nucleo_wb55rg.overlay | 11 /* Set 12KB of storage at the end of 1st half of flash (dual core constraints) */
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| /Zephyr-latest/drivers/video/ |
| D | Kconfig.emul_rx | 5 bool "Software implementation of video frame RX core"
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| /Zephyr-latest/arch/mips/ |
| D | CMakeLists.txt | 15 add_subdirectory(core)
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