| /Zephyr-latest/drivers/pwm/ |
| D | pwm_nrf_sw.c | 98 uint32_t channel, uint32_t period_cycles, in pwm_period_check() argument
110 if ((i != channel) && in pwm_period_check()
120 static int pwm_nrf_sw_set_cycles(const struct device *dev, uint32_t channel, in pwm_nrf_sw_set_cycles() argument
136 if (channel >= config->map_size) { in pwm_nrf_sw_set_cycles()
137 LOG_ERR("Invalid channel: %u.", channel); in pwm_nrf_sw_set_cycles()
144 ret = pwm_period_check(data, config->map_size, channel, period_cycles, in pwm_nrf_sw_set_cycles()
166 gpiote = config->gpiote[channel].p_reg; in pwm_nrf_sw_set_cycles()
167 psel_ch = config->psel_ch[channel]; in pwm_nrf_sw_set_cycles()
168 gpiote_ch = data->gpiote_ch[channel]; in pwm_nrf_sw_set_cycles()
169 ppi_chs = data->ppi_ch[channel]; in pwm_nrf_sw_set_cycles()
[all …]
|
| D | pwm_mcux_ftm.c | 57 ftm_chnl_pwm_config_param_t channel[MAX_CHANNELS]; member
64 static int mcux_ftm_set_cycles(const struct device *dev, uint32_t channel, in mcux_ftm_set_cycles() argument
72 uint32_t pair = channel / 2U; in mcux_ftm_set_cycles()
86 if (channel >= config->channel_count) { in mcux_ftm_set_cycles()
99 data->channel[channel].dutyValue = pulse_cycles; in mcux_ftm_set_cycles()
102 data->channel[channel].level = kFTM_HighTrue; in mcux_ftm_set_cycles()
104 data->channel[channel].level = kFTM_LowTrue; in mcux_ftm_set_cycles()
112 if (irqs & BIT_MASK(ARRAY_SIZE(data->channel))) { in mcux_ftm_set_cycles()
135 status = FTM_SetupPwmMode(config->base, data->channel, in mcux_ftm_set_cycles()
148 uint32_t channel, pwm_flags_t flags, in mcux_ftm_configure_capture() argument
[all …]
|
| D | pwm_test.c | 18 static int vnd_pwm_set_cycles(const struct device *dev, uint32_t channel, in vnd_pwm_set_cycles() argument
26 static int vnd_pwm_configure_capture(const struct device *dev, uint32_t channel, in vnd_pwm_configure_capture() argument
34 static int vnd_pwm_enable_capture(const struct device *dev, uint32_t channel) in vnd_pwm_enable_capture() argument
39 static int vnd_pwm_disable_capture(const struct device *dev, uint32_t channel) in vnd_pwm_disable_capture() argument
46 uint32_t channel, uint64_t *cycles) in vnd_pwm_get_cycles_per_sec() argument
|
| D | pwm_capture.c | 22 uint32_t channel, in z_pwm_capture_cycles_callback() argument
36 int z_impl_pwm_capture_cycles(const struct device *dev, uint32_t channel, in z_impl_pwm_capture_cycles() argument
51 err = pwm_configure_capture(dev, channel, flags, in z_impl_pwm_capture_cycles()
58 err = pwm_enable_capture(dev, channel); in z_impl_pwm_capture_cycles()
66 (void)pwm_disable_capture(dev, channel); in z_impl_pwm_capture_cycles()
67 (void)pwm_configure_capture(dev, channel, flags, NULL, NULL); in z_impl_pwm_capture_cycles()
|
| /Zephyr-latest/drivers/dma/ |
| D | dma_rpi_pico.c | 58 uint32_t channel) in rpi_pico_dma_channel_clear_error_flags() argument
62 ((dma_hw_t *)cfg->reg)->ch[channel].al1_ctrl &= ~DMA_INT_ERROR_FLAGS; in rpi_pico_dma_channel_clear_error_flags()
66 uint32_t channel) in rpi_pico_dma_channel_get_error_flags() argument
70 return ((dma_hw_t *)cfg->reg)->ch[channel].al1_ctrl & DMA_INT_ERROR_FLAGS; in rpi_pico_dma_channel_get_error_flags()
73 static inline void rpi_pico_dma_channel_abort(const struct device *dev, uint32_t channel) in rpi_pico_dma_channel_abort() argument
77 ((dma_hw_t *)cfg->reg)->abort = BIT(channel); in rpi_pico_dma_channel_abort()
96 static inline uint32_t dma_rpi_pico_channel_irq(const struct device *dev, uint32_t channel) in dma_rpi_pico_channel_irq() argument
101 if (cfg->irq0_channels[i] == channel) { in dma_rpi_pico_channel_irq()
113 static int dma_rpi_pico_config(const struct device *dev, uint32_t channel, in dma_rpi_pico_config() argument
119 if (channel >= cfg->channels) { in dma_rpi_pico_config()
[all …]
|
| D | dma_nxp_sdma.c | 211 static int dma_nxp_sdma_channel_init(const struct device *dev, uint32_t channel) in dma_nxp_sdma_channel_init() argument
217 chan_data = &dev_data->chan[channel]; in dma_nxp_sdma_channel_init()
218 SDMA_CreateHandle(&chan_data->handle, dev_cfg->base, channel, &sdma_contexts[channel]); in dma_nxp_sdma_channel_init()
225 static void dma_nxp_sdma_setup_bd(const struct device *dev, uint32_t channel, in dma_nxp_sdma_setup_bd() argument
234 chan_data = &dev_data->chan[channel]; in dma_nxp_sdma_setup_bd()
237 chan_data->bd_pool = &dev_data->bd_pool[channel][0]; in dma_nxp_sdma_setup_bd()
266 static int dma_nxp_sdma_config(const struct device *dev, uint32_t channel, in dma_nxp_sdma_config() argument
274 if (channel >= FSL_FEATURE_SDMA_MODULE_CHANNEL) { in dma_nxp_sdma_config()
275 LOG_ERR("sdma_config() invalid channel %d", channel); in dma_nxp_sdma_config()
279 dma_nxp_sdma_channel_init(dev, channel); in dma_nxp_sdma_config()
[all …]
|
| D | dma_intel_lpss.c | 48 int dma_intel_lpss_reload(const struct device *dev, uint32_t channel, in dma_intel_lpss_reload() argument
51 int dma_intel_lpss_reload(const struct device *dev, uint32_t channel, in dma_intel_lpss_reload()
61 if (channel >= DW_CHAN_COUNT) { in dma_intel_lpss_reload()
65 chan_data = &dev_data->chan[channel]; in dma_intel_lpss_reload()
72 ctrl_hi = dw_read(dev_cfg->base, DW_CTRL_HIGH(channel)); in dma_intel_lpss_reload()
88 int dma_intel_lpss_get_status(const struct device *dev, uint32_t channel, in dma_intel_lpss_get_status() argument
99 if (channel >= DW_CHAN_COUNT) { in dma_intel_lpss_get_status()
103 chan_data = &dev_data->chan[channel]; in dma_intel_lpss_get_status()
104 ctrl_hi = dw_read(dev_cfg->base, DW_CTRL_HIGH(channel)); in dma_intel_lpss_get_status()
108 if (!(dw_read(dev_cfg->base, DW_DMA_CHAN_EN) & DW_CHAN(channel))) { in dma_intel_lpss_get_status()
|
| /Zephyr-latest/drivers/counter/ |
| D | counter_nxp_s32_sys_timer.c | 108 uint8_t channel) in stm_disable_channel() argument
110 REG_WRITE(STM_CCR(channel), STM_CCR_CEN(0U)); in stm_disable_channel()
111 REG_WRITE(STM_CIR(channel), STM_CIR_CIF(1U)); in stm_disable_channel()
114 static int stm_set_alarm(const struct device *dev, uint8_t channel, uint32_t ticks, uint32_t flags) in stm_set_alarm() argument
118 struct nxp_s32_sys_timer_chan_data *ch_data = &data->ch_data[channel]; in stm_set_alarm()
147 stm_disable_channel(config, channel); in stm_set_alarm()
148 REG_WRITE(STM_CMP(channel), ticks); in stm_set_alarm()
149 REG_WRITE(STM_CCR(channel), STM_CCR_CEN(1U)); in stm_set_alarm()
166 atomic_or(&data->irq_pending, BIT(channel)); in stm_set_alarm()
183 uint8_t channel; in stm_isr() local
[all …]
|
| /Zephyr-latest/dts/arm/renesas/ra/ra4/ |
| D | ra4-cm4-common.dtsi | 131 channel = <0>;
145 channel = <1>;
159 channel = <9>;
168 channel = <0>;
177 channel = <1>;
186 channel = <0>;
201 channel = <1>;
218 #io-channel-cells = <1>;
227 #io-channel-cells = <1>;
234 channel = <0>;
[all …]
|
| D | ra4-cm33-common.dtsi | 122 channel = <0>;
136 channel = <9>;
145 channel = <0>;
156 channel = <1>;
163 channel = <0>;
178 channel = <1>;
193 channel = <2>;
208 channel = <3>;
223 channel = <4>;
238 channel = <5>;
[all …]
|
| /Zephyr-latest/dts/arm/renesas/ra/ra6/ |
| D | ra6-cm33-common.dtsi | 117 channel = <0>;
131 channel = <9>;
138 channel = <0>;
145 channel = <1>;
154 channel = <0>;
165 channel = <1>;
174 channel = <0>;
189 channel = <1>;
204 channel = <2>;
219 channel = <3>;
[all …]
|
| /Zephyr-latest/dts/arm/renesas/ra/ra8/ |
| D | ra8x1.dtsi | 176 channel = <0>;
182 channel = <1>;
198 channel = <0>;
212 channel = <1>;
226 channel = <2>;
240 channel = <3>;
254 channel = <4>;
268 channel = <9>;
287 #io-channel-cells = <1>;
289 channel-count = <12>;
[all …]
|
| /Zephyr-latest/samples/drivers/audio/dmic/src/ |
| D | main.c | 38 cfg->streams[0].pcm_rate, cfg->channel.req_num_chan); in do_pdm_transfer()
104 .channel = { in main()
109 cfg.channel.req_num_chan = 1; in main()
110 cfg.channel.req_chan_map_lo = in main()
114 BLOCK_SIZE(cfg.streams[0].pcm_rate, cfg.channel.req_num_chan); in main()
121 cfg.channel.req_num_chan = 2; in main()
122 cfg.channel.req_chan_map_lo = in main()
127 BLOCK_SIZE(cfg.streams[0].pcm_rate, cfg.channel.req_num_chan); in main()
|
| /Zephyr-latest/samples/subsys/usb/audio/headphones_microphone/ |
| D | app.overlay | 11 channel-l;
12 channel-r;
22 channel-l;
23 channel-r;
|
| /Zephyr-latest/tests/drivers/counter/counter_basic_api/boards/ |
| D | mimxrt1170_evk_mimxrt1176_cm7.overlay | 15 /* channel 2 disabled to test disabled channel not breaking things */
29 /* channel 2 disabled to test disabled channel not breaking things */
|
| D | mimxrt1160_evk_mimxrt1166_cm7.overlay | 15 /* channel 2 disabled to test disabled channel not breaking things */
29 /* channel 2 disabled to test disabled channel not breaking things */
|
| /Zephyr-latest/samples/subsys/usb/audio/headset/ |
| D | app.overlay | 11 mic-channel-l;
12 mic-channel-r;
15 hp-channel-l;
16 hp-channel-r;
|
| /Zephyr-latest/drivers/dac/ |
| D | dac_shell.c | 18 uint8_t channel; member
26 .channel = 2,
45 cfg.channel_id = strtoul(argv[args_indx.channel], NULL, 0); in cmd_setup()
75 uint8_t channel; in cmd_write_value() local
85 channel = strtoul(argv[args_indx.channel], NULL, 0); in cmd_write_value()
88 err = dac_write_value(dac, channel, value); in cmd_write_value()
|
| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_rv32m1_intmux.c | 58 uint32_t channel = rv32m1_intmux_channel(irq); in rv32m1_intmux_irq_enable() local
61 regs->CHANNEL[channel].CHn_IER_31_0 |= BIT(line); in rv32m1_intmux_irq_enable()
67 uint32_t channel = rv32m1_intmux_channel(irq); in rv32m1_intmux_irq_disable() local
70 regs->CHANNEL[channel].CHn_IER_31_0 &= ~BIT(line); in rv32m1_intmux_irq_disable()
91 uint32_t channel = rv32m1_intmux_channel(irq); in rv32m1_intmux_get_line_state() local
94 if ((regs->CHANNEL[channel].CHn_IER_31_0 & BIT(line)) != 0) { in rv32m1_intmux_get_line_state()
105 #define ISR_ENTRY(channel, line) \ argument
106 ((channel) * CONFIG_MAX_IRQ_PER_AGGREGATOR + line)
113 uint32_t channel = POINTER_TO_UINT(arg); in rv32m1_intmux_isr() local
114 uint32_t line = (regs->CHANNEL[channel].CHn_VEC >> 2); in rv32m1_intmux_isr()
[all …]
|
| /Zephyr-latest/drivers/mbox/ |
| D | mbox_nxp_imx_mu.c | 34 static int nxp_imx_mu_send(const struct device *dev, uint32_t channel, const struct mbox_msg *msg) in nxp_imx_mu_send() argument
39 if (channel >= MU_MAX_CHANNELS) { in nxp_imx_mu_send()
45 return MU_TriggerInterrupts(cfg->base, kMU_GenInt0InterruptTrigger >> channel); in nxp_imx_mu_send()
56 MU_SendMsg(cfg->base, channel, data32); in nxp_imx_mu_send()
60 static int nxp_imx_mu_register_callback(const struct device *dev, uint32_t channel, in nxp_imx_mu_register_callback() argument
65 if (channel >= MU_MAX_CHANNELS) { in nxp_imx_mu_register_callback()
69 data->cb[channel] = cb; in nxp_imx_mu_register_callback()
70 data->user_data[channel] = user_data; in nxp_imx_mu_register_callback()
87 static int nxp_imx_mu_set_enabled(const struct device *dev, uint32_t channel, bool enable) in nxp_imx_mu_set_enabled() argument
92 if (channel >= MU_MAX_CHANNELS) { in nxp_imx_mu_set_enabled()
[all …]
|
| D | mbox_ivshmem.c | 68 static int ivshmem_mbox_send(const struct device *dev, mbox_channel_id_t channel, in ivshmem_mbox_send() argument
72 ARG_UNUSED(channel); in ivshmem_mbox_send()
76 LOG_DBG("sending notification to the peer id 0x%x\n", (int)channel); in ivshmem_mbox_send()
77 return ivshmem_int_peer(dev_cfg->ivshmem_dev, (int)channel, 0); in ivshmem_mbox_send()
80 static int ivshmem_mbox_register_callback(const struct device *dev, mbox_channel_id_t channel, in ivshmem_mbox_register_callback() argument
83 ARG_UNUSED(channel); in ivshmem_mbox_register_callback()
116 static int ivshmem_mbox_set_enabled(const struct device *dev, mbox_channel_id_t channel, in ivshmem_mbox_set_enabled() argument
120 ARG_UNUSED(channel); in ivshmem_mbox_set_enabled()
|
| D | mbox_nxp_mailbox.c | 112 static int nxp_mailbox_send(const struct device *dev, uint32_t channel, const struct mbox_msg *msg) in nxp_mailbox_send() argument
117 if (channel >= MAILBOX_MAX_CHANNELS) { in nxp_mailbox_send()
123 MAILBOX_SetValueBits(cfg->base, MAILBOX_ID_OTHER_CPU, GEN0_IRQ_TRIGGER >> channel); in nxp_mailbox_send()
137 (DATA0_IRQ_TRIGGER >> channel) | (data32 & DATA_MASK)); in nxp_mailbox_send()
142 static int nxp_mailbox_register_callback(const struct device *dev, uint32_t channel, in nxp_mailbox_register_callback() argument
147 if (channel >= MAILBOX_MAX_CHANNELS) { in nxp_mailbox_register_callback()
151 data->cb[channel] = cb; in nxp_mailbox_register_callback()
152 data->user_data[channel] = user_data; in nxp_mailbox_register_callback()
170 static int nxp_mailbox_set_enabled(const struct device *dev, uint32_t channel, bool enable) in nxp_mailbox_set_enabled() argument
174 if (channel >= MAILBOX_MAX_CHANNELS) { in nxp_mailbox_set_enabled()
[all …]
|
| /Zephyr-latest/samples/drivers/adc/adc_sequence/boards/ |
| D | s32z2xxdc2_s32z270_rtu0.overlay | 19 group-channel = "standard";
24 channel@3 {
32 channel@4 {
40 channel@5 {
48 channel@6 {
|
| /Zephyr-latest/tests/drivers/i2c/i2c_tca954x/boards/ |
| D | nrf52840dk_nrf52840.overlay | 17 compatible = "ti,tca9546a-channel";
24 compatible = "ti,tca9546a-channel";
34 i2c-channel-0 = &ch0;
35 i2c-channel-1 = &ch1;
|
| /Zephyr-latest/tests/net/lib/wifi_credentials/src/ |
| D | main.c | 94 uint8_t channel = 0; in ZTEST() local
99 ARRAY_SIZE(psk_buf), &psk_len, &flags, &channel, &timeout); in ZTEST()
118 uint8_t channel = 0; in ZTEST() local
124 ARRAY_SIZE(psk_buf), &psk_len, &flags, &channel, &timeout); in ZTEST()
128 zassert_equal(channel, 0, "Channel mismatch"); in ZTEST()
150 uint8_t channel = 0; in ZTEST() local
156 ARRAY_SIZE(psk_buf), &psk_len, &flags, &channel, &timeout); in ZTEST()
162 zassert_equal(channel, CHANNEL1, "Channel mismatch"); in ZTEST()
184 uint8_t channel = 0; in ZTEST() local
190 ARRAY_SIZE(psk_buf), &psk_len, &flags, &channel, &timeout); in ZTEST()
[all …]
|
