| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_intel_adsp.h | 89 static inline void intel_adsp_wdt_pause(uint32_t base, const uint32_t core) in intel_adsp_wdt_pause() argument
91 const uint32_t reg_addr = base + DSPCxWDTCS + DSPBRx_OFFSET(core); in intel_adsp_wdt_pause()
108 static inline void intel_adsp_wdt_resume(uint32_t base, const uint32_t core) in intel_adsp_wdt_resume() argument
110 const uint32_t reg_addr = base + DSPCxWDTCS + DSPBRx_OFFSET(core); in intel_adsp_wdt_resume()
127 static inline void intel_adsp_wdt_reset_set(uint32_t base, const uint32_t core, const bool enable) in intel_adsp_wdt_reset_set() argument
129 sys_write32(enable ? DSPCxWDTCS_STORE : 0, base + DSPCxWDTCS + DSPBRx_OFFSET(core)); in intel_adsp_wdt_reset_set()
149 static inline uint32_t intel_adsp_wdt_pointer_get(uint32_t base, const uint32_t core) in intel_adsp_wdt_pointer_get() argument
151 return FIELD_GET(DSPCxWDTIPPTR_PTR, sys_read32(base + DSPCxWDTIPPTR + DSPBRx_OFFSET(core))); in intel_adsp_wdt_pointer_get()
162 static inline uint32_t intel_adsp_wdt_version_get(uint32_t base, const uint32_t core) in intel_adsp_wdt_version_get() argument
164 return FIELD_GET(DSPCxWDTIPPTR_VER, sys_read32(base + DSPCxWDTIPPTR + DSPBRx_OFFSET(core))); in intel_adsp_wdt_version_get()
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| D | wdt_mcux_imx_wdog.c | 22 WDOG_Type *base; member
37 WDOG_Type *base = config->base; in mcux_wdog_setup() local
50 WDOG_Init(base, &data->wdog_config); in mcux_wdog_setup()
60 WDOG_Type *base = config->base; in mcux_wdog_disable() local
62 WDOG_Deinit(base); in mcux_wdog_disable()
109 WDOG_Type *base = config->base; in mcux_wdog_feed() local
116 WDOG_Refresh(base); in mcux_wdog_feed()
126 WDOG_Type *base = config->base; in mcux_wdog_isr() local
129 flags = WDOG_GetStatusFlags(base); in mcux_wdog_isr()
130 WDOG_ClearInterruptStatus(base, flags); in mcux_wdog_isr()
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_gecko.c | 14 USART_TypeDef *base = (USART_TypeDef *)reg; in pinctrl_configure_pins() local
72 base->ROUTEPEN |= USART_ROUTEPEN_RXPEN; in pinctrl_configure_pins()
73 base->ROUTELOC0 &= ~_USART_ROUTELOC0_RXLOC_MASK; in pinctrl_configure_pins()
74 base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_RXLOC_SHIFT); in pinctrl_configure_pins()
78 base->ROUTEPEN |= USART_ROUTEPEN_TXPEN; in pinctrl_configure_pins()
79 base->ROUTELOC0 &= ~_USART_ROUTELOC0_TXLOC_MASK; in pinctrl_configure_pins()
80 base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_TXLOC_SHIFT); in pinctrl_configure_pins()
84 base->ROUTEPEN |= USART_ROUTEPEN_RTSPEN; in pinctrl_configure_pins()
85 base->ROUTELOC1 &= ~_USART_ROUTELOC1_RTSLOC_MASK; in pinctrl_configure_pins()
86 base->ROUTELOC1 |= (loc << _USART_ROUTELOC1_RTSLOC_SHIFT); in pinctrl_configure_pins()
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| /Zephyr-latest/include/zephyr/net/prometheus/ |
| D | gauge.h | 31 struct prometheus_metric base; member
61 .base.name = STRINGIFY(_name), \
62 .base.type = PROMETHEUS_GAUGE, \
63 .base.description = _desc, \
64 .base.labels[0] = __DEBRACKET _label, \
65 .base.num_labels = 1, \
66 .base.collector = _collector, \
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| D | histogram.h | 45 struct prometheus_metric base; member
81 .base.name = STRINGIFY(_name), \
82 .base.type = PROMETHEUS_HISTOGRAM, \
83 .base.description = _desc, \
84 .base.labels[0] = __DEBRACKET _label, \
85 .base.num_labels = 1, \
86 .base.collector = _collector, \
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| D | counter.h | 33 struct prometheus_metric base; member
62 .base.name = STRINGIFY(_name), \
63 .base.type = PROMETHEUS_COUNTER, \
64 .base.description = _desc, \
65 .base.labels[0] = __DEBRACKET _label, \
66 .base.num_labels = 1, \
67 .base.collector = _collector, \
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| D | summary.h | 47 struct prometheus_metric base; member
85 .base.name = STRINGIFY(_name), \
86 .base.type = PROMETHEUS_SUMMARY, \
87 .base.description = _desc, \
88 .base.labels[0] = __DEBRACKET _label, \
89 .base.num_labels = 1, \
90 .base.collector = _collector, \
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| /Zephyr-latest/drivers/counter/ |
| D | counter_mcux_gpt.c | 48 GPT_Type *base = get_base(dev); in mcux_gpt_start() local
50 GPT_StartTimer(base); in mcux_gpt_start()
57 GPT_Type *base = get_base(dev); in mcux_gpt_stop() local
59 GPT_StopTimer(base); in mcux_gpt_stop()
66 GPT_Type *base = get_base(dev); in mcux_gpt_get_value() local
68 *ticks = GPT_GetCurrentTimerCount(base); in mcux_gpt_get_value()
75 GPT_Type *base = get_base(dev); in mcux_gpt_set_alarm() local
78 uint32_t current = GPT_GetCurrentTimerCount(base); in mcux_gpt_set_alarm()
97 GPT_SetOutputCompareValue(base, kGPT_OutputCompare_Channel1, in mcux_gpt_set_alarm()
99 GPT_EnableInterrupts(base, kGPT_OutputCompare1InterruptEnable); in mcux_gpt_set_alarm()
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| /Zephyr-latest/drivers/mdio/ |
| D | mdio_nxp_enet_qos.c | 35 enet_qos_t *base; member
39 static bool check_busy(enet_qos_t *base) in check_busy() argument
41 uint32_t val = base->MAC_MDIO_ADDRESS; in check_busy()
49 enet_qos_t *base = mdio->base; in do_transaction() local
56 base->MAC_MDIO_DATA = in do_transaction()
67 base->MAC_MDIO_ADDRESS = in do_transaction()
76 base->MAC_MDIO_ADDRESS = in do_transaction()
83 if (!check_busy(base)) { in do_transaction()
96 uint32_t val = mdio->base->MAC_MDIO_DATA; in do_transaction()
115 enet_qos_t *base = ENET_QOS_MODULE_CFG(config->enet_dev)->base; in nxp_enet_qos_mdio_read() local
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| /Zephyr-latest/soc/sensry/ganymed/sy1xx/common/ |
| D | udma.c | 110 int32_t sy1xx_udma_cancel(uint32_t base, uint32_t channel) in sy1xx_udma_cancel() argument
115 SY1XX_UDMA_WRITE_REG(base, SY1XX_UDMA_CFG_REG + channel_offset, in sy1xx_udma_cancel()
120 int32_t sy1xx_udma_is_ready(uint32_t base, uint32_t channel) in sy1xx_udma_is_ready() argument
124 int32_t isBusy = SY1XX_UDMA_READ_REG(base, SY1XX_UDMA_CFG_REG + channel_offset) & in sy1xx_udma_is_ready()
130 int32_t sy1xx_udma_wait_for_finished(uint32_t base, uint32_t channel) in sy1xx_udma_wait_for_finished() argument
136 while (SY1XX_UDMA_READ_REG(base, SY1XX_UDMA_CFG_REG + channel_offset) & in sy1xx_udma_wait_for_finished()
148 int32_t sy1xx_udma_wait_for_status(uint32_t base) in sy1xx_udma_wait_for_status() argument
153 while (SY1XX_UDMA_READ_REG(base, SY1XX_UDMA_STATUS) & (0x3)) { in sy1xx_udma_wait_for_status()
164 int32_t sy1xx_udma_start(uint32_t base, uint32_t channel, uint32_t saddr, uint32_t size, in sy1xx_udma_start() argument
169 SY1XX_UDMA_WRITE_REG(base, SY1XX_UDMA_SADDR_REG + channel_offset, saddr); in sy1xx_udma_start()
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| D | udma.h | 91 int32_t sy1xx_udma_cancel(uint32_t base, uint32_t channel);
92 int32_t sy1xx_udma_is_ready(uint32_t base, uint32_t channel);
93 int32_t sy1xx_udma_wait_for_finished(uint32_t base, uint32_t channel);
94 int32_t sy1xx_udma_wait_for_status(uint32_t base);
95 int32_t sy1xx_udma_start(uint32_t base, uint32_t channel, uint32_t saddr, uint32_t size,
97 int32_t sy1xx_udma_get_remaining(uint32_t base, uint32_t channel);
140 #define SY1XX_UDMA_START_RX(base, addr, size, cfg) \ argument
141 sy1xx_udma_start(base, SY1XX_UDMA_RX_CHANNEL, addr, size, cfg)
142 #define SY1XX_UDMA_START_TX(base, addr, size, cfg) \ argument
143 sy1xx_udma_start(base, SY1XX_UDMA_TX_CHANNEL, addr, size, cfg)
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_ifx_cat1.c | 53 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_configure() local
85 Cy_GPIO_SetInterruptMask(base, pin, 0); in gpio_cat1_configure()
94 Cy_GPIO_Pin_FastInit(base, pin, drive_mode, pin_val, HSIOM_SEL_GPIO); in gpio_cat1_configure()
103 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_get_raw() local
105 *value = GPIO_PRT_IN(base); in gpio_cat1_port_get_raw()
114 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_set_masked_raw() local
116 GPIO_PRT_OUT(base) = (GPIO_PRT_OUT(base) & ~mask) | (mask & value); in gpio_cat1_port_set_masked_raw()
125 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_set_bits_raw() local
127 GPIO_PRT_OUT_SET(base) = mask; in gpio_cat1_port_set_bits_raw()
136 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_clear_bits_raw() local
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| D | gpio_si32.c | 22 SI32_PBSTD_A_Type *base; member
47 SI32_PBSTD_A_write_pins_high(config->base, BIT(pin)); in gpio_si32_configure()
49 SI32_PBSTD_A_write_pins_low(config->base, BIT(pin)); in gpio_si32_configure()
52 SI32_PBSTD_A_set_pins_push_pull_output(config->base, BIT(pin)); in gpio_si32_configure()
54 SI32_PBSTD_A_set_pins_digital_input(config->base, BIT(pin)); in gpio_si32_configure()
56 SI32_PBSTD_A_set_pins_analog(config->base, BIT(pin)); in gpio_si32_configure()
63 config->base->PM_SET = BIT(pin); in gpio_si32_configure()
65 config->base->PM_CLR = BIT(pin); in gpio_si32_configure()
77 *value = SI32_PBSTD_A_read_pins(config->base); in gpio_si32_port_get_raw()
87 SI32_PBSTD_A_write_pins_masked(config->base, value, mask); in gpio_si32_port_set_masked_raw()
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| D | gpio_mcux_igpio.c | 55 GPIO_Type *base = get_base(dev); in mcux_igpio_configure() local
207 GPIO_WritePinOutput(base, pin, 1); in mcux_igpio_configure()
211 GPIO_WritePinOutput(base, pin, 0); in mcux_igpio_configure()
214 WRITE_BIT(base->GDIR, pin, flags & GPIO_OUTPUT); in mcux_igpio_configure()
221 GPIO_Type *base = get_base(dev); in mcux_igpio_port_get_raw() local
223 *value = base->DR; in mcux_igpio_port_get_raw()
232 GPIO_Type *base = get_base(dev); in mcux_igpio_port_set_masked_raw() local
234 base->DR = (base->DR & ~mask) | (mask & value); in mcux_igpio_port_set_masked_raw()
242 GPIO_Type *base = get_base(dev); in mcux_igpio_port_set_bits_raw() local
244 GPIO_PortSet(base, mask); in mcux_igpio_port_set_bits_raw()
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| D | gpio_brcmstb.c | 32 mem_addr_t base; member
44 sys_set_bit(data->base + GIO_IODIR, pin); in gpio_brcmstb_pin_configure()
46 sys_clear_bit(data->base + GIO_IODIR, pin); in gpio_brcmstb_pin_configure()
49 sys_set_bit(data->base + GIO_DATA, pin); in gpio_brcmstb_pin_configure()
51 sys_clear_bit(data->base + GIO_DATA, pin); in gpio_brcmstb_pin_configure()
62 *value = sys_read32(data->base + GIO_DATA); in gpio_brcmstb_port_get_raw()
72 sys_clear_bits(data->base + GIO_DATA, mask); in gpio_brcmstb_port_set_masked_raw()
73 sys_set_bits(data->base + GIO_DATA, (value & mask)); in gpio_brcmstb_port_set_masked_raw()
82 sys_set_bits(data->base + GIO_DATA, pins); in gpio_brcmstb_port_set_bits_raw()
91 sys_clear_bits(data->base + GIO_DATA, pins); in gpio_brcmstb_port_clear_bits_raw()
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_xilinx_axi.c | 21 mem_addr_t base; member
45 sys_write32(SOFTR_KEY, config->base + REG_SOFTR); in i2c_xilinx_axi_reinit()
46 sys_write32(CR_TX_FIFO_RST, config->base + REG_CR); in i2c_xilinx_axi_reinit()
47 sys_write32(CR_EN, config->base + REG_CR); in i2c_xilinx_axi_reinit()
48 sys_write32(GIE_ENABLE, config->base + REG_GIE); in i2c_xilinx_axi_reinit()
62 sys_write32(ISR_ADDR_TARGET, config->base + REG_IER); in i2c_xilinx_axi_target_setup()
63 sys_write32(cfg->address << 1, config->base + REG_ADR); in i2c_xilinx_axi_target_setup()
64 sys_write32(0, config->base + REG_RX_FIFO_PIRQ); in i2c_xilinx_axi_target_setup()
120 sys_write32(0, config->base + REG_ADR); in i2c_xilinx_axi_target_unregister()
122 sys_write32(CR_EN, config->base + REG_CR); in i2c_xilinx_axi_target_unregister()
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| D | i2c_gecko.c | 26 #define DEV_BASE(dev) ((I2C_TypeDef *)((const struct i2c_gecko_config *const)(dev)->config)->base)
30 I2C_TypeDef *base; member
49 I2C_TypeDef *base = DEV_BASE(dev); in i2c_gecko_configure() local
81 I2C_Init(base, &i2cInit); in i2c_gecko_configure()
91 I2C_TypeDef *base = DEV_BASE(dev); in i2c_gecko_transfer() local
132 ret = I2C_TransferInit(base, &seq); in i2c_gecko_transfer()
134 ret = I2C_Transfer(base); in i2c_gecko_transfer()
193 I2C_SlaveAddressSet(config->base, cfg->address << _I2C_SADDR_ADDR_SHIFT); in i2c_gecko_target_register()
195 I2C_SlaveAddressMaskSet(config->base, _I2C_SADDRMASK_SADDRMASK_MASK); in i2c_gecko_target_register()
197 I2C_IntDisable(config->base, _I2C_IEN_MASK); in i2c_gecko_target_register()
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| /Zephyr-latest/drivers/ethernet/eth_nxp_enet_qos/ |
| D | eth_nxp_enet_qos_mac.c | 59 enet_qos_t *base = config->base; in eth_nxp_enet_qos_tx() local
123 base->DMA_CH[0].DMA_CHX_TXDESC_RING_LENGTH = frags_count - 1; in eth_nxp_enet_qos_tx()
124 base->DMA_CH[0].DMA_CHX_TXDESC_TAIL_PTR = in eth_nxp_enet_qos_tx()
249 enet_qos_t *base = config->base; in eth_nxp_enet_qos_mac_isr() local
252 volatile uint32_t mac_interrupts = base->MAC_INTERRUPT_STATUS; in eth_nxp_enet_qos_mac_isr()
253 volatile uint32_t mac_rx_tx_status = base->MAC_RX_TX_STATUS; in eth_nxp_enet_qos_mac_isr()
254 volatile uint32_t dma_interrupts = base->DMA_INTERRUPT_STATUS; in eth_nxp_enet_qos_mac_isr()
255 volatile uint32_t dma_ch0_interrupts = base->DMA_CH[0].DMA_CHX_STAT; in eth_nxp_enet_qos_mac_isr()
259 base->DMA_CH[0].DMA_CHX_STAT = 0xFFFFFFFF; in eth_nxp_enet_qos_mac_isr()
290 static inline int enet_qos_dma_reset(enet_qos_t *base) in enet_qos_dma_reset() argument
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| /Zephyr-latest/drivers/dai/nxp/esai/ |
| D | esai.h | 423 static inline void esai_tx_rx_enable_disable_fifo(ESAI_Type *base, in esai_tx_rx_enable_disable_fifo() argument
429 base->RFCR |= ESAI_RFCR_RFE_MASK; in esai_tx_rx_enable_disable_fifo()
431 base->TFCR |= ESAI_TFCR_TFE_MASK; in esai_tx_rx_enable_disable_fifo()
435 base->RFCR &= ~ESAI_RFCR_RFE_MASK; in esai_tx_rx_enable_disable_fifo()
437 base->TFCR &= ~ESAI_TFCR_TFE_MASK; in esai_tx_rx_enable_disable_fifo()
442 static inline void esai_tx_rx_enable_disable(ESAI_Type *base, in esai_tx_rx_enable_disable() argument
450 base->RCR |= val; in esai_tx_rx_enable_disable()
452 base->TCR |= val; in esai_tx_rx_enable_disable()
456 base->RCR &= ~val; in esai_tx_rx_enable_disable()
458 base->TCR &= ~val; in esai_tx_rx_enable_disable()
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| /Zephyr-latest/subsys/net/lib/prometheus/ |
| D | collector.c | 51 LOG_DBG("entry->name: %s", entry->base.name); in prometheus_get_counter_metric()
53 if (strncmp(entry->base.name, name, strlen(entry->base.name)) == 0) { in prometheus_get_counter_metric()
54 LOG_DBG("Counter found %s", entry->base.name); in prometheus_get_counter_metric()
67 LOG_DBG("entry->name: %s", entry->base.name); in prometheus_get_gauge_metric()
69 if (strncmp(entry->base.name, name, strlen(entry->base.name)) == 0) { in prometheus_get_gauge_metric()
70 LOG_DBG("Counter found %s", entry->base.name); in prometheus_get_gauge_metric()
83 LOG_DBG("entry->name: %s", entry->base.name); in prometheus_get_histogram_metric()
85 if (strncmp(entry->base.name, name, strlen(entry->base.name)) == 0) { in prometheus_get_histogram_metric()
86 LOG_DBG("Counter found %s", entry->base.name); in prometheus_get_histogram_metric()
99 LOG_DBG("entry->name: %s", entry->base.name); in prometheus_get_summary_metric()
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| /Zephyr-latest/lib/utils/ |
| D | timeutil.c | 80 if (((tsp->base.ref == 0) && (inst->ref > 0)) in timeutil_sync_state_update()
81 || ((inst->ref > tsp->base.ref) in timeutil_sync_state_update()
82 && (inst->local > tsp->base.local))) { in timeutil_sync_state_update()
83 if (tsp->base.ref == 0) { in timeutil_sync_state_update()
84 tsp->base = *inst; in timeutil_sync_state_update()
98 const struct timeutil_sync_instant *base) in timeutil_sync_state_set_skew() argument
104 if (base != NULL) { in timeutil_sync_state_set_skew()
105 tsp->base = *base; in timeutil_sync_state_set_skew()
118 if ((tsp->base.ref != 0) && (tsp->latest.ref != 0) in timeutil_sync_estimate_skew()
119 && (tsp->latest.local > tsp->base.local)) { in timeutil_sync_estimate_skew()
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| /Zephyr-latest/drivers/serial/ |
| D | uart_cc32xx.c | 23 unsigned long base; member
71 MAP_UARTConfigSetExpClk(config->base, in uart_cc32xx_init()
76 MAP_UARTFlowControlSet(config->base, UART_FLOWCONTROL_NONE); in uart_cc32xx_init()
78 MAP_UARTFIFODisable(config->base); in uart_cc32xx_init()
82 MAP_UARTIntClear(config->base, UART_INT_RX); in uart_cc32xx_init()
90 MAP_UARTCharPutNonBlocking(config->base, PRIME_CHAR); in uart_cc32xx_init()
99 if (MAP_UARTCharsAvail(config->base)) { in uart_cc32xx_poll_in()
100 *c = MAP_UARTCharGetNonBlocking(config->base); in uart_cc32xx_poll_in()
111 MAP_UARTCharPut(config->base, c); in uart_cc32xx_poll_out()
120 cc32xx_errs = MAP_UARTRxErrorGet(config->base); in uart_cc32xx_err_check()
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| D | uart_mcux_iuart.c | 18 UART_Type *base; member
42 if (UART_GetStatusFlag(config->base, kUART_RxDataReadyFlag)) { in mcux_iuart_poll_in()
43 *c = UART_ReadByte(config->base); in mcux_iuart_poll_in()
54 while (!(UART_GetStatusFlag(config->base, kUART_TxReadyFlag))) { in mcux_iuart_poll_out()
57 UART_WriteByte(config->base, c); in mcux_iuart_poll_out()
65 if (UART_GetStatusFlag(config->base, kUART_RxOverrunFlag)) { in mcux_iuart_err_check()
67 UART_ClearStatusFlag(config->base, kUART_RxOverrunFlag); in mcux_iuart_err_check()
70 if (UART_GetStatusFlag(config->base, kUART_ParityErrorFlag)) { in mcux_iuart_err_check()
72 UART_ClearStatusFlag(config->base, kUART_ParityErrorFlag); in mcux_iuart_err_check()
75 if (UART_GetStatusFlag(config->base, kUART_FrameErrorFlag)) { in mcux_iuart_err_check()
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| D | uart_psoc6.c | 45 CySCB_Type *base; member
124 (void) Cy_SCB_UART_Init(config->base, &uartConfig, NULL); in uart_psoc6_init()
125 Cy_SCB_UART_Enable(config->base); in uart_psoc6_init()
139 rec = Cy_SCB_UART_Get(config->base); in uart_psoc6_poll_in()
149 while (Cy_SCB_UART_Put(config->base, (uint32_t)c) != 1UL) { in uart_psoc6_poll_out()
156 uint32_t status = Cy_SCB_UART_GetRxFifoStatus(config->base); in uart_psoc6_err_check()
182 return Cy_SCB_UART_PutArray(config->base, (uint8_t *) tx_data, size); in uart_psoc6_fifo_fill()
191 return Cy_SCB_UART_GetArray(config->base, rx_data, size); in uart_psoc6_fifo_read()
198 Cy_SCB_SetTxInterruptMask(config->base, CY_SCB_UART_TX_EMPTY); in uart_psoc6_irq_tx_enable()
205 Cy_SCB_SetTxInterruptMask(config->base, 0); in uart_psoc6_irq_tx_disable()
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_imx.c | 24 PWM_Type *base; member
34 static bool imx_pwm_is_enabled(PWM_Type *base) in imx_pwm_is_enabled() argument
36 return PWM_PWMCR_REG(base) & PWM_PWMCR_EN_MASK; in imx_pwm_is_enabled()
44 *cycles = get_pwm_clock_freq(config->base) >> config->prescaler; in imx_pwm_get_cycles_per_sec()
56 bool enabled = imx_pwm_is_enabled(config->base); in imx_pwm_set_cycles()
83 sr = PWM_PWMSR_REG(config->base); in imx_pwm_set_cycles()
86 period_ms = (get_pwm_clock_freq(config->base) >> in imx_pwm_set_cycles()
90 sr = PWM_PWMSR_REG(config->base); in imx_pwm_set_cycles()
96 PWM_PWMCR_REG(config->base) = PWM_PWMCR_SWR(1); in imx_pwm_set_cycles()
99 cr = PWM_PWMCR_REG(config->base); in imx_pwm_set_cycles()
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