Lines Matching refs:base
110 int32_t sy1xx_udma_cancel(uint32_t base, uint32_t channel) in sy1xx_udma_cancel() argument
115 SY1XX_UDMA_WRITE_REG(base, SY1XX_UDMA_CFG_REG + channel_offset, in sy1xx_udma_cancel()
120 int32_t sy1xx_udma_is_ready(uint32_t base, uint32_t channel) in sy1xx_udma_is_ready() argument
124 int32_t isBusy = SY1XX_UDMA_READ_REG(base, SY1XX_UDMA_CFG_REG + channel_offset) & in sy1xx_udma_is_ready()
130 int32_t sy1xx_udma_wait_for_finished(uint32_t base, uint32_t channel) in sy1xx_udma_wait_for_finished() argument
136 while (SY1XX_UDMA_READ_REG(base, SY1XX_UDMA_CFG_REG + channel_offset) & in sy1xx_udma_wait_for_finished()
148 int32_t sy1xx_udma_wait_for_status(uint32_t base) in sy1xx_udma_wait_for_status() argument
153 while (SY1XX_UDMA_READ_REG(base, SY1XX_UDMA_STATUS) & (0x3)) { in sy1xx_udma_wait_for_status()
164 int32_t sy1xx_udma_start(uint32_t base, uint32_t channel, uint32_t saddr, uint32_t size, in sy1xx_udma_start() argument
169 SY1XX_UDMA_WRITE_REG(base, SY1XX_UDMA_SADDR_REG + channel_offset, saddr); in sy1xx_udma_start()
170 SY1XX_UDMA_WRITE_REG(base, SY1XX_UDMA_SIZE_REG + channel_offset, size); in sy1xx_udma_start()
171 SY1XX_UDMA_WRITE_REG(base, SY1XX_UDMA_CFG_REG + channel_offset, in sy1xx_udma_start()
177 int32_t sy1xx_udma_get_remaining(uint32_t base, uint32_t channel) in sy1xx_udma_get_remaining() argument
181 int32_t size = SY1XX_UDMA_READ_REG(base, SY1XX_UDMA_SIZE_REG + channel_offset); in sy1xx_udma_get_remaining()