21 	mem_addr_t base;  member
45 	sys_write32(SOFTR_KEY, config->base + REG_SOFTR);  in i2c_xilinx_axi_reinit()
46 	sys_write32(CR_TX_FIFO_RST, config->base + REG_CR);  in i2c_xilinx_axi_reinit()
47 	sys_write32(CR_EN, config->base + REG_CR);  in i2c_xilinx_axi_reinit()
48 	sys_write32(GIE_ENABLE, config->base + REG_GIE);  in i2c_xilinx_axi_reinit()
62 	sys_write32(ISR_ADDR_TARGET, config->base + REG_IER);  in i2c_xilinx_axi_target_setup()
63 	sys_write32(cfg->address << 1, config->base + REG_ADR);  in i2c_xilinx_axi_target_setup()
64 	sys_write32(0, config->base + REG_RX_FIFO_PIRQ);  in i2c_xilinx_axi_target_setup()
120 	sys_write32(0, config->base + REG_ADR);  in i2c_xilinx_axi_target_unregister()
122 	sys_write32(CR_EN, config->base + REG_CR);  in i2c_xilinx_axi_target_unregister()
123 	int_enable = sys_read32(config->base + REG_IER);  in i2c_xilinx_axi_target_unregister()
125 	sys_write32(int_enable, config->base + REG_IER);  in i2c_xilinx_axi_target_unregister()
146 		if (sys_read32(config->base + REG_SR) & SR_SRW) {  in i2c_xilinx_axi_target_isr()
158 			sys_write32(read_byte, config->base + REG_TX_FIFO);  in i2c_xilinx_axi_target_isr()
163 				uint32_t cr = sys_read32(config->base + REG_CR);  in i2c_xilinx_axi_target_isr()
167 				sys_write32(cr, config->base + REG_CR);  in i2c_xilinx_axi_target_isr()
177 		sys_write32(CR_EN, config->base + REG_CR);  in i2c_xilinx_axi_target_isr()
185 			sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK;  in i2c_xilinx_axi_target_isr()
189 			uint32_t cr = sys_read32(config->base + REG_CR);  in i2c_xilinx_axi_target_isr()
193 			sys_write32(cr, config->base + REG_CR);  in i2c_xilinx_axi_target_isr()
213 		sys_write32(read_byte, config->base + REG_TX_FIFO);  in i2c_xilinx_axi_target_isr()
223 	uint32_t int_enable = sys_read32(config->base + REG_IER);  in i2c_xilinx_axi_isr()
224 	uint32_t int_status = sys_read32(config->base + REG_ISR) & int_enable;  in i2c_xilinx_axi_isr()
227 	LOG_DBG("ISR called for 0x%08" PRIxPTR ", status 0x%02x", config->base, int_status);  in i2c_xilinx_axi_isr()
231 		uint32_t cr = sys_read32(config->base + REG_CR);  in i2c_xilinx_axi_isr()
234 		sys_write32(cr, config->base + REG_CR);  in i2c_xilinx_axi_isr()
245 	sys_write32(int_enable & ~int_status, config->base + REG_IER);  in i2c_xilinx_axi_isr()
247 	sys_write32(ints_to_clear & sys_read32(config->base + REG_ISR), config->base + REG_ISR);  in i2c_xilinx_axi_isr()
259 	LOG_INF("Configuring %s at 0x%08" PRIxPTR, dev->name, config->base);  in i2c_xilinx_axi_configure()
268 	const uint32_t int_enable = sys_read32(config->base + REG_IER) | int_mask;  in i2c_xilinx_axi_wait_interrupt()
272 	sys_write32(int_enable, config->base + REG_IER);  in i2c_xilinx_axi_wait_interrupt()
281 			sys_read32(config->base + REG_SR), sys_read32(config->base + REG_ISR));  in i2c_xilinx_axi_wait_interrupt()
290 	const uint32_t int_status = sys_read32(config->base + REG_ISR);  in i2c_xilinx_axi_clear_interrupt()
293 		sys_write32(int_status & int_mask, config->base + REG_ISR);  in i2c_xilinx_axi_clear_interrupt()
304 	if (!(sys_read32(config->base + REG_SR) & SR_RX_FIFO_EMPTY) &&  in i2c_xilinx_axi_wait_rx_full()
305 	    (sys_read32(config->base + REG_RX_FIFO_OCY) & RX_FIFO_OCY_MASK) + 1 >= read_bytes) {  in i2c_xilinx_axi_wait_rx_full()
307 			sys_read32(config->base + REG_SR),  in i2c_xilinx_axi_wait_rx_full()
308 			sys_read32(config->base + REG_RX_FIFO_OCY));  in i2c_xilinx_axi_wait_rx_full()
356 	sys_write32(0, config->base + REG_RX_FIFO_PIRQ);  in i2c_xilinx_axi_read_nondyn()
361 		sys_write32(cr, config->base + REG_CR);  in i2c_xilinx_axi_read_nondyn()
362 		sys_write32((addr << 1) | I2C_MSG_READ, config->base + REG_TX_FIFO);  in i2c_xilinx_axi_read_nondyn()
364 		sys_write32((addr << 1) | I2C_MSG_READ, config->base + REG_TX_FIFO);  in i2c_xilinx_axi_read_nondyn()
365 		sys_write32(cr, config->base + REG_CR);  in i2c_xilinx_axi_read_nondyn()
383 		sys_write32(cr, config->base + REG_CR);  in i2c_xilinx_axi_read_nondyn()
385 		*read_ptr++ = sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK;  in i2c_xilinx_axi_read_nondyn()
407 	sys_write32(cr, config->base + REG_CR);  in i2c_xilinx_axi_read_dyn()
412 	sys_write32(bytes_to_read - 1, config->base + REG_RX_FIFO_PIRQ);  in i2c_xilinx_axi_read_dyn()
413 	sys_write32((addr << 1) | I2C_MSG_READ | TX_FIFO_START, config->base + REG_TX_FIFO);  in i2c_xilinx_axi_read_dyn()
418 	sys_write32(len_word, config->base + REG_TX_FIFO);  in i2c_xilinx_axi_read_dyn()
428 		sys_write32(bytes_to_read - 1, config->base + REG_RX_FIFO_PIRQ);  in i2c_xilinx_axi_read_dyn()
435 			*read_ptr++ = sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK;  in i2c_xilinx_axi_read_dyn()
467 	if (sys_read32(config->base + REG_SR) & SR_BB) {  in i2c_xilinx_axi_wait_not_busy()
494 	sys_write32(cr, config->base + REG_CR);  in i2c_xilinx_axi_write()
495 	sys_write32((addr << 1) | TX_FIFO_START, config->base + REG_TX_FIFO);  in i2c_xilinx_axi_write()
520 			sys_write32(write_word, config->base + REG_TX_FIFO);  in i2c_xilinx_axi_write()
639 		.base = DT_INST_REG_ADDR(n),                                                       \