| /Zephyr-latest/drivers/i2c/ |
| D | i2c_cc32xx.c | 44 (((const struct i2c_cc32xx_config *const)(dev)->config)->base)
65 uint32_t base; member
87 uint32_t base = DEV_BASE(dev); in i2c_cc32xx_configure() local
109 MAP_I2CMasterInitExpClk(base, I2C_CLK_FREQ(0), bitrate_id); in i2c_cc32xx_configure()
119 uint32_t base = DEV_BASE(dev); in i2c_cc32xx_prime_transfer() local
129 MAP_I2CMasterSlaveAddrSet(base, addr, false); in i2c_cc32xx_prime_transfer()
135 MAP_I2CMasterDataPut(base, *((data->msg.buf)++)); in i2c_cc32xx_prime_transfer()
138 MAP_I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_START); in i2c_cc32xx_prime_transfer()
143 MAP_I2CMasterSlaveAddrSet(base, addr, true); in i2c_cc32xx_prime_transfer()
150 MAP_I2CMasterControl(base, in i2c_cc32xx_prime_transfer()
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| D | i2c_imx.c | 24 ((I2C_Type *)((const struct i2c_imx_config * const)(dev)->config)->base)
27 I2C_Type *base; member
53 I2C_Type *base = DEV_BASE(dev); in i2c_imx_write() local
60 I2C_ClearStatusFlag(base, i2cStatusInterrupt); in i2c_imx_write()
63 I2C_SetDirMode(base, i2cDirectionTransmit); in i2c_imx_write()
69 I2C_WriteByte(base, *transfer->txBuff); in i2c_imx_write()
76 I2C_SetIntCmd(base, true); in i2c_imx_write()
87 I2C_Type *base = DEV_BASE(dev); in i2c_imx_read() local
94 I2C_ClearStatusFlag(base, i2cStatusInterrupt); in i2c_imx_read()
97 I2C_SetDirMode(base, i2cDirectionReceive); in i2c_imx_read()
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| D | i2c_ite_it8xxx2.c | 43 uint8_t *base; member
169 uint8_t *base = config->base; in i2c_get_line_levels() local
171 return (IT8XXX2_SMB_SMBPCTL(base) & in i2c_get_line_levels()
178 uint8_t *base = config->base; in i2c_is_busy() local
180 return (IT8XXX2_SMB_HOSTA(base) & in i2c_is_busy()
197 uint8_t *base = config->base; in i2c_reset() local
200 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_KILL; in i2c_reset()
201 IT8XXX2_SMB_HOCTL(base) = 0; in i2c_reset()
203 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT; in i2c_reset()
325 uint8_t *base = config->base; in i2c_r_last_byte() local
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| D | i2c_cc13xx_cc26xx.c | 39 uint32_t base; member
48 const uint32_t base = config->base; in i2c_cc13xx_cc26xx_transmit() local
56 I2CMasterSlaveAddrSet(base, addr, false); in i2c_cc13xx_cc26xx_transmit()
64 I2CMasterDataPut(base, *buf); in i2c_cc13xx_cc26xx_transmit()
66 I2CMasterControl(base, I2C_MASTER_CMD_SINGLE_SEND); in i2c_cc13xx_cc26xx_transmit()
74 I2CMasterDataPut(base, buf[0]); in i2c_cc13xx_cc26xx_transmit()
76 I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_START); in i2c_cc13xx_cc26xx_transmit()
85 I2CMasterDataPut(base, buf[i]); in i2c_cc13xx_cc26xx_transmit()
87 I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_CONT); in i2c_cc13xx_cc26xx_transmit()
96 I2CMasterDataPut(base, buf[len - 1]); in i2c_cc13xx_cc26xx_transmit()
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| D | i2c_bcm_iproc.c | 153 #define DEV_BASE(dev) ((DEV_CFG(dev))->base)
156 mem_addr_t base; member
177 mem_addr_t base = DEV_BASE(dev); in iproc_i2c_enable_disable() local
180 val = sys_read32(base + CFG_OFFSET); in iproc_i2c_enable_disable()
186 sys_write32(val, base + CFG_OFFSET); in iproc_i2c_enable_disable()
191 mem_addr_t base = DEV_BASE(dev); in iproc_i2c_reset_controller() local
195 val = sys_read32(base + CFG_OFFSET); in iproc_i2c_reset_controller()
198 sys_write32(val, base + CFG_OFFSET); in iproc_i2c_reset_controller()
203 sys_clear_bit(base + CFG_OFFSET, CFG_RESET_SHIFT); in iproc_i2c_reset_controller()
210 mem_addr_t base = DEV_BASE(dev); in iproc_i2c_target_set_address() local
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| D | i2c_ite_enhance.c | 63 uint8_t *base; member
253 uint8_t *base = config->base; in i2c_get_line_levels() local
256 if (IT8XXX2_I2C_TOS(base) & IT8XXX2_I2C_SCL_IN) { in i2c_get_line_levels()
260 if (IT8XXX2_I2C_TOS(base) & IT8XXX2_I2C_SDA_IN) { in i2c_get_line_levels()
270 uint8_t *base = config->base; in i2c_is_busy() local
272 return (IT8XXX2_I2C_STR(base) & E_HOSTA_BB); in i2c_is_busy()
288 uint8_t *base = config->base; in i2c_reset() local
291 IT8XXX2_I2C_CTR(base) = E_STS_AND_HW_RST; in i2c_reset()
300 uint8_t *base = config->base; in i2c_enhanced_port_set_frequency() local
343 IT8XXX2_I2C_PSR(base) = psr_l & 0xFF; in i2c_enhanced_port_set_frequency()
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_imx.c | 24 GPIO_Type *base; member
40 GPIO_Type *base = config->base; in imx_gpio_configure() local
95 GPIO_SetPinIntMode(base, pin, false); in imx_gpio_configure()
96 GPIO_SetIntEdgeSelect(base, pin, false); in imx_gpio_configure()
101 GPIO_WritePinOutput(base, pin, gpioPinClear); in imx_gpio_configure()
103 GPIO_WritePinOutput(base, pin, gpioPinSet); in imx_gpio_configure()
107 WRITE_BIT(base->GDIR, pin, 1U); in imx_gpio_configure()
110 WRITE_BIT(base->GDIR, pin, 0U); in imx_gpio_configure()
121 GPIO_Type *base = config->base; in imx_gpio_port_get_raw() local
123 *value = GPIO_ReadPortInput(base); in imx_gpio_port_get_raw()
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| /Zephyr-latest/drivers/counter/ |
| D | counter_mcux_tpm.c | 50 TPM_Type *base = get_base(dev); in mcux_tpm_start() local
52 TPM_StartTimer(base, config->tpm_clock_source); in mcux_tpm_start()
59 TPM_Type *base = get_base(dev); in mcux_tpm_stop() local
61 TPM_StopTimer(base); in mcux_tpm_stop()
68 TPM_Type *base = get_base(dev); in mcux_tpm_get_value() local
70 *ticks = TPM_GetCurrentTimerCount(base); in mcux_tpm_get_value()
78 TPM_Type *base = get_base(dev); in mcux_tpm_set_alarm() local
79 uint32_t current = TPM_GetCurrentTimerCount(base); in mcux_tpm_set_alarm()
80 uint32_t top_value = base->MOD; in mcux_tpm_set_alarm()
108 TPM_SetupOutputCompare(base, kTPM_Chnl_0, kTPM_NoOutputSignal, ticks); in mcux_tpm_set_alarm()
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| D | counter_nxp_mrt.c | 54 MRT_Type *base; member
66 MRT_Type *base = config->base; in nxp_mrt_stop() local
69 LOG_DBG("MRT@%p channel %d stopped", base, channel_id); in nxp_mrt_stop()
73 base->CHANNEL[channel_id].INTVAL = MRT_CHANNEL_INTVAL_LOAD(1); in nxp_mrt_stop()
81 MRT_Type *base = config->base; in nxp_mrt_start() local
88 base, channel_id, config->info.max_top_value); in nxp_mrt_start()
93 base->CHANNEL[channel_id].INTVAL = data->top; in nxp_mrt_start()
95 LOG_DBG("MRT@%p channel %d started with top value %d", base, channel_id, data->top); in nxp_mrt_start()
103 MRT_Type *base = config->base; in nxp_mrt_get_value() local
106 *ticks = base->CHANNEL[channel_id].TIMER & MRT_CHANNEL_TIMER_VALUE_MASK; in nxp_mrt_get_value()
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| D | counter_mcux_rtc.c | 28 RTC_Type *base; member
38 RTC_StartTimer(config->base); in mcux_rtc_start()
39 RTC_EnableInterrupts(config->base, in mcux_rtc_start()
53 RTC_DisableInterrupts(config->base, in mcux_rtc_stop()
57 RTC_StopTimer(config->base); in mcux_rtc_stop()
60 config->base->TAR = 0; in mcux_rtc_stop()
71 uint32_t ticks = config->base->TSR; in mcux_rtc_read()
78 if (config->base->TSR == ticks) { in mcux_rtc_read()
82 ticks = config->base->TSR; in mcux_rtc_read()
127 config->base->TAR = ticks; in mcux_rtc_set_alarm()
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| /Zephyr-latest/drivers/serial/ |
| D | leuart_gecko.c | 24 ((const struct leuart_gecko_config * const)(dev)->config)->base)
27 LEUART_TypeDef *base; member
52 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_poll_in() local
53 uint32_t flags = LEUART_StatusGet(base); in leuart_gecko_poll_in()
56 *c = LEUART_Rx(base); in leuart_gecko_poll_in()
65 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_poll_out() local
70 LEUART_Tx(base, c); in leuart_gecko_poll_out()
75 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_err_check() local
76 uint32_t flags = LEUART_IntGet(base); in leuart_gecko_err_check()
91 LEUART_IntClear(base, LEUART_IF_RXOF | in leuart_gecko_err_check()
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| D | uart_opentitan.c | 39 mem_addr_t base; member
48 sys_write32(0u, cfg->base + UART_CTRL_REG_OFFSET); in uart_opentitan_init()
52 cfg->base + UART_FIFO_CTRL_REG_OFFSET); in uart_opentitan_init()
55 sys_write32(0u, cfg->base + UART_OVRD_REG_OFFSET); in uart_opentitan_init()
56 sys_write32(0u, cfg->base + UART_TIMEOUT_CTRL_REG_OFFSET); in uart_opentitan_init()
59 sys_write32(0u, cfg->base + UART_INTR_ENABLE_REG_OFFSET); in uart_opentitan_init()
62 sys_write32(0xffffffffu, cfg->base + UART_INTR_STATE_REG_OFFSET); in uart_opentitan_init()
67 cfg->base + UART_CTRL_REG_OFFSET); in uart_opentitan_init()
75 if (sys_read32(cfg->base + UART_STATUS_REG_OFFSET) & UART_STATUS_RXEMPTY_BIT) { in uart_opentitan_poll_in()
79 *c = sys_read32(cfg->base + UART_RDATA_REG_OFFSET); in uart_opentitan_poll_in()
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| /Zephyr-latest/tests/drivers/gnss/gnss_parse/src/ |
| D | main.c | 13 uint8_t base; member
18 {.str = "10", .base = 10, .value = 10},
19 {.str = "1", .base = 10, .value = 1},
20 {.str = "002", .base = 10, .value = 2},
21 {.str = "-10", .base = 10, .value = -10},
22 {.str = "-1", .base = 10, .value = -1},
23 {.str = "-002", .base = 10, .value = -2},
24 {.str = "30000000", .base = 10, .value = 30000000},
25 {.str = "-30000000", .base = 10, .value = -30000000},
26 {.str = "00", .base = 16, .value = 0},
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_dw_common.c | 33 int dw_wdt_configure(const uint32_t base, const uint32_t config) in dw_wdt_configure() argument
45 if (dw_wdt_dual_timeout_period_get(base)) { in dw_wdt_configure()
46 dw_wdt_timeout_period_init_set(base, period); in dw_wdt_configure()
49 dw_wdt_timeout_period_set(base, period); in dw_wdt_configure()
52 dw_wdt_enable(base); in dw_wdt_configure()
53 dw_wdt_counter_restart(base); in dw_wdt_configure()
58 int dw_wdt_calc_period(const uint32_t base, const uint32_t clk_freq, in dw_wdt_calc_period() argument
80 if (period >= dw_wdt_cnt_width_get(base)) { in dw_wdt_calc_period()
90 int dw_wdt_probe(const uint32_t base, const uint32_t reset_pulse_length) in dw_wdt_probe() argument
93 const uint32_t type = dw_wdt_comp_type_get(base); in dw_wdt_probe()
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| /Zephyr-latest/lib/libc/minimal/source/stdlib/ |
| D | strtoul.c | 43 unsigned long strtoul(const char *nptr, char **endptr, register int base) in strtoul() argument
64 if (((base == 0) || (base == 16)) && in strtoul()
68 base = 16; in strtoul()
71 if (base == 0) { in strtoul()
72 base = (c == '0') ? 8 : 10; in strtoul()
75 cutoff = (unsigned long)ULONG_MAX / (unsigned long)base; in strtoul()
76 cutlim = (unsigned long)ULONG_MAX % (unsigned long)base; in strtoul()
85 if (c >= base) { in strtoul()
92 acc *= base; in strtoul()
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| D | strtoull.c | 43 unsigned long long strtoull(const char *nptr, char **endptr, register int base) in strtoull() argument
64 if ((base == 0 || base == 16) && c == '0' && (*s == 'x' || *s == 'X')) { in strtoull()
67 base = 16; in strtoull()
70 if (base == 0) { in strtoull()
71 base = c == '0' ? 8 : 10; in strtoull()
74 cutoff = (unsigned long long)ULLONG_MAX / (unsigned long long)base; in strtoull()
75 cutlim = (unsigned long long)ULLONG_MAX % (unsigned long long)base; in strtoull()
84 if (c >= base) { in strtoull()
91 acc *= base; in strtoull()
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| D | strtol.c | 43 long strtol(const char *nptr, char **endptr, register int base) in strtol() argument
66 if (((base == 0) || (base == 16)) && in strtol()
70 base = 16; in strtol()
73 if (base == 0) { in strtol()
74 base = (c == '0') ? 8 : 10; in strtol()
95 cutlim = cutoff % (unsigned long)base; in strtol()
96 cutoff /= (unsigned long)base; in strtol()
105 if (c >= base) { in strtol()
112 acc *= base; in strtol()
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| D | strtoll.c | 43 long long strtoll(const char *nptr, char **endptr, register int base) in strtoll() argument
66 if ((base == 0 || base == 16) && c == '0' && (*s == 'x' || *s == 'X')) { in strtoll()
69 base = 16; in strtoll()
72 if (base == 0) { in strtoll()
73 base = c == '0' ? 8 : 10; in strtoll()
94 cutlim = cutoff % (unsigned long long)base; in strtoll()
95 cutoff /= (unsigned long long)base; in strtoll()
104 if (c >= base) { in strtoll()
111 acc *= base; in strtoll()
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| /Zephyr-latest/drivers/timer/ |
| D | mcux_gpt_timer.c | 47 static GPT_Type *base; variable
59 GPT_SetOutputCompareValue(base, kGPT_OutputCompare_Channel2, next - 1); in gpt_set_safe()
60 now = GPT_GetCurrentTimerCount(base); in gpt_set_safe()
77 GPT_SetOutputCompareValue(base, in gpt_set_safe()
79 now = GPT_GetCurrentTimerCount(base); in gpt_set_safe()
94 now = GPT_GetCurrentTimerCount(base); in mcux_imx_gpt_isr()
95 status = GPT_GetStatusFlags(base, in mcux_imx_gpt_isr()
98 GPT_ClearStatusFlags(base, status); in mcux_imx_gpt_isr()
119 GPT_ClearStatusFlags(base, kGPT_OutputCompare1Flag); in mcux_imx_gpt_isr()
149 now = GPT_GetCurrentTimerCount(base); in sys_clock_set_timeout()
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| /Zephyr-latest/kernel/include/ |
| D | kthread.h | 63 return thread->base.preempt <= _PREEMPT_THRESHOLD; in thread_is_preemptible()
70 return (thread->base.prio - K_HIGHEST_THREAD_PRIO) in thread_is_metairq()
81 return (thread->base.thread_state & _THREAD_DUMMY) != 0U; in is_thread_dummy()
88 return (thread->base.thread_state & _THREAD_SUSPENDED) != 0U; in z_is_thread_suspended()
93 return (thread->base.thread_state & _THREAD_PENDING) != 0U; in z_is_thread_pending()
98 uint8_t state = thread->base.thread_state; in z_is_thread_prevented_from_running()
106 return !z_is_inactive_timeout(&thread->base.timeout); in z_is_thread_timeout_active()
117 return (thread->base.thread_state & state) != 0U; in z_is_thread_state_set()
127 thread->base.thread_state |= _THREAD_SUSPENDED; in z_mark_thread_as_suspended()
134 thread->base.thread_state &= ~_THREAD_SUSPENDED; in z_mark_thread_as_not_suspended()
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_miwu.c | 76 uintptr_t base; member
132 const uint32_t base = config->base; in npcx_miwu_set_pseudo_both_edge() local
135 if (IS_BIT_SET(NPCX_WKST(base, group), bit)) { in npcx_miwu_set_pseudo_both_edge()
137 NPCX_WKEDG(base, group) |= pmask; in npcx_miwu_set_pseudo_both_edge()
140 NPCX_WKEDG(base, group) &= ~pmask; in npcx_miwu_set_pseudo_both_edge()
149 const uint32_t base = config->base; in intc_miwu_isr_pri() local
150 uint8_t mask = NPCX_WKPND(base, wui_group) & NPCX_WKEN(base, wui_group); in intc_miwu_isr_pri()
159 NPCX_WKPCL(base, wui_group) = pending_mask; in intc_miwu_isr_pri()
169 NPCX_WKPCL(base, wui_group) = mask; in intc_miwu_isr_pri()
181 const uint32_t base = config->base; in npcx_miwu_irq_enable() local
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| /Zephyr-latest/drivers/dp/ |
| D | swdp_ll_pin.h | 39 static ALWAYS_INLINE void swdp_ll_pin_input(void *const base, uint8_t pin) in swdp_ll_pin_input() argument
42 NRF_GPIO_Type * reg = base; in swdp_ll_pin_input()
48 static ALWAYS_INLINE void swdp_ll_pin_output(void *const base, uint8_t pin) in swdp_ll_pin_output() argument
51 NRF_GPIO_Type * reg = base; in swdp_ll_pin_output()
58 static ALWAYS_INLINE void swdp_ll_pin_set(void *const base, uint8_t pin) in swdp_ll_pin_set() argument
61 NRF_GPIO_Type * reg = base; in swdp_ll_pin_set()
67 static ALWAYS_INLINE void swdp_ll_pin_clr(void *const base, uint8_t pin) in swdp_ll_pin_clr() argument
70 NRF_GPIO_Type * reg = base; in swdp_ll_pin_clr()
76 static ALWAYS_INLINE uint32_t swdp_ll_pin_get(void *const base, uint8_t pin) in swdp_ll_pin_get() argument
79 NRF_GPIO_Type * reg = base; in swdp_ll_pin_get()
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| /Zephyr-latest/drivers/pcie/host/ |
| D | vc.c | 16 uint32_t base; in pcie_vc_cap_lookup() local
18 base = pcie_get_ext_cap(bdf, PCIE_EXT_CAP_ID_VC); in pcie_vc_cap_lookup()
19 if (base == 0) { in pcie_vc_cap_lookup()
20 base = pcie_get_ext_cap(bdf, PCIE_EXT_CAP_ID_MFVC_VC); in pcie_vc_cap_lookup()
21 if (base == 0) { in pcie_vc_cap_lookup()
26 regs->cap_reg_1.raw = pcie_conf_read(bdf, base + in pcie_vc_cap_lookup()
28 regs->cap_reg_2.raw = pcie_conf_read(bdf, base + in pcie_vc_cap_lookup()
30 regs->ctrl_reg.raw = pcie_conf_read(bdf, base + in pcie_vc_cap_lookup()
33 return base; in pcie_vc_cap_lookup()
37 uint32_t base, in pcie_vc_load_resources_regs() argument
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| /Zephyr-latest/drivers/dma/ |
| D | dma_intel_adsp_hda.c | 49 res = intel_adsp_hda_set_buffer(cfg->base, cfg->regblock_size, channel, buf, in intel_adsp_hda_dma_host_in_config()
53 *DGMBS(cfg->base, cfg->regblock_size, channel) = in intel_adsp_hda_dma_host_in_config()
56 intel_adsp_hda_set_sample_container_size(cfg->base, cfg->regblock_size, channel, in intel_adsp_hda_dma_host_in_config()
84 res = intel_adsp_hda_set_buffer(cfg->base, cfg->regblock_size, channel, buf, in intel_adsp_hda_dma_host_out_config()
88 *DGMBS(cfg->base, cfg->regblock_size, channel) = in intel_adsp_hda_dma_host_out_config()
91 intel_adsp_hda_set_sample_container_size(cfg->base, cfg->regblock_size, channel, in intel_adsp_hda_dma_host_out_config()
117 res = intel_adsp_hda_set_buffer(cfg->base, cfg->regblock_size, channel, buf, in intel_adsp_hda_dma_link_in_config()
120 intel_adsp_hda_set_sample_container_size(cfg->base, cfg->regblock_size, channel, in intel_adsp_hda_dma_link_in_config()
148 res = intel_adsp_hda_set_buffer(cfg->base, cfg->regblock_size, channel, buf, in intel_adsp_hda_dma_link_out_config()
151 intel_adsp_hda_set_sample_container_size(cfg->base, cfg->regblock_size, channel, in intel_adsp_hda_dma_link_out_config()
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| /Zephyr-latest/drivers/mipi_dbi/ |
| D | mipi_dbi_nxp_lcdic.c | 77 LCDIC_Type *base; member
154 LCDIC_Type *base = config->base; in mipi_dbi_lcdic_reset_state() local
156 base->CTRL &= ~LCDIC_CTRL_LCDIC_EN_MASK; in mipi_dbi_lcdic_reset_state()
158 base->CTRL |= LCDIC_CTRL_LCDIC_EN_MASK; in mipi_dbi_lcdic_reset_state()
180 stream->blk_cfg[0].dest_address = (uint32_t)&config->base->TFIFO_WDATA; in mipi_dbi_lcdic_start_dma()
188 stream->blk_cfg[0].dest_address = (uint32_t)&config->base->TFIFO_WDATA; in mipi_dbi_lcdic_start_dma()
199 (uint32_t)&config->base->TFIFO_WDATA; in mipi_dbi_lcdic_start_dma()
220 config->base->CTRL |= LCDIC_CTRL_DMA_EN_MASK; in mipi_dbi_lcdic_start_dma()
242 LCDIC_Type *base = config->base; in mipi_dbi_lcdic_configure() local
251 base->ICR = LCDIC_ALL_INTERRUPTS; in mipi_dbi_lcdic_configure()
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