1 /*
2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_it8xxx2_i2c
8
9 #include <zephyr/drivers/gpio.h>
10 #include <zephyr/drivers/i2c.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/irq.h>
13 #include <zephyr/kernel.h>
14 #include <errno.h>
15 #include <ilm.h>
16 #include <soc.h>
17 #include <soc_dt.h>
18 #include <zephyr/dt-bindings/i2c/it8xxx2-i2c.h>
19 #include <zephyr/pm/policy.h>
20 #include <zephyr/sys/util.h>
21
22 #include <zephyr/logging/log.h>
23 LOG_MODULE_REGISTER(i2c_ite_it8xxx2, CONFIG_I2C_LOG_LEVEL);
24
25 #include "i2c-priv.h"
26
27 /* Start smbus session from idle state */
28 #define I2C_MSG_START BIT(5)
29
30 #define I2C_LINE_SCL_HIGH BIT(0)
31 #define I2C_LINE_SDA_HIGH BIT(1)
32 #define I2C_LINE_IDLE (I2C_LINE_SCL_HIGH | I2C_LINE_SDA_HIGH)
33
34 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
35 #define I2C_FIFO_MODE_MAX_SIZE 32
36 #define I2C_FIFO_MODE_TOTAL_LEN 255
37 #define I2C_MSG_BURST_READ_MASK (I2C_MSG_RESTART | I2C_MSG_STOP | I2C_MSG_READ)
38 #endif
39
40 struct i2c_it8xxx2_config {
41 void (*irq_config_func)(void);
42 uint32_t bitrate;
43 uint8_t *base;
44 uint8_t *reg_mstfctrl;
45 uint8_t i2c_irq_base;
46 uint8_t port;
47 uint8_t channel_switch_sel;
48 /* SCL GPIO cells */
49 struct gpio_dt_spec scl_gpios;
50 /* SDA GPIO cells */
51 struct gpio_dt_spec sda_gpios;
52 /* I2C alternate configuration */
53 const struct pinctrl_dev_config *pcfg;
54 uint32_t clock_gate_offset;
55 int transfer_timeout_ms;
56 bool fifo_enable;
57 bool push_pull_recovery;
58 };
59
60 enum i2c_pin_fun {
61 SCL = 0,
62 SDA,
63 };
64
65 enum i2c_ch_status {
66 I2C_CH_NORMAL = 0,
67 I2C_CH_REPEAT_START,
68 I2C_CH_WAIT_READ,
69 I2C_CH_WAIT_NEXT_XFER,
70 };
71
72 struct i2c_it8xxx2_data {
73 enum i2c_ch_status i2ccs;
74 struct i2c_msg *active_msg;
75 struct k_mutex mutex;
76 struct k_sem device_sync_sem;
77 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
78 struct i2c_msg *msgs_list;
79 /* Read or write byte counts. */
80 uint32_t bytecnt;
81 /* Number of messages. */
82 uint8_t num_msgs;
83 uint8_t active_msg_index;
84 #endif
85 /* Index into output data */
86 size_t widx;
87 /* Index into input data */
88 size_t ridx;
89 /* operation freq of i2c */
90 uint32_t bus_freq;
91 /* Error code, if any */
92 uint32_t err;
93 /* address of device */
94 uint16_t addr_16bit;
95 /* Frequency setting */
96 uint8_t freq;
97 /* wait for stop bit interrupt */
98 uint8_t stop;
99 };
100
101 enum i2c_host_status {
102 /* Host busy */
103 HOSTA_HOBY = 0x01,
104 /* Finish Interrupt */
105 HOSTA_FINTR = 0x02,
106 /* Device error */
107 HOSTA_DVER = 0x04,
108 /* Bus error */
109 HOSTA_BSER = 0x08,
110 /* Fail */
111 HOSTA_FAIL = 0x10,
112 /* Not response ACK */
113 HOSTA_NACK = 0x20,
114 /* Time-out error */
115 HOSTA_TMOE = 0x40,
116 /* Byte done status */
117 HOSTA_BDS = 0x80,
118 /* Error bit is set */
119 HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER | HOSTA_FAIL |
120 HOSTA_NACK | HOSTA_TMOE),
121 /* W/C for next byte */
122 HOSTA_NEXT_BYTE = HOSTA_BDS,
123 /* W/C host status register */
124 HOSTA_ALL_WC_BIT = (HOSTA_FINTR | HOSTA_ANY_ERROR | HOSTA_BDS),
125 };
126
127 enum i2c_reset_cause {
128 I2C_RC_NO_IDLE_FOR_START = 1,
129 I2C_RC_TIMEOUT,
130 };
131
i2c_parsing_return_value(const struct device * dev)132 static int i2c_parsing_return_value(const struct device *dev)
133 {
134 const struct i2c_it8xxx2_config *config = dev->config;
135 struct i2c_it8xxx2_data *data = dev->data;
136
137 if (!data->err) {
138 return 0;
139 }
140
141 if (data->err == ETIMEDOUT) {
142 /* Connection timed out */
143 LOG_ERR("I2C ch%d Address:0x%X Transaction time out.",
144 config->port, data->addr_16bit);
145 } else {
146 LOG_DBG("I2C ch%d Address:0x%X Host error bits message:",
147 config->port, data->addr_16bit);
148 /* Host error bits message*/
149 if (data->err & HOSTA_TMOE) {
150 LOG_ERR("Time-out error: hardware time-out error.");
151 }
152 if (data->err & HOSTA_NACK) {
153 LOG_DBG("NACK error: device does not response ACK.");
154 }
155 if (data->err & HOSTA_FAIL) {
156 LOG_ERR("Fail: a processing transmission is killed.");
157 }
158 if (data->err & HOSTA_BSER) {
159 LOG_ERR("BUS error: SMBus has lost arbitration.");
160 }
161 }
162
163 return -EIO;
164 }
165
i2c_get_line_levels(const struct device * dev)166 static int i2c_get_line_levels(const struct device *dev)
167 {
168 const struct i2c_it8xxx2_config *config = dev->config;
169 uint8_t *base = config->base;
170
171 return (IT8XXX2_SMB_SMBPCTL(base) &
172 (IT8XXX2_SMB_SMBDCS | IT8XXX2_SMB_SMBCS));
173 }
174
i2c_is_busy(const struct device * dev)175 static int i2c_is_busy(const struct device *dev)
176 {
177 const struct i2c_it8xxx2_config *config = dev->config;
178 uint8_t *base = config->base;
179
180 return (IT8XXX2_SMB_HOSTA(base) &
181 (HOSTA_HOBY | HOSTA_ALL_WC_BIT));
182 }
183
i2c_bus_not_available(const struct device * dev)184 static int i2c_bus_not_available(const struct device *dev)
185 {
186 if (i2c_is_busy(dev) ||
187 (i2c_get_line_levels(dev) != I2C_LINE_IDLE)) {
188 return -EIO;
189 }
190
191 return 0;
192 }
193
i2c_reset(const struct device * dev)194 static void i2c_reset(const struct device *dev)
195 {
196 const struct i2c_it8xxx2_config *config = dev->config;
197 uint8_t *base = config->base;
198
199 /* bit1, kill current transaction. */
200 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_KILL;
201 IT8XXX2_SMB_HOCTL(base) = 0;
202 /* W/C host status register */
203 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
204 }
205
206 /*
207 * Set i2c standard port (A, B, or C) runs at 400kHz by using timing registers
208 * (offset 0h ~ 7h).
209 */
i2c_standard_port_timing_regs_400khz(uint8_t port)210 static void i2c_standard_port_timing_regs_400khz(uint8_t port)
211 {
212 /* Port clock frequency depends on setting of timing registers. */
213 IT8XXX2_SMB_SCLKTS(port) = 0;
214 /* Suggested setting of timing registers of 400kHz. */
215 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
216 IT8XXX2_SMB_4P7USL = 0x16;
217 IT8XXX2_SMB_4P0USL = 0x11;
218 IT8XXX2_SMB_300NS = 0x8;
219 IT8XXX2_SMB_250NS = 0x8;
220 IT8XXX2_SMB_45P3USL = 0xff;
221 IT8XXX2_SMB_45P3USH = 0x3;
222 IT8XXX2_SMB_4P7A4P0H = 0;
223 #else
224 IT8XXX2_SMB_4P7USL = 0x3;
225 IT8XXX2_SMB_4P0USL = 0;
226 IT8XXX2_SMB_300NS = 0x1;
227 IT8XXX2_SMB_250NS = 0x5;
228 IT8XXX2_SMB_45P3USL = 0x6a;
229 IT8XXX2_SMB_45P3USH = 0x1;
230 IT8XXX2_SMB_4P7A4P0H = 0;
231 #endif
232 }
233
234 /* Set clock frequency for i2c port A, B , or C */
i2c_standard_port_set_frequency(const struct device * dev,int freq_hz,int freq_set)235 static void i2c_standard_port_set_frequency(const struct device *dev,
236 int freq_hz, int freq_set)
237 {
238 const struct i2c_it8xxx2_config *config = dev->config;
239
240 /*
241 * If port's clock frequency is 400kHz, we use timing registers
242 * for setting. So we can adjust tlow to meet timing.
243 * The others use basic 50/100/1000 KHz setting.
244 */
245 if (freq_hz == I2C_BITRATE_FAST) {
246 i2c_standard_port_timing_regs_400khz(config->port);
247 } else {
248 IT8XXX2_SMB_SCLKTS(config->port) = freq_set;
249 }
250
251 /* This field defines the SMCLK0/1/2 clock/data low timeout. */
252 IT8XXX2_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
253 }
254
i2c_it8xxx2_configure(const struct device * dev,uint32_t dev_config_raw)255 static int i2c_it8xxx2_configure(const struct device *dev,
256 uint32_t dev_config_raw)
257 {
258 const struct i2c_it8xxx2_config *config = dev->config;
259 struct i2c_it8xxx2_data *const data = dev->data;
260 uint32_t freq_set;
261
262 if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
263 return -EINVAL;
264 }
265
266 if (I2C_ADDR_10_BITS & dev_config_raw) {
267 return -EINVAL;
268 }
269
270 data->bus_freq = I2C_SPEED_GET(dev_config_raw);
271
272 switch (data->bus_freq) {
273 case I2C_SPEED_DT:
274 freq_set = IT8XXX2_SMB_SMCLKS_50K;
275 break;
276 case I2C_SPEED_STANDARD:
277 freq_set = IT8XXX2_SMB_SMCLKS_100K;
278 break;
279 case I2C_SPEED_FAST:
280 freq_set = IT8XXX2_SMB_SMCLKS_400K;
281 break;
282 case I2C_SPEED_FAST_PLUS:
283 freq_set = IT8XXX2_SMB_SMCLKS_1M;
284 break;
285 default:
286 return -EINVAL;
287 }
288
289 i2c_standard_port_set_frequency(dev, config->bitrate, freq_set);
290
291 return 0;
292 }
293
i2c_it8xxx2_get_config(const struct device * dev,uint32_t * dev_config)294 static int i2c_it8xxx2_get_config(const struct device *dev,
295 uint32_t *dev_config)
296 {
297 struct i2c_it8xxx2_data *const data = dev->data;
298 uint32_t speed;
299
300 if (!data->bus_freq) {
301 LOG_ERR("The bus frequency is not initially configured.");
302 return -EIO;
303 }
304
305 switch (data->bus_freq) {
306 case I2C_SPEED_DT:
307 case I2C_SPEED_STANDARD:
308 case I2C_SPEED_FAST:
309 case I2C_SPEED_FAST_PLUS:
310 speed = I2C_SPEED_SET(data->bus_freq);
311 break;
312 default:
313 return -ERANGE;
314 }
315
316 *dev_config = (I2C_MODE_CONTROLLER | speed);
317
318 return 0;
319 }
320
i2c_r_last_byte(const struct device * dev)321 void __soc_ram_code i2c_r_last_byte(const struct device *dev)
322 {
323 struct i2c_it8xxx2_data *data = dev->data;
324 const struct i2c_it8xxx2_config *config = dev->config;
325 uint8_t *base = config->base;
326
327 /*
328 * bit5, The firmware shall write 1 to this bit
329 * when the next byte will be the last byte for i2c read.
330 */
331 if ((data->active_msg->flags & I2C_MSG_STOP) &&
332 (data->ridx == data->active_msg->len - 1)) {
333 IT8XXX2_SMB_HOCTL(base) |= IT8XXX2_SMB_LABY;
334 }
335 }
336
i2c_w2r_change_direction(const struct device * dev)337 void __soc_ram_code i2c_w2r_change_direction(const struct device *dev)
338 {
339 const struct i2c_it8xxx2_config *config = dev->config;
340 uint8_t *base = config->base;
341
342 /* I2C switch direction */
343 if (IT8XXX2_SMB_HOCTL2(base) & IT8XXX2_SMB_I2C_SW_EN) {
344 i2c_r_last_byte(dev);
345 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
346 } else {
347 /*
348 * bit2, I2C switch direction wait.
349 * bit3, I2C switch direction enable.
350 */
351 IT8XXX2_SMB_HOCTL2(base) |= IT8XXX2_SMB_I2C_SW_EN |
352 IT8XXX2_SMB_I2C_SW_WAIT;
353 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
354 i2c_r_last_byte(dev);
355 IT8XXX2_SMB_HOCTL2(base) &= ~IT8XXX2_SMB_I2C_SW_WAIT;
356 }
357 }
358
359 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
i2c_fifo_en_w2r(const struct device * dev,bool enable)360 void __soc_ram_code i2c_fifo_en_w2r(const struct device *dev, bool enable)
361 {
362 const struct i2c_it8xxx2_config *config = dev->config;
363 unsigned int key = irq_lock();
364
365 if (enable) {
366 if (config->port == SMB_CHANNEL_A) {
367 IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MAIF |
368 IT8XXX2_SMB_MAIFI;
369 } else if (config->port == SMB_CHANNEL_B) {
370 IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MBCIF |
371 IT8XXX2_SMB_MBIFI;
372 } else if (config->port == SMB_CHANNEL_C) {
373 IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MBCIF |
374 IT8XXX2_SMB_MCIFI;
375 }
376 } else {
377 if (config->port == SMB_CHANNEL_A) {
378 IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MAIF |
379 IT8XXX2_SMB_MAIFI);
380 } else if (config->port == SMB_CHANNEL_B) {
381 IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MBCIF |
382 IT8XXX2_SMB_MBIFI);
383 } else if (config->port == SMB_CHANNEL_C) {
384 IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MBCIF |
385 IT8XXX2_SMB_MCIFI);
386 }
387 }
388
389 irq_unlock(key);
390 }
391
i2c_tran_fifo_write_start(const struct device * dev)392 void __soc_ram_code i2c_tran_fifo_write_start(const struct device *dev)
393 {
394 struct i2c_it8xxx2_data *data = dev->data;
395 const struct i2c_it8xxx2_config *config = dev->config;
396 uint32_t i;
397 uint8_t *base = config->base;
398 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
399
400 /* Clear start flag. */
401 data->active_msg->flags &= ~I2C_MSG_START;
402 /* Enable SMB channel in FIFO mode. */
403 *reg_mstfctrl |= IT8XXX2_SMB_FFEN;
404 /* I2C enable. */
405 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
406 IT8XXX2_SMB_I2C_EN |
407 IT8XXX2_SMB_SMHEN;
408 /* Set write byte counts. */
409 IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
410 /*
411 * bit[7:1]: Address of the target.
412 * bit[0]: Direction of the host transfer.
413 */
414 IT8XXX2_SMB_TRASLA(base) = (uint8_t)data->addr_16bit << 1;
415 /* The maximum fifo size is 32 bytes. */
416 data->bytecnt = MIN(data->active_msg->len, I2C_FIFO_MODE_MAX_SIZE);
417
418 for (i = 0; i < data->bytecnt; i++) {
419 /* Set host block data byte. */
420 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
421 }
422 /* Calculate the remaining byte counts. */
423 data->bytecnt = data->active_msg->len - data->bytecnt;
424 /*
425 * bit[6] = 1b: Start.
426 * bit[4:2] = 111b: Extend command.
427 * bit[0] = 1b: Host interrupt enable.
428 */
429 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
430 IT8XXX2_SMB_SMCD_EXTND |
431 IT8XXX2_SMB_INTREN;
432 }
433
i2c_tran_fifo_write_next_block(const struct device * dev)434 void __soc_ram_code i2c_tran_fifo_write_next_block(const struct device *dev)
435 {
436 struct i2c_it8xxx2_data *data = dev->data;
437 const struct i2c_it8xxx2_config *config = dev->config;
438 uint32_t i, _bytecnt;
439 uint8_t *base = config->base;
440 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
441
442 /* The maximum fifo size is 32 bytes. */
443 _bytecnt = MIN(data->bytecnt, I2C_FIFO_MODE_MAX_SIZE);
444
445 for (i = 0; i < _bytecnt; i++) {
446 /* Set host block data byte. */
447 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
448 }
449 /* Clear FIFO block done status. */
450 *reg_mstfctrl |= IT8XXX2_SMB_BLKDS;
451 /* Calculate the remaining byte counts. */
452 data->bytecnt -= _bytecnt;
453 }
454
i2c_tran_fifo_write_finish(const struct device * dev)455 void __soc_ram_code i2c_tran_fifo_write_finish(const struct device *dev)
456 {
457 const struct i2c_it8xxx2_config *config = dev->config;
458 uint8_t *base = config->base;
459
460 /* Clear byte count register. */
461 IT8XXX2_SMB_D0REG(base) = 0;
462 /* W/C */
463 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
464 /* Disable the SMBus host interface. */
465 IT8XXX2_SMB_HOCTL2(base) = 0x00;
466 }
467
i2c_tran_fifo_w2r_change_direction(const struct device * dev)468 int __soc_ram_code i2c_tran_fifo_w2r_change_direction(const struct device *dev)
469 {
470 struct i2c_it8xxx2_data *data = dev->data;
471 const struct i2c_it8xxx2_config *config = dev->config;
472 uint8_t *base = config->base;
473
474 if (++data->active_msg_index >= data->num_msgs) {
475 LOG_ERR("Current message index is error.");
476 data->err = EINVAL;
477 /* W/C */
478 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
479 /* Disable the SMBus host interface. */
480 IT8XXX2_SMB_HOCTL2(base) = 0x00;
481
482 return 0;
483 }
484 /* Set I2C_SW_EN = 1 */
485 IT8XXX2_SMB_HOCTL2(base) |= IT8XXX2_SMB_I2C_SW_EN |
486 IT8XXX2_SMB_I2C_SW_WAIT;
487 IT8XXX2_SMB_HOCTL2(base) &= ~IT8XXX2_SMB_I2C_SW_WAIT;
488 /* Point to the next msg for the read location. */
489 data->active_msg = &data->msgs_list[data->active_msg_index];
490 /* Set read byte counts. */
491 IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
492 data->bytecnt = data->active_msg->len;
493 /* W/C I2C W2R FIFO interrupt status. */
494 IT8XXX2_SMB_IWRFISTA = BIT(config->port);
495
496 return 1;
497 }
498
i2c_tran_fifo_read_start(const struct device * dev)499 void __soc_ram_code i2c_tran_fifo_read_start(const struct device *dev)
500 {
501 struct i2c_it8xxx2_data *data = dev->data;
502 const struct i2c_it8xxx2_config *config = dev->config;
503 uint8_t *base = config->base;
504 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
505
506 /* Clear start flag. */
507 data->active_msg->flags &= ~I2C_MSG_START;
508 /* Enable SMB channel in FIFO mode. */
509 *reg_mstfctrl |= IT8XXX2_SMB_FFEN;
510 /* I2C enable. */
511 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
512 IT8XXX2_SMB_I2C_EN |
513 IT8XXX2_SMB_SMHEN;
514 /* Set read byte counts. */
515 IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
516 /*
517 * bit[7:1]: Address of the target.
518 * bit[0]: Direction of the host transfer.
519 */
520 IT8XXX2_SMB_TRASLA(base) = (uint8_t)(data->addr_16bit << 1) |
521 IT8XXX2_SMB_DIR;
522
523 data->bytecnt = data->active_msg->len;
524 /*
525 * bit[6] = 1b: Start.
526 * bit[4:2] = 111b: Extend command.
527 * bit[0] = 1b: Host interrupt enable.
528 */
529 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
530 IT8XXX2_SMB_SMCD_EXTND |
531 IT8XXX2_SMB_INTREN;
532 }
533
i2c_tran_fifo_read_next_block(const struct device * dev)534 void __soc_ram_code i2c_tran_fifo_read_next_block(const struct device *dev)
535 {
536 struct i2c_it8xxx2_data *data = dev->data;
537 const struct i2c_it8xxx2_config *config = dev->config;
538 uint32_t i;
539 uint8_t *base = config->base;
540 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
541
542 for (i = 0; i < I2C_FIFO_MODE_MAX_SIZE; i++) {
543 /* To get received data. */
544 *(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
545 }
546 /* Clear FIFO block done status. */
547 *reg_mstfctrl |= IT8XXX2_SMB_BLKDS;
548 /* Calculate the remaining byte counts. */
549 data->bytecnt -= I2C_FIFO_MODE_MAX_SIZE;
550 }
551
i2c_tran_fifo_read_finish(const struct device * dev)552 void __soc_ram_code i2c_tran_fifo_read_finish(const struct device *dev)
553 {
554 struct i2c_it8xxx2_data *data = dev->data;
555 const struct i2c_it8xxx2_config *config = dev->config;
556 uint32_t i;
557 uint8_t *base = config->base;
558
559 for (i = 0; i < data->bytecnt; i++) {
560 /* To get received data. */
561 *(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
562 }
563 /* Clear byte count register. */
564 IT8XXX2_SMB_D0REG(base) = 0;
565 /* W/C */
566 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
567 /* Disable the SMBus host interface. */
568 IT8XXX2_SMB_HOCTL2(base) = 0x00;
569
570 }
571
i2c_tran_fifo_write_to_read(const struct device * dev)572 int __soc_ram_code i2c_tran_fifo_write_to_read(const struct device *dev)
573 {
574 struct i2c_it8xxx2_data *data = dev->data;
575 const struct i2c_it8xxx2_config *config = dev->config;
576 uint8_t *base = config->base;
577 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
578 int ret = 1;
579
580 if (data->active_msg->flags & I2C_MSG_START) {
581 /* Enable I2C write to read FIFO mode. */
582 i2c_fifo_en_w2r(dev, 1);
583 i2c_tran_fifo_write_start(dev);
584 } else {
585 /* Check block done status. */
586 if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
587 if (IT8XXX2_SMB_HOCTL2(base) & IT8XXX2_SMB_I2C_SW_EN) {
588 i2c_tran_fifo_read_next_block(dev);
589 } else {
590 i2c_tran_fifo_write_next_block(dev);
591 }
592 } else if (IT8XXX2_SMB_IWRFISTA & BIT(config->port)) {
593 /*
594 * This function returns 0 on a failure to indicate
595 * that the current transaction is completed and
596 * returned the data->err.
597 */
598 ret = i2c_tran_fifo_w2r_change_direction(dev);
599 } else {
600 /* Wait finish. */
601 if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
602 i2c_tran_fifo_read_finish(dev);
603 /* Done doing work. */
604 ret = 0;
605 }
606 }
607 }
608
609 return ret;
610 }
611
i2c_tran_fifo_read(const struct device * dev)612 int __soc_ram_code i2c_tran_fifo_read(const struct device *dev)
613 {
614 struct i2c_it8xxx2_data *data = dev->data;
615 const struct i2c_it8xxx2_config *config = dev->config;
616 uint8_t *base = config->base;
617 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
618
619 if (data->active_msg->flags & I2C_MSG_START) {
620 i2c_tran_fifo_read_start(dev);
621 } else {
622 /* Check block done status. */
623 if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
624 i2c_tran_fifo_read_next_block(dev);
625 } else {
626 /* Wait finish. */
627 if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
628 i2c_tran_fifo_read_finish(dev);
629 /* Done doing work. */
630 return 0;
631 }
632 }
633 }
634
635 return 1;
636 }
637
i2c_tran_fifo_write(const struct device * dev)638 int __soc_ram_code i2c_tran_fifo_write(const struct device *dev)
639 {
640 struct i2c_it8xxx2_data *data = dev->data;
641 const struct i2c_it8xxx2_config *config = dev->config;
642 uint8_t *base = config->base;
643 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
644
645 if (data->active_msg->flags & I2C_MSG_START) {
646 i2c_tran_fifo_write_start(dev);
647 } else {
648 /* Check block done status. */
649 if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
650 i2c_tran_fifo_write_next_block(dev);
651 } else {
652 /* Wait finish. */
653 if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
654 i2c_tran_fifo_write_finish(dev);
655 /* Done doing work. */
656 return 0;
657 }
658 }
659 }
660
661 return 1;
662 }
663
i2c_fifo_transaction(const struct device * dev)664 int __soc_ram_code i2c_fifo_transaction(const struct device *dev)
665 {
666 struct i2c_it8xxx2_data *data = dev->data;
667 const struct i2c_it8xxx2_config *config = dev->config;
668 uint8_t *base = config->base;
669
670 /* Any error. */
671 if (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR) {
672 data->err = (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR);
673 } else {
674 if (data->num_msgs == 2) {
675 return i2c_tran_fifo_write_to_read(dev);
676 } else if (data->active_msg->flags & I2C_MSG_READ) {
677 return i2c_tran_fifo_read(dev);
678 } else {
679 return i2c_tran_fifo_write(dev);
680 }
681 }
682 /* W/C */
683 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
684 /* Disable the SMBus host interface. */
685 IT8XXX2_SMB_HOCTL2(base) = 0x00;
686
687 return 0;
688 }
689
fifo_mode_allowed(const struct device * dev,struct i2c_msg * msgs)690 bool __soc_ram_code fifo_mode_allowed(const struct device *dev,
691 struct i2c_msg *msgs)
692 {
693 struct i2c_it8xxx2_data *data = dev->data;
694 const struct i2c_it8xxx2_config *config = dev->config;
695
696 /*
697 * If the transaction of write or read is divided into two
698 * transfers(not two messages), the FIFO mode does not support.
699 */
700 if (data->i2ccs != I2C_CH_NORMAL) {
701 return false;
702 }
703 /*
704 * FIFO2 only supports one channel of B or C. If the FIFO of
705 * channel is not enabled, it will select PIO mode.
706 */
707 if (!config->fifo_enable) {
708 return false;
709 }
710 /*
711 * When there is only one message, use the FIFO mode transfer
712 * directly.
713 * Transfer payload too long (>255 bytes), use PIO mode.
714 * Write or read of I2C target address without data, used by
715 * cmd_i2c_scan. Use PIO mode.
716 */
717 if (data->num_msgs == 1 && (msgs[0].flags & I2C_MSG_STOP) &&
718 (msgs[0].len <= I2C_FIFO_MODE_TOTAL_LEN) && (msgs[0].len != 0)) {
719 return true;
720 }
721 /*
722 * When there are two messages, we need to judge whether or not there
723 * is I2C_MSG_RESTART flag from the second message, and then decide to
724 * do the FIFO mode or PIO mode transfer.
725 */
726 if (data->num_msgs == 2) {
727 /*
728 * The first of two messages must be write.
729 * Transfer payload too long (>255 bytes), use PIO mode.
730 */
731 if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
732 (msgs[0].len <= I2C_FIFO_MODE_TOTAL_LEN)) {
733 /*
734 * The transfer is i2c_burst_read().
735 *
736 * e.g. msg[0].flags = I2C_MSG_WRITE;
737 * msg[1].flags = I2C_MSG_RESTART | I2C_MSG_READ |
738 * I2C_MSG_STOP;
739 */
740 if ((msgs[1].flags == I2C_MSG_BURST_READ_MASK) &&
741 (msgs[1].len <= I2C_FIFO_MODE_TOTAL_LEN)) {
742 return true;
743 }
744 }
745 }
746
747 return false;
748 }
749 #endif
750
i2c_tran_read(const struct device * dev)751 int __soc_ram_code i2c_tran_read(const struct device *dev)
752 {
753 struct i2c_it8xxx2_data *data = dev->data;
754 const struct i2c_it8xxx2_config *config = dev->config;
755 uint8_t *base = config->base;
756
757 if (data->active_msg->flags & I2C_MSG_START) {
758 /* i2c enable */
759 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
760 IT8XXX2_SMB_I2C_EN |
761 IT8XXX2_SMB_SMHEN;
762 /*
763 * bit0, Direction of the host transfer.
764 * bit[1:7}, Address of the targeted slave.
765 */
766 IT8XXX2_SMB_TRASLA(base) = (uint8_t)(data->addr_16bit << 1) |
767 IT8XXX2_SMB_DIR;
768 /* clear start flag */
769 data->active_msg->flags &= ~I2C_MSG_START;
770 /*
771 * bit0, Host interrupt enable.
772 * bit[2:4}, Extend command.
773 * bit5, The firmware shall write 1 to this bit
774 * when the next byte will be the last byte.
775 * bit6, start.
776 */
777 if ((data->active_msg->len == 1) &&
778 (data->active_msg->flags & I2C_MSG_STOP)) {
779 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
780 IT8XXX2_SMB_LABY |
781 IT8XXX2_SMB_SMCD_EXTND |
782 IT8XXX2_SMB_INTREN;
783 } else {
784 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
785 IT8XXX2_SMB_SMCD_EXTND |
786 IT8XXX2_SMB_INTREN;
787 }
788 } else {
789 if ((data->i2ccs == I2C_CH_REPEAT_START) ||
790 (data->i2ccs == I2C_CH_WAIT_READ)) {
791 if (data->i2ccs == I2C_CH_REPEAT_START) {
792 /* write to read */
793 i2c_w2r_change_direction(dev);
794 } else {
795 /* For last byte */
796 i2c_r_last_byte(dev);
797 /* W/C for next byte */
798 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
799 }
800 data->i2ccs = I2C_CH_NORMAL;
801 } else if (IT8XXX2_SMB_HOSTA(base) & HOSTA_BDS) {
802 if (data->ridx < data->active_msg->len) {
803 /* To get received data. */
804 *(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
805 data->ridx++;
806 /* For last byte */
807 i2c_r_last_byte(dev);
808 /* done */
809 if (data->ridx == data->active_msg->len) {
810 data->active_msg->len = 0;
811 if (data->active_msg->flags & I2C_MSG_STOP) {
812 /* W/C for finish */
813 IT8XXX2_SMB_HOSTA(base) =
814 HOSTA_NEXT_BYTE;
815
816 data->stop = 1;
817 } else {
818 data->i2ccs = I2C_CH_WAIT_READ;
819 return 0;
820 }
821 } else {
822 /* W/C for next byte */
823 IT8XXX2_SMB_HOSTA(base) =
824 HOSTA_NEXT_BYTE;
825 }
826 }
827 }
828 }
829 return 1;
830
831 }
832
i2c_tran_write(const struct device * dev)833 int __soc_ram_code i2c_tran_write(const struct device *dev)
834 {
835 struct i2c_it8xxx2_data *data = dev->data;
836 const struct i2c_it8xxx2_config *config = dev->config;
837 uint8_t *base = config->base;
838
839 if (data->active_msg->flags & I2C_MSG_START) {
840 /* i2c enable */
841 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
842 IT8XXX2_SMB_I2C_EN |
843 IT8XXX2_SMB_SMHEN;
844 /*
845 * bit0, Direction of the host transfer.
846 * bit[1:7}, Address of the targeted slave.
847 */
848 IT8XXX2_SMB_TRASLA(base) = (uint8_t)data->addr_16bit << 1;
849 /* Send first byte */
850 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
851
852 data->widx++;
853 /* clear start flag */
854 data->active_msg->flags &= ~I2C_MSG_START;
855 /*
856 * bit0, Host interrupt enable.
857 * bit[2:4}, Extend command.
858 * bit6, start.
859 */
860 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
861 IT8XXX2_SMB_SMCD_EXTND |
862 IT8XXX2_SMB_INTREN;
863 } else {
864 /* Host has completed the transmission of a byte */
865 if (IT8XXX2_SMB_HOSTA(base) & HOSTA_BDS) {
866 if (data->widx < data->active_msg->len) {
867 /* Send next byte */
868 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
869
870 data->widx++;
871 /* W/C byte done for next byte */
872 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
873
874 if (data->i2ccs == I2C_CH_REPEAT_START) {
875 data->i2ccs = I2C_CH_NORMAL;
876 }
877 } else {
878 /* done */
879 data->active_msg->len = 0;
880 if (data->active_msg->flags & I2C_MSG_STOP) {
881 /* set I2C_EN = 0 */
882 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
883 IT8XXX2_SMB_SMHEN;
884 /* W/C byte done for finish */
885 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
886
887 data->stop = 1;
888 } else {
889 data->i2ccs = I2C_CH_REPEAT_START;
890 return 0;
891 }
892 }
893 }
894 }
895 return 1;
896
897 }
898
i2c_pio_transaction(const struct device * dev)899 int __soc_ram_code i2c_pio_transaction(const struct device *dev)
900 {
901 struct i2c_it8xxx2_data *data = dev->data;
902 const struct i2c_it8xxx2_config *config = dev->config;
903 uint8_t *base = config->base;
904
905 /* any error */
906 if (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR) {
907 data->err = (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR);
908 } else {
909 if (!data->stop) {
910 /*
911 * The return value indicates if there is more data
912 * to be read or written. If the return value = 1,
913 * it means that the interrupt cannot be disable and
914 * continue to transmit data.
915 */
916 if (data->active_msg->flags & I2C_MSG_READ) {
917 return i2c_tran_read(dev);
918 } else {
919 return i2c_tran_write(dev);
920 }
921 }
922 /* wait finish */
923 if (!(IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
924 return 1;
925 }
926 }
927 /* W/C */
928 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
929 /* disable the SMBus host interface */
930 IT8XXX2_SMB_HOCTL2(base) = 0x00;
931
932 data->stop = 0;
933 /* done doing work */
934 return 0;
935 }
936
i2c_it8xxx2_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)937 static int i2c_it8xxx2_transfer(const struct device *dev, struct i2c_msg *msgs,
938 uint8_t num_msgs, uint16_t addr)
939 {
940 struct i2c_it8xxx2_data *data = dev->data;
941 const struct i2c_it8xxx2_config *config = dev->config;
942 int res, ret;
943
944 /* Lock mutex of i2c controller */
945 k_mutex_lock(&data->mutex, K_FOREVER);
946 /*
947 * If the transaction of write to read is divided into two
948 * transfers, the repeat start transfer uses this flag to
949 * exclude checking bus busy.
950 */
951 if (data->i2ccs == I2C_CH_NORMAL) {
952 struct i2c_msg *start_msg = &msgs[0];
953
954 /* Make sure we're in a good state to start */
955 if (i2c_bus_not_available(dev)) {
956 /* Recovery I2C bus */
957 i2c_recover_bus(dev);
958 /*
959 * After resetting I2C bus, if I2C bus is not available
960 * (No external pull-up), drop the transaction.
961 */
962 if (i2c_bus_not_available(dev)) {
963 /* Unlock mutex of i2c controller */
964 k_mutex_unlock(&data->mutex);
965 return -EIO;
966 }
967 }
968
969 start_msg->flags |= I2C_MSG_START;
970 }
971 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
972 /* Store num_msgs to data struct. */
973 data->num_msgs = num_msgs;
974 /* Store msgs to data struct. */
975 data->msgs_list = msgs;
976 bool fifo_mode_enable = fifo_mode_allowed(dev, msgs);
977
978 if (fifo_mode_enable) {
979 /* Block to enter power policy. */
980 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
981 }
982 #endif
983 for (int i = 0; i < num_msgs; i++) {
984
985 data->widx = 0;
986 data->ridx = 0;
987 data->err = 0;
988 data->active_msg = &msgs[i];
989 data->addr_16bit = addr;
990
991 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
992 data->active_msg_index = 0;
993 /*
994 * Start transaction.
995 * The return value indicates if the initial configuration
996 * of I2C transaction for read or write has been completed.
997 */
998 if (fifo_mode_enable) {
999 if (i2c_fifo_transaction(dev)) {
1000 /* Enable i2c interrupt */
1001 irq_enable(config->i2c_irq_base);
1002 }
1003 } else
1004 #endif
1005 {
1006 if (i2c_pio_transaction(dev)) {
1007 /* Enable i2c interrupt */
1008 irq_enable(config->i2c_irq_base);
1009 }
1010 }
1011 /* Wait for the transfer to complete */
1012 res = k_sem_take(&data->device_sync_sem, K_MSEC(config->transfer_timeout_ms));
1013 /*
1014 * The irq will be enabled at the condition of start or
1015 * repeat start of I2C. If timeout occurs without being
1016 * wake up during suspend(ex: interrupt is not fired),
1017 * the irq should be disabled immediately.
1018 */
1019 irq_disable(config->i2c_irq_base);
1020 /*
1021 * The transaction is dropped on any error(timeout, NACK, fail,
1022 * bus error, device error).
1023 */
1024 if (data->err) {
1025 break;
1026 }
1027
1028 if (res != 0) {
1029 data->err = ETIMEDOUT;
1030 /* reset i2c port */
1031 i2c_reset(dev);
1032 LOG_ERR("I2C ch%d:0x%X reset cause %d",
1033 config->port, data->addr_16bit, I2C_RC_TIMEOUT);
1034 /* If this message is sent fail, drop the transaction. */
1035 break;
1036 }
1037
1038 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1039 /*
1040 * In FIFO mode, messages are compressed into a single
1041 * transaction.
1042 */
1043 if (fifo_mode_enable) {
1044 break;
1045 }
1046 #endif
1047 }
1048 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1049 if (fifo_mode_enable) {
1050 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
1051
1052 /* Disable SMB channels in FIFO mode. */
1053 *reg_mstfctrl &= ~IT8XXX2_SMB_FFEN;
1054 /* Disable I2C write to read FIFO mode. */
1055 if (data->num_msgs == 2) {
1056 i2c_fifo_en_w2r(dev, 0);
1057 }
1058 /* Permit to enter power policy. */
1059 pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
1060 }
1061 #endif
1062 /* reset i2c channel status */
1063 if (data->err || (data->active_msg->flags & I2C_MSG_STOP)) {
1064 data->i2ccs = I2C_CH_NORMAL;
1065 }
1066 /* Save return value. */
1067 ret = i2c_parsing_return_value(dev);
1068 /* Unlock mutex of i2c controller */
1069 k_mutex_unlock(&data->mutex);
1070
1071 return ret;
1072 }
1073
i2c_it8xxx2_isr(const struct device * dev)1074 static void i2c_it8xxx2_isr(const struct device *dev)
1075 {
1076 struct i2c_it8xxx2_data *data = dev->data;
1077 const struct i2c_it8xxx2_config *config = dev->config;
1078
1079 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1080 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
1081
1082 /* If done doing work, wake up the task waiting for the transfer. */
1083 if (config->fifo_enable && (*reg_mstfctrl & IT8XXX2_SMB_FFEN)) {
1084 if (i2c_fifo_transaction(dev)) {
1085 return;
1086 }
1087 } else
1088 #endif
1089 {
1090 if (i2c_pio_transaction(dev)) {
1091 return;
1092 }
1093 }
1094 irq_disable(config->i2c_irq_base);
1095 k_sem_give(&data->device_sync_sem);
1096 }
1097
i2c_it8xxx2_init(const struct device * dev)1098 static int i2c_it8xxx2_init(const struct device *dev)
1099 {
1100 struct i2c_it8xxx2_data *data = dev->data;
1101 const struct i2c_it8xxx2_config *config = dev->config;
1102 uint8_t *base = config->base;
1103 uint32_t bitrate_cfg;
1104 int error, status;
1105
1106 /* Initialize mutex and semaphore */
1107 k_mutex_init(&data->mutex);
1108 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
1109
1110 /* Enable clock to specified peripheral */
1111 volatile uint8_t *reg = (volatile uint8_t *)
1112 (IT8XXX2_ECPM_BASE + (config->clock_gate_offset >> 8));
1113 uint8_t reg_mask = config->clock_gate_offset & 0xff;
1114 *reg &= ~reg_mask;
1115
1116 /* Enable SMBus function */
1117 /*
1118 * bit0, The SMBus host interface is enabled.
1119 * bit1, Enable to communicate with I2C device
1120 * and support I2C-compatible cycles.
1121 * bit4, This bit controls the reset mechanism
1122 * of SMBus master to handle the SMDAT
1123 * line low if 25ms reg timeout.
1124 */
1125 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN | IT8XXX2_SMB_SMHEN;
1126 /*
1127 * bit1, Kill SMBus host transaction.
1128 * bit0, Enable the interrupt for the master interface.
1129 */
1130 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_KILL | IT8XXX2_SMB_SMHEN;
1131 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SMHEN;
1132
1133 /* W/C host status register */
1134 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
1135 IT8XXX2_SMB_HOCTL2(base) = 0x00;
1136
1137 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1138 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
1139
1140 if (config->port == SMB_CHANNEL_B && config->fifo_enable) {
1141 /* Select channel B in FIFO2. */
1142 *reg_mstfctrl = IT8XXX2_SMB_FFCHSEL2_B;
1143 } else if (config->port == SMB_CHANNEL_C && config->fifo_enable) {
1144 /* Select channel C in FIFO2. */
1145 *reg_mstfctrl = IT8XXX2_SMB_FFCHSEL2_C;
1146 }
1147 #endif
1148
1149 /* ChannelA-C switch selection of I2C pin */
1150 if (config->port == SMB_CHANNEL_A) {
1151 IT8XXX2_SMB_SMB01CHS = (IT8XXX2_SMB_SMB01CHS &= ~GENMASK(2, 0)) |
1152 config->channel_switch_sel;
1153 } else if (config->port == SMB_CHANNEL_B) {
1154 IT8XXX2_SMB_SMB01CHS = (config->channel_switch_sel << 4) |
1155 (IT8XXX2_SMB_SMB01CHS &= ~GENMASK(6, 4));
1156 } else if (config->port == SMB_CHANNEL_C) {
1157 IT8XXX2_SMB_SMB23CHS = (IT8XXX2_SMB_SMB23CHS &= ~GENMASK(2, 0)) |
1158 config->channel_switch_sel;
1159 }
1160
1161 /* Set clock frequency for I2C ports */
1162 if (config->bitrate == I2C_BITRATE_STANDARD ||
1163 config->bitrate == I2C_BITRATE_FAST ||
1164 config->bitrate == I2C_BITRATE_FAST_PLUS) {
1165 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
1166 } else {
1167 /* Device tree specified speed */
1168 bitrate_cfg = I2C_SPEED_DT << I2C_SPEED_SHIFT;
1169 }
1170
1171 error = i2c_it8xxx2_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
1172 data->i2ccs = I2C_CH_NORMAL;
1173
1174 if (error) {
1175 LOG_ERR("i2c: failure initializing");
1176 return error;
1177 }
1178
1179 /* Set the pin to I2C alternate function. */
1180 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1181 if (status < 0) {
1182 LOG_ERR("Failed to configure I2C pins");
1183 return status;
1184 }
1185
1186 return 0;
1187 }
1188
i2c_it8xxx2_recover_bus(const struct device * dev)1189 static int i2c_it8xxx2_recover_bus(const struct device *dev)
1190 {
1191 const struct i2c_it8xxx2_config *config = dev->config;
1192 int i, status;
1193
1194 /* Output type selection */
1195 gpio_flags_t flags = GPIO_OUTPUT | (config->push_pull_recovery ? 0 : GPIO_OPEN_DRAIN);
1196 /* Set SCL of I2C as GPIO pin */
1197 gpio_pin_configure_dt(&config->scl_gpios, flags);
1198 /* Set SDA of I2C as GPIO pin */
1199 gpio_pin_configure_dt(&config->sda_gpios, flags);
1200
1201 /*
1202 * In I2C recovery bus, 1ms sleep interval for bitbanging i2c
1203 * is mainly to ensure that gpio has enough time to go from
1204 * low to high or high to low.
1205 */
1206 /* Pull SCL and SDA pin to high */
1207 gpio_pin_set_dt(&config->scl_gpios, 1);
1208 gpio_pin_set_dt(&config->sda_gpios, 1);
1209 k_msleep(1);
1210
1211 /* Start condition */
1212 gpio_pin_set_dt(&config->sda_gpios, 0);
1213 k_msleep(1);
1214 gpio_pin_set_dt(&config->scl_gpios, 0);
1215 k_msleep(1);
1216
1217 /* 9 cycles of SCL with SDA held high */
1218 for (i = 0; i < 9; i++) {
1219 /* SDA */
1220 gpio_pin_set_dt(&config->sda_gpios, 1);
1221 /* SCL */
1222 gpio_pin_set_dt(&config->scl_gpios, 1);
1223 k_msleep(1);
1224 /* SCL */
1225 gpio_pin_set_dt(&config->scl_gpios, 0);
1226 k_msleep(1);
1227 }
1228 /* SDA */
1229 gpio_pin_set_dt(&config->sda_gpios, 0);
1230 k_msleep(1);
1231
1232 /* Stop condition */
1233 gpio_pin_set_dt(&config->scl_gpios, 1);
1234 k_msleep(1);
1235 gpio_pin_set_dt(&config->sda_gpios, 1);
1236 k_msleep(1);
1237
1238 /* Set GPIO back to I2C alternate function of SCL */
1239 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1240 if (status < 0) {
1241 LOG_ERR("Failed to configure I2C pins");
1242 return status;
1243 }
1244
1245 /* reset i2c port */
1246 i2c_reset(dev);
1247 LOG_ERR("I2C ch%d reset cause %d", config->port,
1248 I2C_RC_NO_IDLE_FOR_START);
1249
1250 return 0;
1251 }
1252
1253 static DEVICE_API(i2c, i2c_it8xxx2_driver_api) = {
1254 .configure = i2c_it8xxx2_configure,
1255 .get_config = i2c_it8xxx2_get_config,
1256 .transfer = i2c_it8xxx2_transfer,
1257 .recover_bus = i2c_it8xxx2_recover_bus,
1258 #ifdef CONFIG_I2C_RTIO
1259 .iodev_submit = i2c_iodev_submit_fallback,
1260 #endif
1261 };
1262
1263 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1264 /*
1265 * Sometimes, channel C may write wrong register to the target device.
1266 * This issue occurs when FIFO2 is enabled on channel C. The problem
1267 * arises because FIFO2 is shared between channel B and channel C.
1268 * FIFO2 will be disabled when data access is completed, at which point
1269 * FIFO2 is set to the default configuration for channel B.
1270 * The byte counter of FIFO2 may be affected by channel B. There is a chance
1271 * that channel C may encounter wrong register being written due to FIFO2
1272 * byte counter wrong write after channel B's write operation.
1273 */
1274 BUILD_ASSERT((DT_PROP(DT_NODELABEL(i2c2), fifo_enable) == false),
1275 "Channel C cannot use FIFO mode.");
1276 #endif
1277
1278 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
1279 #define I2C_IT8XXX2_CHECK_SUPPORTED_CLOCK(inst) \
1280 BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) == \
1281 I2C_BITRATE_FAST), "Only supports 400 KHz");
1282
1283 DT_INST_FOREACH_STATUS_OKAY(I2C_IT8XXX2_CHECK_SUPPORTED_CLOCK)
1284 #endif
1285
1286 #define I2C_ITE_IT8XXX2_INIT(inst) \
1287 PINCTRL_DT_INST_DEFINE(inst); \
1288 BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) == \
1289 50000) || \
1290 (DT_INST_PROP(inst, clock_frequency) == \
1291 I2C_BITRATE_STANDARD) || \
1292 (DT_INST_PROP(inst, clock_frequency) == \
1293 I2C_BITRATE_FAST) || \
1294 (DT_INST_PROP(inst, clock_frequency) == \
1295 I2C_BITRATE_FAST_PLUS), "Not support I2C bit rate value"); \
1296 static void i2c_it8xxx2_config_func_##inst(void); \
1297 \
1298 static const struct i2c_it8xxx2_config i2c_it8xxx2_cfg_##inst = { \
1299 .base = (uint8_t *)(DT_INST_REG_ADDR_BY_IDX(inst, 0)), \
1300 .reg_mstfctrl = (uint8_t *)(DT_INST_REG_ADDR_BY_IDX(inst, 1)), \
1301 .irq_config_func = i2c_it8xxx2_config_func_##inst, \
1302 .bitrate = DT_INST_PROP(inst, clock_frequency), \
1303 .i2c_irq_base = DT_INST_IRQN(inst), \
1304 .port = DT_INST_PROP(inst, port_num), \
1305 .channel_switch_sel = DT_INST_PROP(inst, channel_switch_sel), \
1306 .scl_gpios = GPIO_DT_SPEC_INST_GET(inst, scl_gpios), \
1307 .sda_gpios = GPIO_DT_SPEC_INST_GET(inst, sda_gpios), \
1308 .clock_gate_offset = DT_INST_PROP(inst, clock_gate_offset), \
1309 .transfer_timeout_ms = DT_INST_PROP(inst, transfer_timeout_ms), \
1310 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
1311 .fifo_enable = DT_INST_PROP(inst, fifo_enable), \
1312 .push_pull_recovery = DT_INST_PROP(inst, push_pull_recovery), \
1313 }; \
1314 \
1315 static struct i2c_it8xxx2_data i2c_it8xxx2_data_##inst; \
1316 \
1317 I2C_DEVICE_DT_INST_DEFINE(inst, i2c_it8xxx2_init, \
1318 NULL, \
1319 &i2c_it8xxx2_data_##inst, \
1320 &i2c_it8xxx2_cfg_##inst, \
1321 POST_KERNEL, \
1322 CONFIG_I2C_INIT_PRIORITY, \
1323 &i2c_it8xxx2_driver_api); \
1324 \
1325 static void i2c_it8xxx2_config_func_##inst(void) \
1326 { \
1327 IRQ_CONNECT(DT_INST_IRQN(inst), \
1328 0, \
1329 i2c_it8xxx2_isr, \
1330 DEVICE_DT_INST_GET(inst), 0); \
1331 }
1332
1333 DT_INST_FOREACH_STATUS_OKAY(I2C_ITE_IT8XXX2_INIT)
1334
