77 	LCDIC_Type *base;  member
154 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_reset_state()  local
156 	base->CTRL &= ~LCDIC_CTRL_LCDIC_EN_MASK;  in mipi_dbi_lcdic_reset_state()
158 	base->CTRL |= LCDIC_CTRL_LCDIC_EN_MASK;  in mipi_dbi_lcdic_reset_state()
180 		stream->blk_cfg[0].dest_address = (uint32_t)&config->base->TFIFO_WDATA;  in mipi_dbi_lcdic_start_dma()
188 		stream->blk_cfg[0].dest_address = (uint32_t)&config->base->TFIFO_WDATA;  in mipi_dbi_lcdic_start_dma()
199 				(uint32_t)&config->base->TFIFO_WDATA;  in mipi_dbi_lcdic_start_dma()
220 	config->base->CTRL |= LCDIC_CTRL_DMA_EN_MASK;  in mipi_dbi_lcdic_start_dma()
242 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_configure()  local
251 	base->ICR = LCDIC_ALL_INTERRUPTS;  in mipi_dbi_lcdic_configure()
253 	base->IMR = LCDIC_ALL_INTERRUPTS;  in mipi_dbi_lcdic_configure()
271 	reg = base->CTRL;  in mipi_dbi_lcdic_configure()
300 	base->CTRL = reg;  in mipi_dbi_lcdic_configure()
304 	reg = base->SPI_CTRL;  in mipi_dbi_lcdic_configure()
312 	base->SPI_CTRL = reg;  in mipi_dbi_lcdic_configure()
318 	base->I8080_CTRL1 = LCDIC_I8080_CTRL1_TRIW(0xf) |  in mipi_dbi_lcdic_configure()
324 	base->CTRL |= LCDIC_CTRL_LCDIC_EN_MASK;  in mipi_dbi_lcdic_configure()
350 static int mipi_dbi_lcdic_fill_tx(LCDIC_Type *base, const uint8_t *buf,  in mipi_dbi_lcdic_fill_tx()  argument
364 			base->TFIFO_WDATA = last_word;  in mipi_dbi_lcdic_fill_tx()
368 			base->TFIFO_WDATA = word_buf[bytes_written >> 2];  in mipi_dbi_lcdic_fill_tx()
371 		if (base->IRSR & LCDIC_IRSR_TFIFO_OVERFLOW_RAW_INTR_MASK) {  in mipi_dbi_lcdic_fill_tx()
375 			base->ICR |= LCDIC_ICR_TFIFO_OVERFLOW_INTR_CLR_MASK;  in mipi_dbi_lcdic_fill_tx()
385 static void mipi_dbi_lcdic_set_cmd(LCDIC_Type *base,  in mipi_dbi_lcdic_set_cmd()  argument
403 	base->TFIFO_WDATA = cmd.u32;  in mipi_dbi_lcdic_set_cmd()
414 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_write_display()  local
482 		mipi_dbi_lcdic_set_cmd(base, LCDIC_TX, LCDIC_DATA,  in mipi_dbi_lcdic_write_display()
490 		base->IMR &= ~interrupts;  in mipi_dbi_lcdic_write_display()
506 		base->IMR &= ~interrupts;  in mipi_dbi_lcdic_write_display()
524 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_write_cmd()  local
542 	mipi_dbi_lcdic_set_cmd(base, LCDIC_TX, LCDIC_COMMAND,  in mipi_dbi_lcdic_write_cmd()
546 	base->TFIFO_WDATA = cmd;  in mipi_dbi_lcdic_write_cmd()
548 	while ((base->IRSR & LCDIC_IRSR_CMD_DONE_RAW_INTR_MASK) == 0) {  in mipi_dbi_lcdic_write_cmd()
551 	base->ICR |= LCDIC_ICR_CMD_DONE_INTR_CLR_MASK;  in mipi_dbi_lcdic_write_cmd()
567 		mipi_dbi_lcdic_set_cmd(base, LCDIC_TX, LCDIC_DATA,  in mipi_dbi_lcdic_write_cmd()
578 			base->IMR &= ~interrupts;  in mipi_dbi_lcdic_write_cmd()
596 			base->IMR &= ~interrupts;  in mipi_dbi_lcdic_write_cmd()
608 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_reset()  local
636 	base->RST_CTRL = LCDIC_RST_CTRL_RST_WIDTH(rst_width - 1) |  in mipi_dbi_lcdic_reset()
640 	while ((base->IRSR & LCDIC_IRSR_RST_DONE_RAW_INTR_MASK) == 0) {  in mipi_dbi_lcdic_reset()
643 	base->ICR |= LCDIC_ICR_RST_DONE_INTR_CLR_MASK;  in mipi_dbi_lcdic_reset()
652 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_configure_te()  local
684 	reg = base->TE_CTRL;  in mipi_dbi_lcdic_configure_te()
687 	base->TE_CTRL = reg;  in mipi_dbi_lcdic_configure_te()
698 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_init()  local
726 	base->ICR = LCDIC_ALL_INTERRUPTS;  in mipi_dbi_lcdic_init()
728 	base->IMR = LCDIC_ALL_INTERRUPTS;  in mipi_dbi_lcdic_init()
734 	base->FIFO_CTRL = LCDIC_FIFO_CTRL_RFIFO_THRES(LCDIC_RX_FIFO_THRESH) |  in mipi_dbi_lcdic_init()
737 	base->TO_CTRL &= ~(LCDIC_TO_CTRL_CMD_LONG_TO_MASK |  in mipi_dbi_lcdic_init()
741 	base->TIMER_CTRL = LCDIC_TIMER_CTRL_TIMER_RATIO1(config->timer1_ratio) |  in mipi_dbi_lcdic_init()
770 	LCDIC_Type *base = config->base;  in mipi_dbi_lcdic_isr()  local
773 	isr_status = base->ISR;  in mipi_dbi_lcdic_isr()
775 	base->ICR |= isr_status;  in mipi_dbi_lcdic_isr()
778 		if (config->base->CTRL & LCDIC_CTRL_DMA_EN_MASK) {  in mipi_dbi_lcdic_isr()
783 			config->base->CTRL &= ~LCDIC_CTRL_DMA_EN_MASK;  in mipi_dbi_lcdic_isr()
787 			base->IMR |= LCDIC_ALL_INTERRUPTS;  in mipi_dbi_lcdic_isr()
793 			mipi_dbi_lcdic_set_cmd(base, LCDIC_TX, LCDIC_DATA,  in mipi_dbi_lcdic_isr()
817 				bytes_written = mipi_dbi_lcdic_fill_tx(base, data->xfer_buf,  in mipi_dbi_lcdic_isr()
831 		bytes_written = mipi_dbi_lcdic_fill_tx(base, data->xfer_buf,  in mipi_dbi_lcdic_isr()
877 		.base = (LCDIC_Type *)DT_INST_REG_ADDR(n),		\