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/Zephyr-latest/drivers/pwm/
Dpwm_mcux_tpm.c32 TPM_Type *base; member
103 TPM_StopTimer(config->base); in mcux_tpm_set_cycles()
105 status = TPM_SetupPwm(config->base, data->channel, in mcux_tpm_set_cycles()
113 TPM_StartTimer(config->base, config->tpm_clock_source); in mcux_tpm_set_cycles()
115 TPM_UpdateChnlEdgeLevelSelect(config->base, channel, in mcux_tpm_set_cycles()
117 TPM_UpdatePwmDutycycle(config->base, channel, config->mode, in mcux_tpm_set_cycles()
188 TPM_Init(config->base, &tpm_config); in mcux_tpm_init()
203 .base = (TPM_Type *) \
/Zephyr-latest/soc/nuvoton/npcx/common/reg/
Dreg_def.h148 #define NPCX_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + \ argument
165 #define NPCX_DBGCTRL(base) (*(volatile uint8_t *)(base + 0x004)) argument
166 #define NPCX_DBGFRZEN1(base) (*(volatile uint8_t *)(base + 0x006)) argument
167 #define NPCX_DBGFRZEN2(base) (*(volatile uint8_t *)(base + 0x007)) argument
168 #define NPCX_DBGFRZEN3(base) (*(volatile uint8_t *)(base + 0x008)) argument
169 #define NPCX_DBGFRZEN4(base) (*(volatile uint8_t *)(base + 0x009)) argument
238 #define NPCX_DEV_CTL(base, n) \ argument
239 (*(volatile uint8_t *)(base + n))
240 #define NPCX_DEVALT(base, n) \ argument
241 (*(volatile uint8_t *)(base + NPCX_DEVALT_OFFSET(n)))
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/Zephyr-latest/drivers/spi/
Dspi_mcux_flexio.c126 static void spi_flexio_master_init(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, in spi_flexio_master_init() argument
129 assert(base != NULL); in spi_flexio_master_init()
143 ctrlReg = base->flexioBase->CTRL; in spi_flexio_master_init()
153 base->flexioBase->CTRL = ctrlReg; in spi_flexio_master_init()
157 shifterConfig.timerSelect = base->timerIndex[0]; in spi_flexio_master_init()
159 shifterConfig.pinSelect = base->SDOPinIndex; in spi_flexio_master_init()
173 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); in spi_flexio_master_init()
176 shifterConfig.timerSelect = base->timerIndex[0]; in spi_flexio_master_init()
178 shifterConfig.pinSelect = base->SDIPinIndex; in spi_flexio_master_init()
190 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); in spi_flexio_master_init()
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Dspi_oc_simple.h13 ((mem_addr_t) (info->base + \
27 uint32_t base; member
/Zephyr-latest/kernel/
Dcpu_mask.c30 thread->base.cpu_mask |= enable_mask; in cpu_mask_mod()
31 thread->base.cpu_mask &= ~disable_mask; in cpu_mask_mod()
38 int m = thread->base.cpu_mask; in cpu_mask_mod()
Dstack.c33 stack->base = buffer; in k_stack_init()
34 stack->top = stack->base + num_entries; in k_stack_init()
91 k_free(stack->base); in k_stack_cleanup()
92 stack->base = NULL; in k_stack_cleanup()
158 if (likely(stack->next > stack->base)) { in z_impl_k_stack_pop()
185 *data = (stack_data_t)arch_current_thread()->base.swap_data; in z_impl_k_stack_pop()
/Zephyr-latest/lib/utils/
Dring_buffer.c15 int32_t base; in ring_buf_put_claim() local
17 base = buf->put_base; in ring_buf_put_claim()
18 wrap_size = buf->put_head - base; in ring_buf_put_claim()
22 base += buf->size; in ring_buf_put_claim()
30 *data = &buf->buffer[buf->put_head - base]; in ring_buf_put_claim()
82 int32_t base; in ring_buf_get_claim() local
84 base = buf->get_base; in ring_buf_get_claim()
85 wrap_size = buf->get_head - base; in ring_buf_get_claim()
89 base += buf->size; in ring_buf_get_claim()
97 *data = &buf->buffer[buf->get_head - base]; in ring_buf_get_claim()
/Zephyr-latest/drivers/mfd/
Dmfd_npm1300.c187 int mfd_npm1300_reg_read_burst(const struct device *dev, uint8_t base, uint8_t offset, void *data, in mfd_npm1300_reg_read_burst() argument
191 uint8_t buff[] = {base, offset}; in mfd_npm1300_reg_read_burst()
196 int mfd_npm1300_reg_read(const struct device *dev, uint8_t base, uint8_t offset, uint8_t *data) in mfd_npm1300_reg_read() argument
198 return mfd_npm1300_reg_read_burst(dev, base, offset, data, 1U); in mfd_npm1300_reg_read()
201 int mfd_npm1300_reg_write(const struct device *dev, uint8_t base, uint8_t offset, uint8_t data) in mfd_npm1300_reg_write() argument
204 uint8_t buff[] = {base, offset, data}; in mfd_npm1300_reg_write()
209 int mfd_npm1300_reg_write2(const struct device *dev, uint8_t base, uint8_t offset, uint8_t data1, in mfd_npm1300_reg_write2() argument
213 uint8_t buff[] = {base, offset, data1, data2}; in mfd_npm1300_reg_write2()
218 int mfd_npm1300_reg_update(const struct device *dev, uint8_t base, uint8_t offset, uint8_t data, in mfd_npm1300_reg_update() argument
227 ret = mfd_npm1300_reg_read(dev, base, offset, &reg); in mfd_npm1300_reg_update()
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/Zephyr-latest/drivers/crypto/
Dcrypto_mcux_dcp.c32 DCP_Type *base; member
103 status = DCP_AES_EncryptCbc(cfg->base, &session->handle, pkt->in_buf, in crypto_dcp_aes_cbc_encrypt()
134 status = DCP_AES_DecryptCbc(cfg->base, &session->handle, pkt->in_buf + iv_bytes, in crypto_dcp_aes_cbc_decrypt()
154 status = DCP_AES_EncryptEcb(cfg->base, &session->handle, pkt->in_buf, pkt->out_buf, in crypto_dcp_aes_ecb_encrypt()
174 status = DCP_AES_DecryptEcb(cfg->base, &session->handle, pkt->in_buf, pkt->out_buf, in crypto_dcp_aes_ecb_decrypt()
225 status = DCP_AES_SetKey(cfg->base, &session->handle, ctx->key.bit_stream, ctx->keylen); in crypto_dcp_cipher_begin_session()
253 status = DCP_HASH_Update(cfg->base, &session->hash_ctx, pkt->in_buf, pkt->in_len); in crypto_dcp_sha256()
262 status = DCP_HASH_Finish(cfg->base, &session->hash_ctx, pkt->out_buf, NULL); in crypto_dcp_sha256()
289 status = DCP_HASH_Init(cfg->base, &session->handle, &session->hash_ctx, kDCP_Sha256); in crypto_dcp_hash_begin_session()
321 DCP_Init(cfg->base, &hal_cfg); in crypto_dcp_init()
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/Zephyr-latest/drivers/mbox/
Dmbox_nxp_mailbox.c63 MAILBOX_Type *base; member
74 volatile uint32_t mailbox_value = MAILBOX_GetValue(config->base, cpu_id); in mailbox_isr()
78 MAILBOX_ClearValueBits(config->base, cpu_id, mailbox_value); in mailbox_isr()
123 MAILBOX_SetValueBits(cfg->base, MAILBOX_ID_OTHER_CPU, GEN0_IRQ_TRIGGER >> channel); in nxp_mailbox_send()
136 MAILBOX_SetValueBits(cfg->base, MAILBOX_ID_OTHER_CPU, in nxp_mailbox_send()
194 .base = (MAILBOX_Type *)DT_INST_REG_ADDR(idx), \
199 MAILBOX_Init(nxp_mailbox_##idx##_config.base); \
/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_ps.c53 dev_data->base = DEVICE_MMIO_NAMED_GET(dev, reg_base); in gpio_xlnx_ps_init()
54 __ASSERT(dev_data->base != 0, "%s map register space failed", dev->name); in gpio_xlnx_ps_init()
61 bank_data->base = dev_data->base; in gpio_xlnx_ps_init()
124 .base = 0x0,\
/Zephyr-latest/arch/arm/core/mpu/
Darm_mpu_v7_internal.h43 set_region_base_address(region_conf->base & MPU_RBAR_ADDR_Msk); in region_init()
47 MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk) in region_init()
51 index, region_conf->base, region_conf->attr.rasr); in region_init()
115 const k_mem_partition_attr_t *attr, uint32_t base, uint32_t size) in get_region_attr_from_mpu_partition_info() argument
120 (void) base; in get_region_attr_from_mpu_partition_info()
/Zephyr-latest/soc/snps/emsk/
Dlinker.ld14 * DRAM base address and size
25 /* Instruction Closely Coupled Memory (ICCM) base address and size */
33 * DCCM base address and size. DCCM is the data memory.
35 /* Data Closely Coupled Memory (DCCM) base address and size */
/Zephyr-latest/arch/x86/core/
Dmultiboot.c94 x86_memmap[index].base = mmap->base; in z_multiboot_init()
127 x86_memmap[0].base = 0; in z_multiboot_init()
132 x86_memmap[1].base = 1048576U; /* 1MB */ in z_multiboot_init()
/Zephyr-latest/drivers/sensor/st/stm32_digi_temp/
Dstm32_digi_temp.c43 DTS_TypeDef *base; member
54 DTS_TypeDef *dts = cfg->base; in stm32_digi_temp_isr()
67 DTS_TypeDef *dts = cfg->base; in stm32_digi_temp_sample_fetch()
115 DTS_TypeDef *dts = cfg->base; in stm32_digi_temp_configure()
141 DTS_TypeDef *dts = cfg->base; in stm32_digi_temp_enable()
154 DTS_TypeDef *dts = cfg->base; in stm32_digi_temp_disable()
168 DTS_TypeDef *dts = cfg->base; in stm32_digi_temp_init()
277 .base = (DTS_TypeDef *)DT_INST_REG_ADDR(index), \
/Zephyr-latest/drivers/usb/udc/
Dudc_dwc2_vendor_quirks.h66 mem_addr_t ggpio_reg = (mem_addr_t)&config->base->ggpio; in stm32f4_fsotg_enable_phy()
76 mem_addr_t ggpio_reg = (mem_addr_t)&config->base->ggpio; in stm32f4_fsotg_disable_phy()
268 struct usb_dwc2_reg *const base = config->base; in usbhs_post_hibernation_entry() local
271 sys_set_bits((mem_addr_t)&base->pcgcctl, USB_DWC2_PCGCCTL_GATEHCLK); in usbhs_post_hibernation_entry()
283 struct usb_dwc2_reg *const base = config->base; in usbhs_pre_hibernation_exit() local
286 sys_clear_bits((mem_addr_t)&base->pcgcctl, USB_DWC2_PCGCCTL_GATEHCLK); in usbhs_pre_hibernation_exit()
/Zephyr-latest/soc/snps/nsim/arc_classic/
Dlinker.ld13 /* Instruction Closely Coupled Memory (ICCM) base address and size */
21 * DCCM base address and size. DCCM is the data memory.
23 /* Data Closely Coupled Memory (DCCM) base address and size */
36 /* Flash memory base address and size */
/Zephyr-latest/subsys/shell/modules/kernel_service/thread/
Dlist.c81 thread->base.user_options, in shell_tdata_dump()
82 thread->base.prio, in shell_tdata_dump()
83 (int64_t)thread->base.timeout.dticks); in shell_tdata_dump()
89 shell_print(sh, "\tcpu_mask: 0x%x", thread->base.cpu_mask); in shell_tdata_dump()
/Zephyr-latest/drivers/misc/mcux_flexio/
Dmcux_flexio.c20 FLEXIO_Type *base; member
73 FLEXIO_Type *base = config->base; in mcux_flexio_isr() local
77 uint32_t shifter_status_flag = FLEXIO_GetShifterStatusFlags(base); in mcux_flexio_isr()
78 uint32_t shifter_error_flag = FLEXIO_GetShifterErrorFlags(base); in mcux_flexio_isr()
98 uint32_t timer_status_flag = FLEXIO_GetTimerStatusFlags(base); in mcux_flexio_isr()
128 FLEXIO_Init(config->base, &flexio_config); in mcux_flexio_init()
226 .base = (FLEXIO_Type *)DT_INST_REG_ADDR(n), \
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_xlnx_zynqmp.c15 static mm_reg_t base = DT_INST_REG_ADDR(0); variable
34 sys_write32(sel, base + mio_pin_offset * pins[i].pin); in pinctrl_configure_pins()
Dpinctrl_rv32m1.c36 PORT_Type *base = ports[PORT(pins[i])]; in pinctrl_configure_pins() local
40 base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_RV32M1_PCR_MASK)) | mux; in pinctrl_configure_pins()
/Zephyr-latest/subsys/portability/cmsis_rtos_v2/
Dkernel.c42 int temp = arch_current_thread()->base.sched_locked; in osKernelLock()
58 int temp = arch_current_thread()->base.sched_locked; in osKernelUnlock()
74 arch_current_thread()->base.sched_locked = lock; in osKernelRestoreLock()
/Zephyr-latest/drivers/entropy/
Dentropy_neorv32_trng.c27 mm_reg_t base; member
34 return sys_read32(config->base); in neorv32_trng_read_ctrl()
41 sys_write32(ctrl, config->base); in neorv32_trng_write_ctrl()
138 .base = DT_INST_REG_ADDR(n), \
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dsoc.c455 struct usbpd_it8xxx2_regs *base; in ite_it8xxx2_init() local
458 base = (struct usbpd_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(usbpd0)); in ite_it8xxx2_init()
460 base = (struct usbpd_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(usbpd1)); in ite_it8xxx2_init()
467 base->CCGCR |= (IT8XXX2_USBPD_DISABLE_CC | in ite_it8xxx2_init()
473 base->CCCSR |= (IT8XXX2_USBPD_CC2_DISCONNECT | in ite_it8xxx2_init()
478 base->CCPSR |= (IT8XXX2_USBPD_DISCONNECT_POWER_CC2 | in ite_it8xxx2_init()
481 base->CCPSR |= (IT8XXX2_USBPD_DISCONNECT_5_1K_CC2_DB | in ite_it8xxx2_init()
/Zephyr-latest/drivers/i2s/
Di2s_litex.c328 int channels_concatenated = litex_read8(cfg->base + I2S_STATUS_OFFSET); in i2s_litex_configure()
329 int dev_audio_freq = i2s_get_audio_freq(cfg->base); in i2s_litex_configure()
385 int dev_sample_width = i2s_get_sample_width(cfg->base); in i2s_litex_configure()
394 int dev_format = i2s_get_foramt(cfg->base); in i2s_litex_configure()
474 i2s_irq_enable(cfg->base, I2S_EV_READY); in i2s_litex_write()
506 i2s_reset_fifo(cfg->base); in i2s_litex_trigger()
507 i2s_enable(cfg->base); in i2s_litex_trigger()
508 i2s_irq_enable(cfg->base, I2S_EV_READY); in i2s_litex_trigger()
518 i2s_disable(cfg->base); in i2s_litex_trigger()
519 i2s_irq_disable(cfg->base, I2S_EV_READY); in i2s_litex_trigger()
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