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/Zephyr-latest/samples/drivers/adc/adc_sequence/boards/
Dlpcxpresso55s69_cpu0.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 * - Connect VREFN_TARGET to GND, and VREFP_TARGET to 3v3
24 * - Connect LPADC0 CH0A signal to voltage between 0~3.3V (P19 pin 4)
25 * - Connect LPADC0 CH0B signal to voltage between 0~3.3V (P19 pin 2)
26 * LPADC0 CH4A is set up in single ended mode
27 * - Connect LPADC0 CH4A signal to voltage between 0~3.3V (P17 pin 19)
28 * LPADC0 CH4B is set up in single ended mode
[all …]
Dmimxrt595_evk_cm33.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 * LPADC0 CH0A and CH0B are set up in differential mode (B-A)
22 * - Connect LPADC0 CH0A signal to voltage between 0~1.8V (J30 pin 1)
23 * - Connect LPADC0 CH0B signal to voltage between 0~1.8V (J30 pin 2)
24 * LPADC0 CH2A is set up in single ended mode
25 * - Connect LPADC0 CH2A signal to voltage between 0~1.8V (J30 pin 3)
32 zephyr,vref-mv = <1800>;
[all …]
/Zephyr-latest/samples/drivers/adc/adc_dt/boards/
Dlpcxpresso55s69_lpc55s69_cpu0.overlay2 * SPDX-License-Identifier: Apache-2.0
4 * Copyright 2022-2024 NXP
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
11 io-channels = <&adc0 0 &adc0 1 &adc0 2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 * - Connect VREFN_TARGET to GND, and VREFP_TARGET to 3v3
24 * - Connect LPADC0 CH0A signal to voltage between 0~3.3V (P19 pin 4)
25 * - Connect LPADC0 CH0B signal to voltage between 0~3.3V (P19 pin 2)
26 * LPADC0 CH4A is set up in single ended mode
[all …]
Dmimxrt595_evk_mimxrt595s_cm33.overlay2 * SPDX-License-Identifier: Apache-2.0
5 * Copyright 2023-2024 NXP
8 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
13 io-channels = <&lpadc0 0>, <&lpadc0 1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 * LPADC0 CH0A and CH0B are set up in differential mode (B-A)
24 * - Connect LPADC0 CH0A signal to voltage between 0~1.8V (J30 pin 1)
25 * - Connect LPADC0 CH0B signal to voltage between 0~1.8V (J30 pin 2)
26 * LPADC0 CH2A is set up in single ended mode
[all …]
Dfrdm_mcxn236.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/adc.h>
8 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
13 io-channels = <&lpadc0 0>, <&lpadc0 1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 * LPADC0 CH1A and CH1B are set up in differential mode (B-A)
24 * - Connect LPADC0 CH1A signal to voltage between 0~1.8V (J4 pin 4)
25 * - Connect LPADC0 CH1B signal to voltage between 0~1.8V (J8 pin 11)
26 * LPADC0 CH2A is set up in single ended mode
[all …]
Dfrdm_mcxn947_mcxn947_cpu0.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/adc.h>
8 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
13 io-channels = <&lpadc0 0>, <&lpadc0 1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 * LPADC0 CH1A and CH1B are set up in differential mode (B-A)
24 * - Connect LPADC0 CH1A signal to voltage between 0~1.8V (J8 pin 20)
25 * - Connect LPADC0 CH1B signal to voltage between 0~1.8V (J8 pin 24)
26 * LPADC0 CH2A is set up in single ended mode
[all …]
Dfrdm_mcxn947_mcxn947_cpu0_qspi.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/adc.h>
8 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
13 io-channels = <&lpadc0 0>, <&lpadc0 1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 * LPADC0 CH1A and CH1B are set up in differential mode (B-A)
24 * - Connect LPADC0 CH1A signal to voltage between 0~1.8V (J8 pin 20)
25 * - Connect LPADC0 CH1B signal to voltage between 0~1.8V (J8 pin 24)
26 * LPADC0 CH2A is set up in single ended mode
[all …]
/Zephyr-latest/tests/drivers/adc/adc_api/boards/
Dlpcxpresso55s69_lpc55s69_cpu0.overlay2 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
11 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 * Channel 0 is used in single ended mode, with 12 bit resolution
27 zephyr,vref-mv = <3300>;
28 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
30 zephyr,input-positive = <MCUX_LPADC_CH0A>;
34 * Channel 1 is used in single ended mode, with 16 bit resolution
[all …]
Dlpcxpresso55s69_lpc55s69_cpu0_ns.overlay2 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
11 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 * Channel 0 is used in single ended mode, with 12 bit resolution
27 zephyr,vref-mv = <3300>;
28 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
30 zephyr,input-positive = <MCUX_LPADC_CH0A>;
34 * Channel 1 is used in single ended mode, with 16 bit resolution
[all …]
/Zephyr-latest/dts/bindings/clock/
Dmicrochip,xec-pcr.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
25 pll-32k-src:
30 periph-32k-src:
35 xtal-single-ended:
37 description: Use single ended crystal connection to XTAL2 pin.
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Dgpio.h5 * SPDX-License-Identifier: Apache-2.0
39 /* Configures GPIO output in single-ended mode (open drain or open source). */
41 /* Configures GPIO output in push-pull mode */
44 /* Indicates single ended open drain mode (wired AND). */
46 /* Indicates single ended open source mode (wired OR). */
74 /** Enables GPIO pin pull-up. */
77 /** Enable GPIO pin pull-down. */
/Zephyr-latest/samples/drivers/clock_control_xec/
DREADME.rst28 Dual-ended 32KHz Crystal jumper configuration
31 Jumper on JP1 1-2 connect crystal Y1 pin 1 to MEC172x XTAL1
32 Jumper on JP2 2-3 connect crystal Y1 pin 2 to MEC172x XTAL2
39 External single-ended 32KHz waveform to MEC172x XTAL2 input
43 Jumper on JP2 1-2 connect external 32KHz signal to XTAL2
47 Jumper on JP121 pins 3-4 connect U15 32KHz output to
50 External single-ended 32KHz waveform to MEC172x 32KHZ_IN pin
58 Jumper on JP121 pins 1-2 connect U15 32KHz output to
64 .. code-block:: console
/Zephyr-latest/include/zephyr/drivers/comparator/
Dnrf_comp.h4 * SPDX-License-Identifier: Apache-2.0
78 /** Low-power mode */
82 /** High-speed mode */
99 * @brief Single-ended mode configuration structure
123 * @brief Configure comparator in single-ended mode
126 * @param config Single-ended mode configuration
129 * @retval negative errno-code otherwise
155 * @retval negative errno-code otherwise
/Zephyr-latest/samples/boards/bbc/microbit/pong/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
21 /* The micro:bit has a 5x5 LED display, using (x, y) notation the top-left
22 * corner has coordinates (0, 0) and the bottom-right has (4, 4). To make
24 * system where top-left is (0, 0) and bottom-right is (49, 49).
37 #define BALL_VEL_Y_START -4 /* Default ball vertical speed */
52 /* Ball starting position (just to the left of the paddle mid-point) */
63 SINGLE, enumerator
84 { SINGLE, "Single" },
90 static int64_t ended; variable
161 SCROLL_SPEED, "%s", select->choice[select_idx].str); in pong_select()
[all …]
/Zephyr-latest/samples/drivers/clock_control_xec/boards/
Dmec1501modular_assy6885.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
15 xtal-single-ended;
16 internal-osc-disable;
19 pinctrl-0 = <&tst_clk_out_gpio060 &clk_32khz_out_gpio221>;
22 /* pinctrl-0 = <&clk_32khz_in_gpio165>; */
25 /* pinctrl-0 = <&clk_32khz_in_gpio165
29 pinctrl-names = "default";
Dmec15xxevb_assy6853.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
15 xtal-single-ended;
16 internal-osc-disable;
19 pinctrl-0 = <&tst_clk_out_gpio060 &clk_32khz_out_gpio221>;
22 /* pinctrl-0 = <&clk_32khz_in_gpio165>; */
25 /* pinctrl-0 = <&clk_32khz_in_gpio165
29 pinctrl-names = "default";
Dmec172xevb_assy6906.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
15 xtal-single-ended;
16 internal-osc-disable;
19 pinctrl-0 = <&tst_clk_out_gpio060 &clk_32khz_out_gpio221>;
22 /* pinctrl-0 = <&clk_32khz_in_gpio165>; */
25 /* pinctrl-0 = <&clk_32khz_in_gpio165
29 pinctrl-names = "default";
/Zephyr-latest/drivers/adc/
Dadc_b91.c4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/adc/b91-adc.h>
51 if (sequence->options) { in adc_b91_validate_buffer_size()
52 needed *= (1 + sequence->options->extra_samplings); in adc_b91_validate_buffer_size()
55 if (sequence->buffer_size < needed) { in adc_b91_validate_buffer_size()
56 return -ENOMEM; in adc_b91_validate_buffer_size()
67 if (sequence->channels != BIT(0)) { in adc_b91_validate_sequence()
69 return -ENOTSUP; in adc_b91_validate_sequence()
72 if (sequence->oversampling) { in adc_b91_validate_sequence()
74 return -ENOTSUP; in adc_b91_validate_sequence()
[all …]
Dadc_nrfx_saadc.c4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/adc/nrf-saadc-v3.h>
11 #include <zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h>
68 "Definitions from nrf-adc.h do not match those from nrf_saadc.h");
112 if (NRF_SAADC_8BIT_SAMPLE_WIDTH == 8 && sequence->resolution == 8) { in samples_to_bytes()
147 result = -EINVAL; in adc_convert_acq_time()
162 tacq = (nrf_saadc_acqtime_t)(acq_time / MINIMUM_ACQ_TIME_IN_NS) - 1; in adc_convert_acq_time()
164 result = -EINVAL; in adc_convert_acq_time()
190 return -ENOTSUP; in saadc_pm_hook()
204 uint8_t channel_id = channel_cfg->channel_id; in adc_nrfx_channel_setup()
[all …]
Dadc_sam.c4 * SPDX-License-Identifier: Apache-2.0
69 const struct adc_sam_config *const cfg = dev->config; in adc_sam_channel_setup()
70 Adc *const adc = cfg->regs; in adc_sam_channel_setup()
72 uint8_t channel_id = channel_cfg->channel_id; in adc_sam_channel_setup()
74 if (channel_cfg->differential) { in adc_sam_channel_setup()
75 if (channel_id != (channel_cfg->input_positive / 2U) in adc_sam_channel_setup()
76 || channel_id != (channel_cfg->input_negative / 2U)) { in adc_sam_channel_setup()
78 return -EINVAL; in adc_sam_channel_setup()
81 if (channel_id != channel_cfg->input_positive) { in adc_sam_channel_setup()
82 LOG_ERR("Invalid ADC single-ended input for channel %u", channel_id); in adc_sam_channel_setup()
[all …]
/Zephyr-latest/dts/bindings/comparator/
Dnordic,nrf-comp.yaml2 # SPDX-License-Identifier: Apache-2.0
13 compatible = "nordic,nrf-comp";
23 single-ended mode, selecting an internal reference:
27 main-mode = "SE";
30 sp-mode = "NORMAL";
31 th-up = <36>;
32 th-down = <30>;
51 main-mode = "DIFF";
54 sp-mode = "NORMAL";
55 enable-hyst;
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dti,fdc2x1x.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 sd-gpios:
12 type: phandle-array
18 intb-gpios:
19 type: phandle-array
28 Set to identify the sensor as FDC2114 or FDC2214 (4-channel version)
33 Set the Auto-Scan Mode.
35 false = Continuous conversion on the single channel selected by
36 "active-channel" (single channel mode).
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_vbat.h4 * SPDX-License-Identifier: Apache-2.0
16 /* Offset 0x00 Power-Fail and Reset Status */
48 /* single ended crystal on XTAL2 instead of parallel across XTAL1 and XTAL2 */
77 * Monotonic Counter least significant word (32-bit), read-only.
82 /* Monotonic Counter most significant word (32-bit). Read-Write */
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_adc.h4 * SPDX-License-Identifier: Apache-2.0
14 /* 16 ADC channels numbered 0 - 15 */
18 /* Eight ADC channels numbered 0 - 7 */
49 /* Single Conversion Select register */
134 /* Select single ended or differential operation */
164 volatile uint32_t SINGLE; member
167 uint8_t RSVD1[0x7c - ((MCHP_ADC_MAX_CHAN * 4) + 0x14)];
/Zephyr-latest/tests/boards/nrf/comp/src/
Dtest.c4 * SPDX-License-Identifier: Apache-2.0
43 * @brief Configure comparator in single-ended mode with
74 * @brief Configure comparator in single-ended mode with

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