1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC_ADC_H 8 #define _MEC_ADC_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 #if defined(CONFIG_SOC_MEC172X_NLJ) 14 /* 16 ADC channels numbered 0 - 15 */ 15 #define MCHP_ADC_MAX_CHAN 16u 16 #define MCHP_ADC_MAX_CHAN_MASK 0x0fu 17 #else 18 /* Eight ADC channels numbered 0 - 7 */ 19 #define MCHP_ADC_MAX_CHAN 8u 20 #define MCHP_ADC_MAX_CHAN_MASK 0x07u 21 #endif 22 23 /* Control register */ 24 #define MCHP_ADC_CTRL_REG_OFS 0u 25 #define MCHP_ADC_CTRL_REG_MASK 0xdfu 26 #define MCHP_ADC_CTRL_REG_RW_MASK 0x1fu 27 #define MCHP_ADC_CTRL_REG_RW1C_MASK 0xc0u 28 #define MCHP_ADC_CTRL_ACTV BIT(0) 29 #define MCHP_ADC_CTRL_START_SNGL BIT(1) 30 #define MCHP_ADC_CTRL_START_RPT BIT(2) 31 #define MCHP_ADC_CTRL_PWRSV_DIS BIT(3) 32 #define MCHP_ADC_CTRL_SRST BIT(4) 33 #define MCHP_ADC_CTRL_RPT_DONE_STS BIT(6) /* R/W1C */ 34 #define MCHP_ADC_CTRL_SNGL_DONE_STS BIT(7) /* R/W1C */ 35 36 /* Delay register. Start and repeat delays in units of 40 us */ 37 #define MCHP_ADC_DELAY_REG_OFS 4u 38 #define MCHP_ADC_DELAY_REG_MASK 0xffffffffu 39 #define MCHP_ADC_DELAY_START_POS 0u 40 #define MCHP_ADC_DELAY_START_MASK 0xffffu 41 #define MCHP_ADC_DELAY_RPT_POS 16u 42 #define MCHP_ADC_DELAY_RPT_MASK 0xffff0000u 43 44 /* Status register. 0 <= n < MCHP_ADC_MAX_CHAN */ 45 #define MCHP_ADC_STATUS_REG_OFS 8u 46 #define MCHP_ADC_STATUS_REG_MASK 0xffffu 47 #define MCHP_ADC_STATUS_CHAN(n) BIT(n) 48 49 /* Single Conversion Select register */ 50 #define MCHP_ADC_SCS_REG_OFS 0x0cu 51 #if defined(CONFIG_SOC_MEC172X_NLJ) 52 #define MCHP_ADC_SCS_REG_MASK 0xffffu 53 #define MCHP_ADC_SCS_CH_0_15 0xffffu 54 #define MCHP_ADC_SCS_CH(n) BIT(((n) & 0x0fu)) 55 #else 56 #define MCHP_ADC_SCS_REG_MASK 0xffu 57 #define MCHP_ADC_SCS_CH_0_7 0xffu 58 #define MCHP_ADC_SCS_CH(n) BIT(((n) & 0x07u)) 59 #endif 60 61 /* Repeat Conversion Select register */ 62 #define MCHP_ADC_RCS_REG_OFS 0x10u 63 #if defined(CONFIG_SOC_MEC172X_NLJ) 64 #define MCHP_ADC_RCS_REG_MASK 0xffffu 65 #define MCHP_ADC_RCS_CH_0_15 0xffffu 66 #define MCHP_ADC_RCS_CH(n) BIT(((n) & 0x0fu)) 67 #else 68 #define MCHP_ADC_RCS_REG_MASK 0xffu 69 #define MCHP_ADC_RCS_CH_0_7 0xffu 70 #define MCHP_ADC_RCS_CH(n) BIT(((n) & 0x07u)) 71 #endif 72 73 /* Channel reading registers */ 74 #define MCHP_ADC_RDCH_REG_MASK 0xfffu 75 #define MCHP_ADC_RDCH0_REG_OFS 0x14u 76 #define MCHP_ADC_RDCH1_REG_OFS 0x18u 77 #define MCHP_ADC_RDCH2_REG_OFS 0x1cu 78 #define MCHP_ADC_RDCH3_REG_OFS 0x20u 79 #define MCHP_ADC_RDCH4_REG_OFS 0x24u 80 #define MCHP_ADC_RDCH5_REG_OFS 0x28u 81 #define MCHP_ADC_RDCH6_REG_OFS 0x2cu 82 #define MCHP_ADC_RDCH7_REG_OFS 0x30u 83 #define MCHP_ADC_RDCH8_REG_OFS 0x34u 84 #define MCHP_ADC_RDCH9_REG_OFS 0x38u 85 #define MCHP_ADC_RDCH10_REG_OFS 0x3cu 86 #define MCHP_ADC_RDCH11_REG_OFS 0x40u 87 #define MCHP_ADC_RDCH12_REG_OFS 0x44u 88 #define MCHP_ADC_RDCH13_REG_OFS 0x48u 89 #define MCHP_ADC_RDCH14_REG_OFS 0x4cu 90 #define MCHP_ADC_RDCH15_REG_OFS 0x50u 91 92 /* Configuration register */ 93 #define MCHP_ADC_CFG_REG_OFS 0x7cu 94 #define MCHP_ADC_CFG_REG_MASK 0xffffu 95 #define MCHP_ADC_CFG_CLK_LO_TIME_POS 0 96 #define MCHP_ADC_CFG_CLK_LO_TIME_MASK0 0xffu 97 #define MCHP_ADC_CFG_CLK_LO_TIME_MASK 0xffu 98 #define MCHP_ADC_CFG_CLK_HI_TIME_POS 8 99 #define MCHP_ADC_CFG_CLK_HI_TIME_MASK0 0xffu 100 #define MCHP_ADC_CFG_CLK_HI_TIME_MASK SHLU32(0xffu, 8) 101 102 /* Channel Vref Select register */ 103 #define MCHP_ADC_CH_VREF_SEL_REG_OFS 0x80u 104 #define MCHP_ADC_CH_VREF_SEL_REG_MASK 0x00ffffffu 105 #if defined(CONFIG_SOC_MEC172X_NLJ) 106 #define MCHP_ADC_CH_VREF_SEL_MASK(n) SHLU32(0x03u, (((n) & 0x0f) * 2u)) 107 #define MCHP_ADC_CH_VREF_SEL_PAD(n) 0u 108 #define MCHP_ADC_CH_VREF_SEL_GPIO(n) SHLU32(0x01u, (((n) & 0x0f) * 2u)) 109 #else 110 #define MCHP_ADC_CH_VREF_SEL_MASK(n) SHLU32(0x03u, (((n) & 0x07) * 2u)) 111 #define MCHP_ADC_CH_VREF_SEL_PAD(n) 0u 112 #define MCHP_ADC_CH_VREF_SEL_GPIO(n) SHLU32(0x01u, (((n) & 0x07) * 2u)) 113 #endif 114 115 /* Vref Control register */ 116 #define MCHP_ADC_VREF_CTRL_REG_OFS 0x84u 117 #define MCHP_ADC_VREF_CTRL_REG_MASK 0xffffffffu 118 #define MCHP_ADC_VREF_CTRL_CHRG_DEL_POS 0 119 #define MCHP_ADC_VREF_CTRL_CHRG_DEL_MASK0 0xffffu 120 #define MCHP_ADC_VREF_CTRL_CHRG_DEL_MASK 0xffffu 121 #define MCHP_ADC_VREF_CTRL_SW_DEL_POS 16 122 #define MCHP_ADC_VREF_CTRL_SW_DEL_MASK0 0x1fffu 123 #define MCHP_ADC_VREF_CTRL_SW_DEL_MASK SHLU32(0x1fffu, 16) 124 #define MCHP_ADC_VREF_CTRL_PAD_POS 29 125 #define MCHP_ADC_VREF_CTRL_PAD_UNUSED_FLOAT 0u 126 #define MCHP_ADC_VREF_CTRL_PAD_UNUSED_DRIVE_LO BIT(29) 127 #define MCHP_ADC_VREF_CTRL_SEL_STS_POS 30 128 #define MCHP_ADC_VREF_CTRL_SEL_STS_MASK0 0x03u 129 #define MCHP_ADC_VREF_CTRL_SEL_STS_MASK SHLU32(3u, 30) 130 131 /* SAR ADC Control register */ 132 #define MCHP_ADC_SAR_CTRL_REG_OFS 0x88u 133 #define MCHP_ADC_SAR_CTRL_REG_MASK 0x0001ff8fu 134 /* Select single ended or differential operation */ 135 #define MCHP_ADC_SAR_CTRL_SELDIFF_POS 0 136 #define MCHP_ADC_SAR_CTRL_SELDIFF_DIS 0u 137 #define MCHP_ADC_SAR_CTRL_SELDIFF_EN BIT(0) 138 /* Select resolution */ 139 #define MCHP_ADC_SAR_CTRL_RES_POS 1 140 #define MCHP_ADC_SAR_CTRL_RES_MASK0 0x03u 141 #define MCHP_ADC_SAR_CTRL_RES_MASK 0x06u 142 #define MCHP_ADC_SAR_CTRL_RES_10_BITS 0x04u 143 #define MCHP_ADC_SAR_CTRL_RES_12_BITS 0x06u 144 /* Shift data in reading register */ 145 #define MCHP_ADC_SAR_CTRL_SHIFTD_POS 3 146 #define MCHP_ADC_SAR_CTRL_SHIFTD_DIS 0u 147 #define MCHP_ADC_SAR_CTRL_SHIFTD_EN BIT(3) 148 /* Warm up delay in ADC clock cycles */ 149 #define MCHP_ADC_SAR_CTRL_WUP_DLY_POS 7 150 #define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK0 0x3ffu 151 #define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK SHLU32(0x3ffu, 7) 152 #define MCHP_ADC_SAR_CTRL_WUP_DLY_DFLT SHLU32(0x202u, 7) 153 154 /* Register interface */ 155 #define MCHP_ADC_CH_NUM(n) ((n) & MCHP_ADC_MAX_CHAN_MASK) 156 #define MCHP_ADC_CH_OFS(n) (MCHP_ADC_CH_NUM(n) * 4u) 157 #define MCHP_ADC_CH_ADDR(n) (MCHP_ADC_BASE_ADDR + MCHP_ADC_CH_OFS(n)) 158 159 /** @brief Analog to Digital Converter Registers (ADC) */ 160 struct adc_regs { 161 volatile uint32_t CONTROL; 162 volatile uint32_t DELAY; 163 volatile uint32_t STATUS; 164 volatile uint32_t SINGLE; 165 volatile uint32_t REPEAT; 166 volatile uint32_t RD[MCHP_ADC_MAX_CHAN]; 167 uint8_t RSVD1[0x7c - ((MCHP_ADC_MAX_CHAN * 4) + 0x14)]; 168 volatile uint32_t CONFIG; 169 volatile uint32_t VREF_CHAN_SEL; 170 volatile uint32_t VREF_CTRL; 171 volatile uint32_t SARADC_CTRL; 172 }; 173 174 #endif /* #ifndef _MEC_ADC_H */ 175
