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Searched +full:pll +full:- +full:lock +full:- +full:timeout +full:- +full:ms (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/dts/bindings/clock/
Dmicrochip,xec-pcr.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
25 pll-32k-src:
28 description: 32 KHz clock source for PLL
30 periph-32k-src:
35 xtal-single-ended:
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/Zephyr-latest/soc/microchip/mec/mec172x/
Dpower.c5 * SPDX-License-Identifier: Apache-2.0
27 * Lower power dissipation, 48MHz PLL is off
30 * between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
34 * We touch the Cortex-M's primary mask and base priority registers
43 * PLL. Firmware should not disable JTAG/SWD in the EC subsystem
45 * TAP controller in a state of requesting clocks preventing the PLL
67 * Set MCHP Heavy sleep (PLL OFF when all CLK_REQ clear) and SLEEP_ALL in z_power_soc_deep_sleep()
72 SCB->SCR |= BIT(2); in z_power_soc_deep_sleep()
73 pcr->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_HEAVY; in z_power_soc_deep_sleep()
74 pcr->OSC_ID = pcr->SYS_SLP_CTRL; in z_power_soc_deep_sleep()
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/Zephyr-latest/drivers/timer/
Dite_it8xxx2_timer.c3 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
19 #define COUNT_1US (EC_FREQ / USEC_PER_SEC - 1)
53 * timer2 only one shot to wake up chip and change pll.
61 #define MS_TO_COUNT(hz, ms) ((hz) * (ms) / 1000) argument
76 static struct k_spinlock lock; variable
109 * We are here because we have completed changing PLL sequence, in timer_5ms_one_shot_isr()
117 * changing PLL sequence.
135 timer2_reg->ET2PSR = EXT_PSR_32P768K; in timer_5ms_one_shot()
141 hw_cnt = MS_TO_COUNT(32768, 5/*ms*/); in timer_5ms_one_shot()
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/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
99 uint32_t RSVD4[(0x00c0 - 0x0094) / 4];
192 uint8_t core_clk_div; /* Cortex-M4 clock divider (CPU and NVIC) */
208 pcr->SYS_SLP_CTRL = 0U; in pcr_slp_init()
209 SCB->SCR &= ~BIT(2); in pcr_slp_init()
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/Zephyr-latest/drivers/ieee802154/
Dieee802154_dw1000_regs.h4 * SPDX-License-Identifier: Apache-2.0
7 * https://github.com/Decawave/mynewt-dw1000-core.git
14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved
24 * http://www.apache.org/licenses/LICENSE-2.0
75 /* Frame Filtering Behave as a Co-ordinator */
114 /* Receive Wait Timeout Enable. */
117 * Receiver Auto-Re-enable.
118 * This bit is used to cause the receiver to re-enable automatically
126 /* System Time Counter (40-bit) */
180 * of non-standard values
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/Zephyr-latest/dts/arm/microchip/
Dmec1501hsz.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4";
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Dmec172x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "microchip,xec-pcr";
13 reg-names = "pcrr", "vbatr";
15 core-clock-div = <1>;
17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
19 clk32kmon-period-min = <1435>;
20 clk32kmon-period-max = <1495>;
21 clk32kmon-duty-cycle-var-max = <132>;
22 clk32kmon-valid-min = <4>;
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/Zephyr-latest/doc/releases/
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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Drelease-notes-2.7.rst17 * Support for M-Profile Vector Extensions (MVE) on ARMv8.1-M
18 * Improved thread safety for Newlib and C++ on SMP-capable systems
20 * New Action-based Power Management API
23 * Linker Support for Tightly-Coupled Memory in RISC-V
25 * Support for extended PCI / PCIe capabilities, improved MIS-X support
33 * The kernel now supports both 32- and 64-bit architectures
36 * We added support for Point-to-Point Protocol (PPP)
37 * We added support for UpdateHub, an end-to-end solution for over-the-air device updates
38 * We added support for ARM Cortex-R Architecture
40 * Expanded support for ARMv6-M architecture
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Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
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