Lines Matching +full:pll +full:- +full:lock +full:- +full:timeout +full:- +full:ms

5  * SPDX-License-Identifier: Apache-2.0
27  * Lower power dissipation, 48MHz PLL is off
30  * between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
34  * We touch the Cortex-M's primary mask and base priority registers
43  * PLL. Firmware should not disable JTAG/SWD in the EC subsystem
45  * TAP controller in a state of requesting clocks preventing the PLL
67 	 * Set MCHP Heavy sleep (PLL OFF when all CLK_REQ clear) and SLEEP_ALL  in z_power_soc_deep_sleep()
72 	SCB->SCR |= BIT(2);  in z_power_soc_deep_sleep()
73 	pcr->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_HEAVY;  in z_power_soc_deep_sleep()
74 	pcr->OSC_ID = pcr->SYS_SLP_CTRL;  in z_power_soc_deep_sleep()
86 	 * PM post ops. This de-asserts peripheral SLP_EN signals.  in z_power_soc_deep_sleep()
88 	pcr->SYS_SLP_CTRL = 0U;  in z_power_soc_deep_sleep()
89 	SCB->SCR &= ~BIT(2);  in z_power_soc_deep_sleep()
91 	/* Wait for PLL to lock with timeout */  in z_power_soc_deep_sleep()
92 	htmr0->PRLD = 0U; /* make sure its stopped */  in z_power_soc_deep_sleep()
93 	htmr0->CTRL = 0U; /* 30.5 us per tick */  in z_power_soc_deep_sleep()
94 	htmr0->PRLD = 216U; /* ~6.6 ms 2x the expected lock time */  in z_power_soc_deep_sleep()
95 	temp = htmr0->PRLD;  in z_power_soc_deep_sleep()
96 	while ((pcr->OSC_ID & MCHP_PCR_OSC_ID_PLL_LOCK) == 0) {  in z_power_soc_deep_sleep()
97 		temp = htmr0->PRLD;  in z_power_soc_deep_sleep()
103 	htmr0->PRLD = 0U; /* stop */  in z_power_soc_deep_sleep()
117  * Higher power dissipation, 48MHz PLL remains on.
129 	SCB->SCR &= ~BIT(2);  in z_power_soc_sleep()
130 	pcr->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_LIGHT;  in z_power_soc_sleep()
131 	pcr->OSC_ID = pcr->SYS_SLP_CTRL;  in z_power_soc_sleep()
137 	pcr->SYS_SLP_CTRL = 0U;  in z_power_soc_sleep()
163  * arch_irq_lock() which sets BASEPRI to a non-zero value masking interrupts at
166  * ISR on wake except for faults. We re-enable interrupts by undoing global disable