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/Zephyr-latest/dts/bindings/counter/
Dnxp,pit.yaml1 # Copyright 2020,2023-2024 NXP
2 # SPDX-License-Identifier: Apache-2.0
17 max-load-value:
20 description: maximum load value supported
/Zephyr-latest/drivers/watchdog/
Dwdt_cmsdk_apb.c4 * SPDX-License-Identifier: Apache-2.0
21 /* offset: 0x000 (r/w) watchdog load register */
22 volatile uint32_t load; member
23 /* offset: 0x004 (r/ ) watchdog value register */
24 volatile uint32_t value; member
56 * Value written to the LOCK register to lock or unlock the write access
68 /* watchdog reload value in clock cycles */
81 wdog->lock = CMSDK_APB_WDOG_UNLOCK_VALUE; in wdog_cmsdk_apb_unlock()
92 wdog->ctrl = (CMSDK_APB_WDOG_CTRL_RESEN | CMSDK_APB_WDOG_CTRL_INTEN); in wdog_cmsdk_apb_setup()
104 wdog->ctrl = ~(CMSDK_APB_WDOG_CTRL_RESEN | CMSDK_APB_WDOG_CTRL_INTEN); in wdog_cmsdk_apb_disable()
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Dwdt_rpi_pico.c4 * SPDX-License-Identifier: Apache-2.0
20 /* Maximum watchdog time is halved due to errata RP2040-E1 */
32 uint32_t load; member
43 const struct wdt_rpi_pico_config *config = dev->config; in wdt_rpi_pico_setup()
44 struct wdt_rpi_pico_data *data = dev->data; in wdt_rpi_pico_setup()
49 return -ENOTSUP; in wdt_rpi_pico_setup()
52 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in wdt_rpi_pico_setup()
54 psm_hw->wdsel = 0; in wdt_rpi_pico_setup()
57 if (data->reset_type == WDT_FLAG_RESET_SOC) { in wdt_rpi_pico_setup()
58 hw_set_bits(&psm_hw->wdsel, PSM_WDSEL_BITS); in wdt_rpi_pico_setup()
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/Zephyr-latest/dts/bindings/regulator/
Dregulator.yaml1 # Copyright 2019-2020, Peter Bigot Consulting, LLC
3 # SPDX-License-Identifier: Apache-2.0
14 regulator-name:
18 regulator-init-microvolt:
22 regulator-min-microvolt:
26 regulator-max-microvolt:
30 regulator-microvolt-offset:
34 regulator-init-microamp:
38 regulator-min-microamp:
42 regulator-max-microamp:
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/Zephyr-latest/arch/riscv/core/
Duserspace.S6 * SPDX-License-Identifier: Apache-2.0
29 sw a5, 0(a2) # Init error value to 0
34 lbu a4, 0(a4) # Load string's character
38 bne a5, a1, continue # Check if max length is reached
41 mv a0, a5 # Return counter value (length)
49 li a4, -1 # Put error to -1
/Zephyr-latest/samples/sensor/bq274xx/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
12 static void bq274xx_show_values(const char *type, struct sensor_value value) in bq274xx_show_values() argument
14 if ((value.val2 < 0) && (value.val1 >= 0)) { in bq274xx_show_values()
15 value.val2 = -(value.val2); in bq274xx_show_values()
16 printk("%s: -%d.%06d\n", type, value.val1, value.val2); in bq274xx_show_values()
17 } else if ((value.val2 > 0) && (value.val1 < 0)) { in bq274xx_show_values()
18 printk("%s: %d.%06d\n", type, value.val1, value.val2); in bq274xx_show_values()
19 } else if ((value.val2 < 0) && (value.val1 < 0)) { in bq274xx_show_values()
20 value.val2 = -(value.val2); in bq274xx_show_values()
21 printk("%s: %d.%06d\n", type, value.val1, value.val2); in bq274xx_show_values()
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/Zephyr-latest/dts/bindings/input/
Dst,stmpe811.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [i2c-device.yaml, touchscreen-common.yaml]
11 int-gpios:
12 type: phandle-array
17 raw-x-min:
23 raw-y-min:
29 raw-x-max:
35 raw-y-max:
41 panel-driver-settling-time-us:
44 - 10
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/Zephyr-latest/drivers/timer/
Dcortex_m_systick.c4 * SPDX-License-Identifier: Apache-2.0
20 #define MAX_TICKS ((k_ticks_t)(COUNTER_MAX / CYC_PER_TICK) - 1)
25 * reliably" -- it becomes the minimum value of the LOAD register, and
32 #define MIN_DELAY MAX(1024U, ((uint32_t)CYC_PER_TICK/16U))
49 * At an arbitrary point in time the "current" value of the SysTick
61 * Additions/subtractions/comparisons of 64-bits values on 32-bits systems
63 * cycle_count and announced_cycles is stored in a 32-bit variable before
74 * Each time cycle_count is updated with the value from overflow_cyc,
84 * case because the Cortex-m SysTick is not clocked in the low power
92 /* Idle timer value before entering the idle state. */
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Dmchp_xec_rtos_timer.c4 * SPDX-License-Identifier: Apache-2.0
67 * pcrs property at index 0 is register index into array of 32-bit PCR SLP_EN,
77 /* Mask off bits[31:28] of 32-bit count */
86 /* max number of ticks we can load into the timer in one shot */
118 ECIA_XEC_REGS->GIRQ[girq - 8].SRC = BIT(bitpos); in girq_src_clr()
127 ECIA_XEC_REGS->GIRQ[girq - 8].EN_SET = BIT(bitpos); in girq_src_en()
136 ECIA_XEC_REGS->GIRQ[girq - 8].EN_CLR = BIT(bitpos); in girq_src_dis()
141 TIMER_REGS->CTRL = 0U; in timer_restart()
142 TIMER_REGS->CTRL = MCHP_RTMR_CTRL_BLK_EN; in timer_restart()
143 TIMER_REGS->PRLD = countdown; in timer_restart()
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Dmchp_mec5_ktimer.c3 * SPDX-License-Identifier: Apache-2.0
58 /* Mask off bits[31:28] of 32-bit count */
67 /* max number of ticks we can load into the timer in one shot */
103 * was on. We detect the timer is in the load state by checking the read-only
106 * process of moving the preload register value into the count register.
130 * RTMR counter register is read-only and is loaded from the preload
131 * register by a 0->1 transition of the control register start bit.
132 * Writing a new value to preload only takes effect once the count
147 * global objects safe from pre-emption? in sys_clock_set_timeout()
157 full_ticks = MAX_TICKS - 1; in sys_clock_set_timeout()
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/Zephyr-latest/tests/subsys/settings/fcb/src/
Dsettings_test_save_2_fcb.c5 * SPDX-License-Identifier: Apache-2.0
26 zassert_true(rc == 0 || rc == -EEXIST, "settings_register fail"); in ZTEST()
28 zassert_true(rc == 0 || rc == -EEXIST, "settings_register fail"); in ZTEST()
53 printk("load val8 and val_string\n"); in ZTEST()
58 zassert_true(val8 == 42U, "bad value read"); in ZTEST()
59 zassert_str_equal(val_string[0], test_ref_value[0], "bad value read"); in ZTEST()
63 * Now add the number of settings to max. Keep adjusting the test_data, in ZTEST()
82 "bad value read"); in ZTEST()
83 zassert_true(val8 == 42U, "bad value read"); in ZTEST()
/Zephyr-latest/soc/nuvoton/npcm/common/esiost/
Desiost.py5 # SPDX-License-Identifier: Apache-2.0
8 # NPCM eSIO series how to load the firmware from flash to code ram
10 # -i in_file.bin -o out_file.bin
11 # [-chip <name>] [-v]
61 INVALID_INPUT = -1
103 :returns: output file path object, or -1 if fails
110 exit_with_failure("Define input file, using -i flag")
157 """writes the anchor value to the output file
164 message = f'ANCHOR max support 8 bytes'
172 print(f'- HDR - FW Header ANCHOR - Offset '
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/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,mcux-rt-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
15 drive-strength = "r0-6";
16 slew-rate = "slow";
17 nxp,speed = "100-mhz";
21 Both pins will be configured with a weak latch, drive strength of "r0-6",
26 input-schmitt-enable: HYS=1
27 drive-open-drain: ODE=1
28 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
29 bias-pull-down: PUE=1, PUS=<bias-pull-down-value>
30 bias-pull-up: PUE=1, PUS=<bias-pull-up-value>
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/Zephyr-latest/drivers/pwm/
Dpwm_cc13xx_cc26xx_timer.c4 * SPDX-License-Identifier: Apache-2.0
29 * prescaler. Count is set to (2^24 - 2) to allow for a glitch free 100% duty
30 * cycle at max. period count.
46 static void write_value(const struct pwm_cc13xx_cc26xx_config *config, uint32_t value, in write_value() argument
49 /* Upper byte represents the prescaler value. */ in write_value()
50 uint8_t prescaleValue = 0xff & (value >> 16); in write_value()
52 HWREG(config->gpt_base + prescale_register) = prescaleValue; in write_value()
54 /* The remaining bytes represent the load / match value. */ in write_value()
55 HWREG(config->gpt_base + value_register) = value & 0xffff; in write_value()
64 TimerDisable(config->gpt_base, TIMER_B); in set_period_and_pulse()
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/Zephyr-latest/soc/nuvoton/npcx/common/ecst/
Decst.py5 # SPDX-License-Identifier: Apache-2.0
8 # NPCX EC series how to load the firmware from flash to code ram
10 # -i in_file.bin -o out_file.bin
11 # [-chip <name>] [-v|-vv]
12 # [-nohcrc] [-nofcrc] [-ph <offset>]
13 # [-flashsize <1|2|4|8|16>]
14 # [-spimaxclk <20|25|33|40|50>]
15 # [-spireadmode <normal|fast|dual|quad>]
112 INVALID_INPUT = -1
115 BYTES_TO_PAD = HDR_FW_HEADER_SIG_OFFSET - RESERVED_BYTES_OFFSET
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/Zephyr-latest/scripts/kconfig/
Dmenuconfig.py3 # Copyright (c) 2018-2019, Nordic Semiconductor ASA and Ulf Magnusson
4 # SPDX-License-Identifier: ISC
10 A curses-based Python 2/3 menuconfig implementation. The interface should feel
19 Ctrl-D/U: Page Down/Page Up
27 character in it in the current menu isn't supported. A jump-to feature for
33 F: Toggle show-help mode, which shows the help text of the currently selected
37 C: Toggle show-name mode, which shows the symbol name before each symbol menu
40 A: Toggle show-all mode, which shows all items, including currently invisible
50 bit inflexible in that it will still load and save .config, etc.
52 When run in standalone mode, the top-level Kconfig file to load can be passed
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/Zephyr-latest/arch/x86/core/intel64/
Duserspace.S4 * SPDX-License-Identifier: Apache-2.0
53 movq $0, -8(%rsp) /* Delete stashed RAX data */
75 * eventually gets put on the stack before we re-enable interrupts
76 * as this is a per-cpu and not per-thread area.
86 /* Load kernel's page table */
93 movq $0, -8(%rsp) /* Delete stashed RAX data */
109 sti /* re-enable interrupts */
111 /* call_id is in RAX. bounds-check it, must be less than
124 * RBX, RBP, R12-R15, plus floating point / SIMD registers.
126 * We save caller-saved registers so we can restore to original values
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/Zephyr-latest/include/zephyr/settings/
Dsettings.h5 * SPDX-License-Identifier: Apache-2.0
37 #define SETTINGS_MAX_DIR_DEPTH 8 /* max depth of settings tree */
46 #define SETTINGS_EXTRA_LEN ((SETTINGS_MAX_DIR_DEPTH - 1) + 2)
58 * @return positive: Number of bytes read, 0: key-value pair is deleted.
59 * On error returns -ERRNO code.
74 /**< Priority of commit, lower value is higher priority */
80 * - key[in] the name with skipped part that was used as name in
82 * - val[out] buffer to receive value.
83 * - val_len_max[in] size of that buffer.
90 /**< Set value handler of settings items identified by keyword names.
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/Zephyr-latest/dts/arm/nxp/
Dnxp_s32z27x_rtu0_r52.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
12 /delete-node/ cpu@4;
13 /delete-node/ cpu@5;
14 /delete-node/ cpu@6;
15 /delete-node/ cpu@7;
19 /* Accessing code RAM over AXIF - a read-only flash memory bus */
21 compatible = "mmio-sram";
26 compatible = "nxp,s32-sys-timer";
34 compatible = "nxp,s32-sys-timer";
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Dnxp_s32z27x_rtu1_r52.dtsi2 * Copyright 2022-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
12 /delete-node/ cpu@0;
13 /delete-node/ cpu@1;
14 /delete-node/ cpu@2;
15 /delete-node/ cpu@3;
19 /* Accessing code RAM over AXIF - a read-only flash memory bus */
21 compatible = "mmio-sram";
26 compatible = "nxp,s32-sys-timer";
34 compatible = "nxp,s32-sys-timer";
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/Zephyr-latest/drivers/counter/
Dcounter_nxp_mrt.c4 * SPDX-License-Identifier: Apache-2.0
11 * initialization, interrupt handling, and any other module-wide tasks. The current implementation
34 (*(struct nxp_mrt_channel_data *const *const)dev->data)
36 /* Device config->data is an array of data pointers ordered by channel number,
37 * dev->data is a pointer to one of these pointers in that array,
38 * so the value of the dev->data - dev->config->data is the channel index
41 (((struct nxp_mrt_channel_data *const *)dev->data) - \
42 ((const struct nxp_mrt_config *)dev->config)->data)
65 const struct nxp_mrt_config *config = dev->config; in nxp_mrt_stop()
66 MRT_Type *base = config->base; in nxp_mrt_stop()
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/Zephyr-latest/subsys/bluetooth/host/
DKconfig3 # Copyright (c) 2016-2020 Nordic Semiconductor ASA
4 # Copyright (c) 2015-2016 Intel Corporation
5 # SPDX-License-Identifier: Apache-2.0
8 bool "Dedicated workqueue for long-running tasks."
11 Adds an API for a workqueue dedicated to long-running tasks.
23 int "Long workqueue priority. Should be pre-emptible."
44 # NOTE: This value is derived from other symbols and should only be
58 # the worst-case stack size if an out-of-tree controller is used.
70 # Hidden option for Co-Operative Tx thread priority
97 bool "Process low priority HCI packets in the bluetooth-specific work queue"
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/Zephyr-latest/arch/xtensa/core/
Dgdbstub.c4 * SPDX-License-Identifier: Apache-2.0
118 * which is 0-255. in read_sreg()
120 regno = reg->regno & 0xFF; in read_sreg()
125 * hard-coded at compile time. in read_sreg()
323 reg->val = val; in read_sreg()
324 reg->seqno = ctx->seqno; in read_sreg()
347 /* load/store error */ in get_gdb_exception_reason()
355 /* load/store alignment */ in get_gdb_exception_reason()
363 /* load/store PIF data error */ in get_gdb_exception_reason()
371 /* load/store PIF addr error */ in get_gdb_exception_reason()
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/Zephyr-latest/soc/intel/intel_adsp/tools/
Dremote-fw-service.py3 # SPDX-License-Identifier: Apache-2.0
20 # pylint: disable=duplicate-code
28 # Define the command and the max size
33 # Define the return value in handle function
42 log = logging.getLogger("remote-fw")
65 data = self.request.recv(min(BUF_SIZE, fsize - len(total)))
81 md5_tx = md5_tx_b.decode('utf-8')
93 recv_file = recv_file.decode('utf-8')
105 action = cmd.decode("utf-8")
106 log.debug(f'load {action}')
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/Zephyr-latest/dts/riscv/
Driscv32-litex-vexriscv.dtsi2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "litex,vexriscv", "litex-dev";
21 #address-cells = <1>;
22 #size-cells = <0>;
24 clock-frequency = <100000000>;
25 compatible = "litex,vexriscv-standard", "riscv";
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