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/Zephyr-latest/drivers/timer/
DKconfig.cortex_m_systick1 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
6 DT_CHOSEN_IDLE_TIMER := zephyr,cortex-m-idle-timer
9 bool "Cortex-M SYSTICK timer"
20 This module implements a kernel device driver for the Cortex-M processor
27 This option should be selected by SysTick-based drivers so that the
31 bool "Cortex-M SYSTICK timer with sys_clock_cycle_get_64() support"
36 This driver, due to its limited 24-bits hardware counter, is already
37 tracking a separate cycle count in software. This option make that
38 count a 64-bits value to support sys_clock_cycle_get_64().
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Darcv2_timer0.c2 * Copyright (c) 2014-2015 Wind River Systems, Inc.
5 * SPDX-License-Identifier: Apache-2.0
37 #define _ARC_V2_TMR_CTRL_NH 0x2 /* count only while not halted */
51 #define MAX_TICKS ((COUNTER_MAX / CYC_PER_TICK) - 1)
104 * @brief Get contents of Timer0 count register
106 * @return Current Timer0 count
114 * @brief Set Timer0 count register to the specified value
152 static ALWAYS_INLINE void timer0_limit_register_set(uint32_t count) in timer0_limit_register_set() argument
154 z_arc_v2_aux_reg_write(_ARC_V2_TMR0_LIMIT, count); in timer0_limit_register_set()
168 * - reprogramming of LIMIT must be clearing the COUNT
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Dcortex_m_systick.c4 * SPDX-License-Identifier: Apache-2.0
20 #define MAX_TICKS ((k_ticks_t)(COUNTER_MAX / CYC_PER_TICK) - 1)
25 * reliably" -- it becomes the minimum value of the LOAD register, and
61 * Additions/subtractions/comparisons of 64-bits values on 32-bits systems
63 * cycle_count and announced_cycles is stored in a 32-bit variable before
81 * entering idle state.
83 * It is used for chips that has to use a separate idle timer in such
84 * case because the Cortex-m SysTick is not clocked in the low power
89 /* Cycle counter before entering the idle state. */
92 /* Idle timer value before entering the idle state. */
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DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
6 # SPDX-License-Identifier: Apache-2.0
16 available to provide values from a 64-bit cycle counter.
25 bool "Timer allowed to skew uptime clock during idle"
28 correct system uptime count when the system enters idle.
63 cycle count accessor. This is needed for instrumenting spin lock
Dintel_adsp_timer.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <cavs-idc.h>
39 #define MAX_TICKS ((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
77 static uint64_t count(void) in count() function
79 /* The count register is 64 bits, but we're a 32 bit CPU that in count()
111 curr = count(); in compare_isr()
112 dticks = (curr - last_count) / CYC_PER_TICK; in compare_isr()
123 if ((int64_t)(next - curr) < MIN_DELAY) { in compare_isr()
134 void sys_clock_set_timeout(int32_t ticks, bool idle) in sys_clock_set_timeout() argument
136 ARG_UNUSED(idle); in sys_clock_set_timeout()
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Dcc13xx_cc26xx_rtc_timer.c4 * SPDX-License-Identifier: Apache-2.0
10 * TI SimpleLink CC13X2/CC26X2 RTC-based system timer
13 * RTC counts continually in 64-bit mode and timeouts are
58 /* RTC count of the last announce call, rounded down to tick boundary. */
75 /* get the current RTC count corresponding to compare window */ in setThreshold()
79 /* assume next never be more than half the maximum 32 bit count value */ in setThreshold()
80 if ((next - now) > (uint32_t)0x80000000) { in setThreshold()
83 } else if ((now + COMPARE_MARGIN - next) < (uint32_t)0x80000000) { in setThreshold()
111 ticks = (currCount - rtc_last) / RTC_COUNTS_PER_TICK; in rtc_isr()
120 /* calculate new 64-bit RTC count for next interrupt */ in rtc_isr()
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Dsam0_rtc_timer.c4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Atmel SAM0 series RTC-based system timer
14 * In tickless mode, RTC counts continually in 32-bit mode and timeouts are
42 #define MAX_TICKS (UINT32_MAX / CYCLES_PER_TICK - 2)
73 /* Tick/cycle count of the last announce call. */
78 /* Current tick count. */
96 while (RTC0->STATUS.reg & RTC_STATUS_SYNCBUSY) { in rtc_sync()
99 while (RTC0->SYNCBUSY.reg) { in rtc_sync()
105 * Reads RTC COUNT register. First a read request must be written to READREQ,
106 * then - when bus synchronization completes - the COUNT register is read and
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Dmchp_mec5_ktimer.c3 * SPDX-License-Identifier: Apache-2.0
58 /* Mask off bits[31:28] of 32-bit count */
63 /* Adjust cycle count programmed into timer for HW restart latency */
98 * has been reloaded within 1 32KHz clock of reading its count register.
103 * was on. We detect the timer is in the load state by checking the read-only
104 * count register and the START bit in the control register. If count register
106 * process of moving the preload register value into the count register.
130 * RTMR counter register is read-only and is loaded from the preload
131 * register by a 0->1 transition of the control register start bit.
132 * Writing a new value to preload only takes effect once the count
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Dambiq_stimer.c4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Ambiq Apollo STIMER-based sys_clock driver
22 /* ambiq-sdk includes */
28 #define MAX_TICKS ((k_ticks_t)(COUNTER_MAX / CYC_PER_TICK) - 1)
63 /* Read current cycle count. */ in update_tick_counter()
66 /* If current cycle count is smaller than the last time stamp, a counter overflow happened. in update_tick_counter()
73 uint32_t elapsed_cycle = (now_64 - g_last_time_stamp); in update_tick_counter()
99 /*Calculate the elapsed ticks based on the current cycle count*/ in stimer_isr()
107 /* Read current cycle count. */ in stimer_isr()
110 /* If current cycle count is smaller than the last time stamp, a counter in stimer_isr()
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Dmchp_xec_rtos_timer.c4 * SPDX-License-Identifier: Apache-2.0
67 * pcrs property at index 0 is register index into array of 32-bit PCR SLP_EN,
77 /* Mask off bits[31:28] of 32-bit count */
82 /* Adjust cycle count programmed into timer for HW restart latency */
118 ECIA_XEC_REGS->GIRQ[girq - 8].SRC = BIT(bitpos); in girq_src_clr()
127 ECIA_XEC_REGS->GIRQ[girq - 8].EN_SET = BIT(bitpos); in girq_src_en()
136 ECIA_XEC_REGS->GIRQ[girq - 8].EN_CLR = BIT(bitpos); in girq_src_dis()
141 TIMER_REGS->CTRL = 0U; in timer_restart()
142 TIMER_REGS->CTRL = MCHP_RTMR_CTRL_BLK_EN; in timer_restart()
143 TIMER_REGS->PRLD = countdown; in timer_restart()
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/Zephyr-latest/dts/bindings/adc/
Dadi,max32-adc-10b.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
4 description: ADI MAX32 ADC 10-Bits
6 compatible: "adi,max32-adc-10b"
9 - name: adi,max32-adc.yaml
10 property-blocklist:
11 - clock-source
12 - clock-divider
13 - track-count
14 - idle-count
Dadi,max32-adc.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,max32-adc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
20 pinctrl-0:
23 pinctrl-names:
26 channel-count:
31 vref-mv:
41 clock-source:
48 - 0: "ADI_MAX32_PRPH_CLK_SRC_PCLK" Peripheral clock
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/Zephyr-latest/subsys/usb/device/class/hid/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
22 default-count = 1
26 module-str = usb hid
47 int "Number of HID idle reports in the instance"
52 support USB HID idle rate and Set/Get Idle Requests.
58 idle rate must be supported.
/Zephyr-latest/dts/bindings/input/
Dgpio-qdec.yaml2 # SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/input/input-event-codes.h>
18 compatible = "gpio-qdec";
21 steps-per-period = <4>;
23 sample-time-us = <2000>;
24 idle-timeout-ms = <200>;
27 compatible: "gpio-qdec"
33 type: phandle-array
38 led-gpios:
39 type: phandle-array
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/Zephyr-latest/include/zephyr/drivers/timer/
Dsystem_timer.h5 * SPDX-License-Identifier: Apache-2.0
53 * for ticks if it wants to preserve the uptime tick count but doesn't
59 * ticks and real-world time must be correct.
70 * @param idle Hint to the driver that the system is about to enter
71 * the idle state immediately after setting the timeout
73 void sys_clock_set_timeout(int32_t ticks, bool idle);
76 * @brief Timer idle exit notification
78 * This notifies the timer driver that the system is exiting the idle
128 * user-facing API is owned by the architecture, not the driver. The
137 * @return The current cycle time. This should count up monotonically
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/Zephyr-latest/arch/arm/core/cortex_a_r/
Disr_wrapper.S2 * Copyright (c) 2013-2014 Wind River Systems, Inc.
5 * SPDX-License-Identifier: Apache-2.0
10 * @brief ARM Cortex-A and Cortex-R wrapper for ISRs with parameter
79 * Save away r0-r3, r12 and lr_irq for the previous context to the
87 push {r0-r3, r12, lr}
98 str r0, [sp, #___fpu_t_SIZEOF - 4]
102 str r0, [sp, #___fpu_t_SIZEOF - 8]
138 /* Align stack at double-word boundary */
143 /* Increment interrupt nesting count */
155 * All interrupts are disabled when handling idle wakeup. For tickless
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/Zephyr-latest/subsys/logging/
Dlog_cache.h4 * SPDX-License-Identifier: Apache-2.0
32 sys_slist_t idle; member
63 * not found in the cache. Releasing puts entry in idle list.
70 /** @brief Get hit count.
78 return cache->hit; in log_cache_get_hit()
81 /** @brief Get miss count.
89 return cache->miss; in log_cache_get_miss()
/Zephyr-latest/include/zephyr/kernel/
Dthread.h4 * SPDX-License-Identifier: Apache-2.0
78 * scheduler lock count and thread priority
87 * By putting them end-to-end, this means that a thread is
88 * non-preemptible if the bundled value is greater than or equal to
111 /* True for the per-CPU idle threads */
117 /* Recursive count of irq_lock() calls */
155 /* Stack start - Represents the start address of the thread-writable
163 * for local thread data storage, as well as any area left-out due to
170 * used for TLS or random stack base offsets. (start + size - delta)
210 * For CPU stats, execution_cycles is the sum of non-idle + idle cycles.
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/Zephyr-latest/tests/bsim/bluetooth/ll/throughput/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
19 #define COUNT 5000 /* Arbitrary GATT Write Cmd iterations used */ macro
28 * Full duplex Tx-Rx duration = 2428 us
31 * Max. radio idle time per 1 second = (1064 + 340) * 20 = 28080 us
32 * Packets per 1 second = (1000000 - 28080) / 2428 = 400.297
38 extern uint32_t central_gatt_write(uint32_t count);
39 extern uint32_t peripheral_gatt_write(uint32_t count);
59 write_rate = central_gatt_write(COUNT); in test_central_main()
78 write_rate = peripheral_gatt_write(COUNT); in test_peripheral_main()
/Zephyr-latest/doc/connectivity/bluetooth/shell/audio/
Dbap.rst9 - Capabilities and Endpoint discovery
10 - Audio Stream Endpoint procedures
15 .. code-block:: console
17 bap --help
58 [lang <ISO 639-3 lang>]
74 .. csv-table:: State Machine Transitions
80 "config","discover","idle/codec-configured/qos-configured","codec-configured"
81 "qos","config","codec-configured/qos-configured","qos-configured"
82 "enable","qos","qos-configured","enabling"
83 "connect","qos/enable","qos-configured/enabling","qos-configured/enabling"
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/Zephyr-latest/boards/renesas/da1469x_dk_pro/dts/
Dda1469x_dk_pro_psram.overlay4 * SPDX-License-Identifier: Apache-2.0
9 sram-ext = &memc;
17 /* QSPIC settings for the APS6404L-3SQR QSPI PSRAM memory in QPI mode. */
20 is-ram;
21 dev-size = <DT_SIZE_M(64)>;
22 dev-type = <0x5D>;
23 dev-id = <0x0D>;
24 dev-density = <0xE040>;
25 reset-delay-us = <50>;
26 read-cs-idle-min-ns = <18>;
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/Zephyr-latest/include/zephyr/drivers/
Dswdp.h4 * SPDX-License-Identifier: Apache-2.0
46 * @brief Write count bits to SWDIO from data LSB first
49 * @param count Number of bits to write
54 uint32_t count,
58 * @brief Read count bits from SWDIO into data LSB first
61 * @param count Number of bits to read
66 uint32_t count,
75 * @param idle_cycles Idle cycles between request and response
139 * @brief Disable interface, set pins to High-Z mode
/Zephyr-latest/tests/lib/p4workq/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
39 /* Choose a random preemptible priority higher than the idle in stress_sub()
43 item->item.priority = sys_rand32_get() % (K_LOWEST_THREAD_PRIO - 1); in stress_sub()
44 item->item.deadline = sys_rand32_get() % k_ms_to_cyc_ceil32(2); in stress_sub()
45 item->item.handler = stress_handler; in stress_sub()
46 item->running = false; in stress_sub()
47 item->active = true; in stress_sub()
49 k_p4wq_submit(&wq, &item->item); in stress_sub()
57 titem->running = true; in stress_handler()
61 zassert_true(curr_pri == item->priority, in stress_handler()
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/Zephyr-latest/tests/kernel/context/src/
Dmain.c2 * Copyright (c) 2012-2015 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
42 #define UNKNOWN_COMMAND -1
43 #define INVALID_BEHAVIOUR -2
54 * The Cortex-M use the SYSTICK exception for the system timer, which is
75 /* Cortex-M1 and Nios II do have a power saving instruction, so k_cpu_idle()
138 if (arch_current_thread()->base.prio < 0) { in isr_handler()
231 /* Set up a time to trigger events to exit idle mode */ in _test_kernel_cpu_idle()
251 dt = k_uptime_ticks() - t0; in _test_kernel_cpu_idle()
252 zassert_true(abs((int32_t) (dt - dur)) <= slop, in _test_kernel_cpu_idle()
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/Zephyr-latest/dts/arm/adi/max32/
Dmax32662.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/dma/max32662_dma.h>
19 /delete-node/ &clk_iso;
21 /delete-node/ &gpio1;
23 /delete-node/ &uart2;
25 /delete-node/ &timer3;
28 compatible = "adi,max32-adc-sar", "adi,max32-adc";
29 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
30 clock-divider = <16>;
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