1/*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <adi/max32/max32xxx.dtsi>
9#include <zephyr/dt-bindings/dma/max32662_dma.h>
10
11&flash0 {
12	reg = <0x10000000 DT_SIZE_K(256)>;
13};
14
15&sram0 {
16	reg = <0x20000000 DT_SIZE_K(16)>;
17};
18
19/delete-node/ &clk_iso;
20
21/delete-node/ &gpio1;
22
23/delete-node/ &uart2;
24
25/delete-node/ &timer3;
26
27&adc {
28	compatible = "adi,max32-adc-sar", "adi,max32-adc";
29	clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
30	clock-divider = <16>;
31	channel-count = <19>;
32	track-count = <4>;
33	idle-count = <0>;
34	vref-mv = <1250>;
35	resolution = <12>;
36};
37
38/* MAX32662 extra peripherals. */
39/ {
40	soc {
41		sram1: memory@20004000 {
42			compatible = "mmio-sram";
43			reg = <0x20004000 DT_SIZE_K(16)>;
44		};
45
46		sram2: memory@20008000 {
47			compatible = "mmio-sram";
48			reg = <0x20008000 DT_SIZE_K(16)>;
49		};
50
51		sram3: memory@2000c000 {
52			compatible = "mmio-sram";
53			reg = <0x2000c000 DT_SIZE_K(16)>;
54		};
55
56		sram4: memory@20010000 {
57			compatible = "mmio-sram";
58			reg = <0x20010000 DT_SIZE_K(4)>;
59		};
60
61		sram5: memory@20011000 {
62			compatible = "mmio-sram";
63			reg = <0x20011000 DT_SIZE_K(4)>;
64		};
65
66		sram6: memory@20012000 {
67			compatible = "mmio-sram";
68			reg = <0x20012000 DT_SIZE_K(4)>;
69		};
70
71		sram7: memory@20013000 {
72			compatible = "mmio-sram";
73			reg = <0x20013000 DT_SIZE_K(4)>;
74		};
75
76		dma0: dma@40028000 {
77			compatible = "adi,max32-dma";
78			reg = <0x40028000 0x1000>;
79			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
80			interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
81			dma-channels = <4>;
82			status = "disabled";
83			#dma-cells = <2>;
84		};
85
86		spi0: spi@40046000 {
87			compatible = "adi,max32-spi";
88			reg = <0x40046000 0x1000>;
89			#address-cells = <1>;
90			#size-cells = <0>;
91			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
92			interrupts = <16 0>;
93			status = "disabled";
94		};
95
96		spi1: spi@40047000 {
97			compatible = "adi,max32-spi";
98			reg = <0x40047000 0x1000>;
99			#address-cells = <1>;
100			#size-cells = <0>;
101			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
102			interrupts = <17 0>;
103			status = "disabled";
104		};
105
106		lptimer0: timer@40113000 {
107			compatible = "adi,max32-timer";
108			reg = <0x40113000 0x2000>;
109			interrupts = <8 0>;
110			status = "disabled";
111			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
112			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
113			prescaler = <1>;
114			counter {
115				compatible = "adi,max32-counter";
116				status = "disabled";
117			};
118		};
119	};
120};
121