1 /*
2 * Copyright (c) 2023 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ambiq_stimer
8
9 /**
10 * @file
11 * @brief Ambiq Apollo STIMER-based sys_clock driver
12 *
13 */
14
15 #include <zephyr/init.h>
16 #include <zephyr/kernel.h>
17 #include <zephyr/drivers/timer/system_timer.h>
18 #include <zephyr/sys_clock.h>
19 #include <zephyr/irq.h>
20 #include <zephyr/spinlock.h>
21
22 /* ambiq-sdk includes */
23 #include <am_mcu_apollo.h>
24
25 #define COUNTER_MAX UINT32_MAX
26
27 #define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
28 #define MAX_TICKS ((k_ticks_t)(COUNTER_MAX / CYC_PER_TICK) - 1)
29 #define MAX_CYCLES (MAX_TICKS * CYC_PER_TICK)
30 #if defined(CONFIG_SOC_SERIES_APOLLO3X)
31 #define MIN_DELAY 1
32 #elif defined(CONFIG_SOC_SERIES_APOLLO4X)
33 #define MIN_DELAY 4
34 #endif
35
36 #define COMPARE_INTERRUPT (AM_HAL_STIMER_INT_COMPAREA | AM_HAL_STIMER_INT_COMPAREB)
37
38 #define COMPAREA_IRQ (DT_INST_IRQN(0))
39 #define COMPAREB_IRQ (COMPAREA_IRQ + 1)
40
41 #define TIMER_CLKSRC (DT_INST_PROP(0, clk_source))
42
43 #if defined(CONFIG_TEST)
44 const int32_t z_sys_timer_irq_for_test = COMPAREA_IRQ;
45 #endif
46
47 /* Elapsed ticks since the previous kernel tick was announced, It will get accumulated every time
48 * stimer_isr is triggered, or sys_clock_set_timeout/sys_clock_elapsed API is called.
49 * It will be cleared after sys_clock_announce is called,.
50 */
51 static uint32_t g_tick_elapsed;
52
53 /* Value of STIMER counter when the previous timer API is called, this value is
54 * aligned to tick boundary. It is updated along with the g_tick_elapsed value.
55 */
56 static uint32_t g_last_time_stamp;
57
58 /* Spinlock to sync between Compare ISR and update of Compare register */
59 static struct k_spinlock g_lock;
60
update_tick_counter(void)61 static void update_tick_counter(void)
62 {
63 /* Read current cycle count. */
64 uint32_t now = am_hal_stimer_counter_get();
65
66 /* If current cycle count is smaller than the last time stamp, a counter overflow happened.
67 * We need to extend the current counter value to 64 bits and add it with 0xFFFFFFFF
68 * to get the correct elapsed cycles.
69 */
70 uint64_t now_64 = (g_last_time_stamp <= now) ? (uint64_t)now : (uint64_t)now + COUNTER_MAX;
71
72 /* Get elapsed cycles */
73 uint32_t elapsed_cycle = (now_64 - g_last_time_stamp);
74
75 /* Get elapsed ticks. */
76 uint32_t dticks = elapsed_cycle / CYC_PER_TICK;
77
78 g_last_time_stamp += dticks * CYC_PER_TICK;
79 g_tick_elapsed += dticks;
80 }
81
ambiq_stimer_delta_set(uint32_t ui32Delta)82 static void ambiq_stimer_delta_set(uint32_t ui32Delta)
83 {
84 am_hal_stimer_compare_delta_set(0, ui32Delta);
85 am_hal_stimer_compare_delta_set(1, ui32Delta + 1);
86 }
87
stimer_isr(const void * arg)88 static void stimer_isr(const void *arg)
89 {
90 ARG_UNUSED(arg);
91
92 uint32_t irq_status = am_hal_stimer_int_status_get(false);
93
94 if (irq_status & COMPARE_INTERRUPT) {
95 am_hal_stimer_int_clear(COMPARE_INTERRUPT);
96
97 k_spinlock_key_t key = k_spin_lock(&g_lock);
98
99 /*Calculate the elapsed ticks based on the current cycle count*/
100 update_tick_counter();
101
102 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
103
104 /* Get the counter value to trigger the next tick interrupt. */
105 uint64_t next = (uint64_t)g_last_time_stamp + CYC_PER_TICK;
106
107 /* Read current cycle count. */
108 uint32_t now = am_hal_stimer_counter_get();
109
110 /* If current cycle count is smaller than the last time stamp, a counter
111 * overflow happened. We need to extend the current counter value to 64 bits
112 * and add 0xFFFFFFFF to get the correct elapsed cycles.
113 */
114 uint64_t now_64 = (g_last_time_stamp <= now) ? (uint64_t)now
115 : (uint64_t)now + COUNTER_MAX;
116
117 uint32_t delta = (now_64 + MIN_DELAY < next) ? (next - now_64) : MIN_DELAY;
118
119 /* Set delta. */
120 ambiq_stimer_delta_set(delta);
121 }
122
123 k_spin_unlock(&g_lock, key);
124
125 sys_clock_announce(g_tick_elapsed);
126 g_tick_elapsed = 0;
127 }
128 }
129
sys_clock_set_timeout(int32_t ticks,bool idle)130 void sys_clock_set_timeout(int32_t ticks, bool idle)
131 {
132 ARG_UNUSED(idle);
133
134 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
135 return;
136 }
137
138 /* Adjust the ticks to the range of [1, MAX_TICKS]. */
139 ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
140 ticks = CLAMP(ticks, 1, (int32_t)MAX_TICKS);
141
142 k_spinlock_key_t key = k_spin_lock(&g_lock);
143
144 /* Update the internal tick counter*/
145 update_tick_counter();
146
147 /* Get current hardware counter value.*/
148 uint32_t now = am_hal_stimer_counter_get();
149
150 /* last: the last recorded counter value.
151 * now_64: current counter value. Extended to uint64_t to easy the handing of hardware
152 * counter overflow.
153 * next: counter values where to trigger the scheduled timeout.
154 * last < now_64 < next
155 */
156 uint64_t last = (uint64_t)g_last_time_stamp;
157 uint64_t now_64 = (g_last_time_stamp <= now) ? (uint64_t)now : (uint64_t)now + COUNTER_MAX;
158 uint64_t next = now_64 + ticks * CYC_PER_TICK;
159
160 uint32_t gap = next - last;
161 uint32_t gap_aligned = (gap / CYC_PER_TICK) * CYC_PER_TICK;
162 uint64_t next_aligned = last + gap_aligned;
163
164 uint32_t delta = next_aligned - now_64;
165
166 if (delta <= MIN_DELAY) {
167 /*If the delta value is smaller than MIN_DELAY, trigger a interrupt immediately*/
168 am_hal_stimer_int_set(COMPARE_INTERRUPT);
169 } else {
170 ambiq_stimer_delta_set(delta);
171 }
172
173 k_spin_unlock(&g_lock, key);
174 }
175
sys_clock_elapsed(void)176 uint32_t sys_clock_elapsed(void)
177 {
178 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
179 return 0;
180 }
181
182 k_spinlock_key_t key = k_spin_lock(&g_lock);
183 update_tick_counter();
184 k_spin_unlock(&g_lock, key);
185
186 return g_tick_elapsed;
187 }
188
sys_clock_cycle_get_32(void)189 uint32_t sys_clock_cycle_get_32(void)
190 {
191 return am_hal_stimer_counter_get();
192 }
193
stimer_init(void)194 static int stimer_init(void)
195 {
196 uint32_t oldCfg;
197
198 oldCfg = am_hal_stimer_config(TIMER_CLKSRC | AM_HAL_STIMER_CFG_FREEZE);
199
200 #if defined(CONFIG_SOC_SERIES_APOLLO3X)
201 am_hal_stimer_config((oldCfg & ~(AM_HAL_STIMER_CFG_FREEZE | CTIMER_STCFG_CLKSEL_Msk)) |
202 TIMER_CLKSRC | AM_HAL_STIMER_CFG_COMPARE_A_ENABLE |
203 AM_HAL_STIMER_CFG_COMPARE_B_ENABLE);
204 #else
205 am_hal_stimer_config((oldCfg & ~(AM_HAL_STIMER_CFG_FREEZE | STIMER_STCFG_CLKSEL_Msk)) |
206 TIMER_CLKSRC | AM_HAL_STIMER_CFG_COMPARE_A_ENABLE |
207 AM_HAL_STIMER_CFG_COMPARE_B_ENABLE);
208 #endif
209 g_last_time_stamp = am_hal_stimer_counter_get();
210
211 /* A Possible clock glitch could rarely cause the Stimer interrupt to be lost.
212 * Set up a backup comparator to handle this case
213 */
214 NVIC_ClearPendingIRQ(COMPAREA_IRQ);
215 NVIC_ClearPendingIRQ(COMPAREB_IRQ);
216 IRQ_CONNECT(COMPAREA_IRQ, 0, stimer_isr, 0, 0);
217 IRQ_CONNECT(COMPAREB_IRQ, 0, stimer_isr, 0, 0);
218 irq_enable(COMPAREA_IRQ);
219 irq_enable(COMPAREB_IRQ);
220
221 am_hal_stimer_int_enable(COMPARE_INTERRUPT);
222 /* Start timer with period CYC_PER_TICK if tickless is not enabled */
223 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
224 ambiq_stimer_delta_set(CYC_PER_TICK);
225 }
226 return 0;
227 }
228
229 SYS_INIT(stimer_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
230
