Home
last modified time | relevance | path

Searched +full:half +full:- +full:duplex (Results 1 – 25 of 96) sorted by relevance

1234

/Zephyr-latest/dts/bindings/ethernet/
Dethernet-phy.yaml1 # Copyright (c) 2021 IP-Logix Inc.
2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "ethernet-phy"
16 no-reset:
19 fixed-link:
23 - "10BASE-T Half-Duplex"
24 - "10BASE-T Full-Duplex"
25 - "100BASE-T Half-Duplex"
26 - "100BASE-T Full-Duplex"
27 - "1000BASE-T Half-Duplex"
[all …]
Dxlnx,gem.yaml3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
27 which it will be adjusted at run-time. Therefore, the value of this
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
42 init-mdio-phy:
45 Activates the management of a PHY associated with the controller in-
46 stance. If this parameter is activated at the board level, the de-
47 fault values of the associated parameters mdio-phy-address, phy-poll-
[all …]
/Zephyr-latest/include/zephyr/net/
Dmii.h5 * SPDX-License-Identifier: Apache-2.0
33 /** Auto-Negotiation Advertisement Register */
35 /** Auto-Negotiation Link Partner Ability Reg */
37 /** Auto-Negotiation Expansion Register */
39 /** Auto-Negotiation Next Page Transmit Register */
41 /** Auto-Negotiation Link Partner Received Next Page Reg */
43 /** 1000BASE-T Control Register */
45 /** 1000BASE-T Status Register */
61 /** Auto-Negotiation enable */
67 /** restart auto-negotiation */
[all …]
Dphy.h8 * Copyright (c) 2021 IP-Logix Inc.
11 * SPDX-License-Identifier: Apache-2.0
33 /** 10Base-T Half-Duplex */
35 /** 10Base-T Full-Duplex */
37 /** 100Base-T Half-Duplex */
39 /** 100Base-T Full-Duplex */
41 /** 1000Base-T Half-Duplex */
43 /** 1000Base-T Full-Duplex */
45 /** 2.5GBase-T Full-Duplex */
47 /** 5GBase-T Full-Duplex */
[all …]
/Zephyr-latest/dts/bindings/wifi/
Dinfineon,airoc-wifi-spi.yaml2 AIROC Wi-Fi Connectivity over SPI.
4 compatible: "infineon,airoc-wifi"
6 include: [spi-device.yaml, "infineon,airoc-wifi.yaml"]
9 wifi-host-wake-gpios:
12 bus-select-gpios:
16 wifi-reg-on-gpios goes high to select SPI bus mode.
17 type: phandle-array
19 spi-half-duplex:
21 Use half-duplex communication; if not present, full-
22 duplex operation is assumed.
[all …]
/Zephyr-latest/dts/bindings/mipi-dbi/
Dmipi-dbi-spi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [mipi-dbi-device.yaml]
9 duplex:
13 SPI Duplex mode, full or half. By default it's always full duplex thus 0
15 Selecting half duplex allows to use SPI MOSI as a bidirectional line,
18 list (see dt-bindings/spi/spi.h)
21 mipi-cpol:
26 mipi-cpha:
31 mipi-hold-cs:
Dzephyr,mipi-dbi-spi.yaml2 # SPDX-License-Identifier: Apache-2.0
5 MIPI-DBI Mode C compatible SPI controller. This driver emulates MIPI DBI
7 compatible: "zephyr,mipi-dbi-spi"
9 include: ["mipi-dbi-controller.yaml", "pinctrl-device.yaml"]
12 spi-dev:
19 dc-gpios:
20 type: phandle-array
25 reset-gpios:
26 type: phandle-array
30 xfr-min-bits:
[all …]
/Zephyr-latest/drivers/ethernet/phy/
Dphy_dm8806_priv.h4 * SPDX-License-Identifier: Apache-2.0
9 /* 10 Mbit/s transfer with half duplex mask. */
11 /* 10 Mbit/s transfer with full duplex mask. */
13 /* 100 Mbit/s transfer with half duplex mask. */
15 /* 100 Mbit/s transfer with full duplex mask. */
17 /* Duplex mode ability offset. */
28 /* 10 Mbit/s transfer speed with half duplex. */
30 /* 10 Mbit/s transfer speed with full duplex. */
32 /* 100 Mbit/s transfer speed with half duplex. */
34 /* 100 Mbit/s transfer speed with full duplex. */
[all …]
/Zephyr-latest/samples/boards/st/uart/single_wire/
DREADME.rst1 .. zephyr:code-sample:: uart-stm32-single-wire
2 :name: Single-wire UART
3 :relevant-api: uart_interface
5 Use single-wire/half-duplex UART functionality of STM32 devices.
10 A simple application demonstrating how to use the single wire / half-duplex UART
23 .. zephyr-app-commands::
24 :zephyr-app: samples/boards/st/uart/single_wire
32 .. code-block:: none
/Zephyr-latest/dts/bindings/spi/
Despressif,esp32-spi.yaml3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
39 dma-clk:
[all …]
Dspi-device.yaml1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
8 on-bus: spi
13 spi-max-frequency:
17 duplex:
21 Duplex mode, full or half. By default it's always full duplex thus 0
24 list (see dt-bindings/spi/spi.h)
28 - 0
29 - 2048
30 frame-format:
[all …]
Dmicrochip,xec-qmspi-ldma.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-qmspi-ldma"
9 include: [spi-controller.yaml, pinctrl-device.yaml]
30 pinctrl-0:
33 pinctrl-names:
39 QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
40 MOSI and MISO or half-duplex on MOSI only. Lines set to 2
42 Defaults to 1 for full duplex driver's support for full-duplex spi.
44 - 1
45 - 2
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/spi/
Dspi.h4 * SPDX-License-Identifier: Apache-2.0
17 * @name SPI duplex mode
20 * Some controllers support half duplex transfer, which results in 3-wire usage.
21 * By default, full duplex will prevail.
/Zephyr-latest/drivers/ethernet/
DKconfig.stm32_hal5 # SPDX-License-Identifier: Apache-2.0
84 PHY's carrier status is re-evaluated.
109 bool "Half duplex mode"
111 Set this if using half duplex when autonegotiation is disabled otherwise
112 duplex mode is full duplex
Dphy_xlnx_gem.c6 * - Marvell Alaska 88E1111 (QEMU simulated PHY)
7 * - Marvell Alaska 88E1510/88E1518/88E1512/88E1514 (Zedboard)
8 * - Texas Instruments TLK105
9 * - Texas Instruments DP83822
12 * SPDX-License-Identifier: Apache-2.0
34 * @return 16-bit data word received from the PHY
44 * MDIO read operation as described in Zynq-7000 TRM, in phy_xlnx_gem_mdio_read()
81 * Wait until gem.net_status[phy_mgmt_idle] == 1 -> current command in phy_xlnx_gem_mdio_read()
99 * Read the data returned by the PHY -> lower 16 bits of the PHY main- in phy_xlnx_gem_mdio_read()
113 * @param value 16-bit data word to be written to the target register
[all …]
Deth_adin2111_priv.h4 * SPDX-License-Identifier: Apache-2.0
175 /* SPI Header for writing control transaction in half duplex mode */
177 /* SPI Header for writing control transaction with MAC TX register (!) in half duplex mode */
179 /* SPI Header for reading control transaction in half duplex mode */
193 /* Max setting to a max RCA of 255 68-bytes ckunks */
/Zephyr-latest/dts/bindings/serial/
Despressif,esp32-uart.yaml3 compatible: "espressif,esp32-uart"
5 include: [uart-controller.yaml, uart-controller-pin-inversion.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 hw-rs485-hd-mode:
20 Enable the hardware RS485 half duplex mode.
21 Overrides hw-flow-control if both are set.
Dnxp,lpuart.yaml5 include: [uart-controller.yaml, uart-controller-pin-inversion.yaml, pinctrl-device.yaml]
18 single-wire:
21 Enable the single wire half-duplex communication.
26 nxp,rs485-mode:
30 of an external RS-485 transceiver. Note hw-flow-control should be
33 nxp,rs485-de-active-low:
Dst,stm32-uart-base.yaml2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
8 - name: uart-controller.yaml
9 property-blocklist:
10 - clock-frequency
11 - name: pinctrl-device.yaml
12 - name: reset-device.yaml
13 - name: uart-controller-pin-inversion.yaml
28 single-wire:
31 Enable the single wire half-duplex communication.
[all …]
/Zephyr-latest/samples/sensor/ds18b20/boards/
Dnucleo_g0b1re.overlay4 * SPDX-License-Identifier: Apache-2.0
12 * b) the UART TX pin only, while the single wire half-duplex mode is enabled.
13 * An external pull-up should be added anyways.
19 drive-open-drain;
20 bias-pull-up;
/Zephyr-latest/dts/bindings/w1/
Dzephyr,w1-serial.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Properties for the serial 1-Wire master driver:
7 # the option for a "single-wire Half-duplex" mode, where the TX and RX lines
9 # needs to be allocated for the 1-Wire communication.
11 description: 1-Wire master over Zephyr uart
13 compatible: "zephyr,w1-serial"
15 include: [uart-device.yaml, w1-master.yaml]
/Zephyr-latest/dts/bindings/mspi/
Dmspi-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
11 clock-frequency:
15 "#address-cells":
18 "#size-cells":
22 op-mode:
25 - "MSPI_CONTROLLER"
26 - "MSPI_PERIPHERAL"
31 duplex:
34 - "MSPI_HALF_DUPLEX"
35 - "MSPI_FULL_DUPLEX"
[all …]
/Zephyr-latest/doc/connectivity/networking/api/
Dethernet.rst28 * Half/full duplex
33 * :ref:`Priority queues <traffic-class-support>`
39 see what is supported by ``net iface`` net-shell command. It will print
/Zephyr-latest/boards/raspberrypi/rpi_pico/
Drpi_pico_rp2040_w.dts2 * Copyright (c) 2023 Dave Rensberger - Beechwoods Software
5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include "rpi_pico-common.dtsi"
24 input-enable;
33 input-enable;
42 compatible = "raspberrypi,pico-spi-pio";
44 #address-cells = <1>;
45 #size-cells = <0>;
46 cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
[all …]
/Zephyr-latest/drivers/serial/
Duart_stm32.h2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
4 * SPDX-License-Identifier: Apache-2.0
36 /* switch to enable single wire / half duplex feature */
61 /* Device defined as wake-up source */

1234