Searched +full:frequency +full:- +full:control (Results 1 – 25 of 407) sorted by relevance
12345678910>>...17
| /Zephyr-latest/dts/bindings/usb/uac2/ |
| D | zephyr,uac2-clock-source.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "zephyr,uac2-clock-source"
9 clock-type:
14 clock or an internal clock with either fixed frequency, variable
15 frequency, or programmable frequency.
17 - "external"
18 - "internal-fixed"
19 - "internal-variable"
20 - "internal-programmable"
22 sof-synchronized:
[all …]
|
| /Zephyr-latest/drivers/clock_control/ |
| D | Kconfig.stm32 | 1 # STM32 MCU clock control driver config
5 # SPDX-License-Identifier: Apache-2.0
8 bool "STM32 Reset & Clock Control"
15 $(dt_nodelabel_has_prop,clk_hse,css-enabled))
17 Enable driver for Reset & Clock Control subsystem found
23 DT_STM32_HSE_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_HSE_CLOCK),clock-frequency)
30 Value of external high-speed clock (HSE). This symbol could be optionally
31 configured using device tree by setting "clock-frequency" value of clk_hse
35 clock-frequency = <DT_FREQ_M(25)>;
61 to occur, in order to determine precisely the LSI period, and thus frequency.
[all …]
|
| D | Kconfig.nrf | 4 # SPDX-License-Identifier: Apache-2.0
11 of the clock control driver.
62 If calibration is disabled when RC is used for low frequency clock then
63 accuracy of the low frequency clock will degrade. Disable on your own
74 Enabling indicates that calibration is performed by the clock control driver.
177 bool "nRF clock control support"
184 Support for nRF clock control devices.
197 bool "Clock control for global HSFLL"
204 int "Frequency request timeout in milliseconds"
208 bool "Request LOW frequency on init"
[all …]
|
| D | Kconfig.litex | 1 # LiteX SoC Builder clock control driver
4 # SPDX-License-Identifier: Apache-2.0
7 bool "LiteX MMCM clock control"
11 This option enables LiteX clock control driver.
13 such as phase, duty cycle, frequency for up to 7
|
| D | Kconfig.cavs | 1 # Intel cAVS clock control driver
4 # SPDX-License-Idertifier: Apache-2.0
7 bool "Intel CAVS clock control"
13 thus frequency) to be chosen.
|
| /Zephyr-latest/tests/drivers/clock_control/nrf_clock_control/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
21 .frequency = MHZ(128),
26 .frequency = MHZ(320),
31 .frequency = MHZ(64),
40 .frequency = MHZ(16),
45 .frequency = MHZ(16),
50 .frequency = MHZ(16),
66 .frequency = MHZ(16),
71 .frequency = MHZ(19),
76 .frequency = MHZ(16),
[all …]
|
| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/ |
| D | adsp_shim.h | 4 * SPDX-License-Identifier: Apache-2.0
15 * Power Management / Clock Control (HST) Registers
18 * and clock control operation for DSP FW.
32 * Power Management / Clock Control (ULP) Registers
35 * and clock control operation for DSP FW.
41 /* HP RING Oscillator Clock Frequency */
44 /* XTAL Oscillator Clock Frequency */
47 /* LP RING Oscillator Clock Frequency */
50 /* Serial I/O RING Oscillator Clock Frequency */
53 /* High Speed I/O RING Oscillator Clock Frequency */
[all …]
|
| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/ |
| D | adsp_shim.h | 4 * SPDX-License-Identifier: Apache-2.0
15 * Power Management / Clock Control (HST) Registers
18 * and clock control operation for DSP FW.
32 * Power Management / Clock Control (ULP) Registers
35 * and clock control operation for DSP FW.
41 /* HP RING Oscillator Clock Frequency */
44 /* XTAL Oscillator Clock Frequency */
47 /* LP RING Oscillator Clock Frequency */
50 /* Serial I/O RING Oscillator Clock Frequency */
53 /* High Speed I/O RING Oscillator Clock Frequency */
[all …]
|
| /Zephyr-latest/dts/bindings/display/ |
| D | istech,ist3931.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [i2c-device.yaml, display-controller.yaml]
11 reset-gpios:
12 type: phandle-array
21 x-offset:
26 y-offset:
31 voltage-converter:
35 voltage-follower:
39 lcd-bias:
44 lcd-ct:
[all …]
|
| D | sharp,ls0xx.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [spi-device.yaml, display-controller.yaml]
11 extcomin-gpios:
12 type: phandle-array
18 extcomin-frequency:
20 description: EXTCOMIN pin toggle frequency
22 The frequency with which the EXTCOMIN pin should be toggled. See
23 datasheet of particular display. Higher frequency gives better
24 contrast while low frequency saves power.
26 disp-en-gpios:
[all …]
|
| /Zephyr-latest/samples/drivers/clock_control_litex/ |
| D | README.rst | 1 .. zephyr:code-sample:: clock-control-litex
2 :name: LiteX clock control driver
3 :relevant-api: clock_control_interface
5 Use LiteX clock control driver to generate multiple clock signals.
10 This sample is providing an overview of LiteX clock control driver capabilities.
11 …lock Manager (MMCM) module to generate up to 7 clocks with defined phase, frequency and duty cycle.
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
21 …e driver, including default settings for clock outputs, is held in Device Tree clock control nodes.
23 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
[all …]
|
| /Zephyr-latest/tests/drivers/spi/spi_loopback/boards/ |
| D | s32z2xxdc2_s32z270_dspi.overlay | 4 * SPDX-License-Identifier: Apache-2.0
11 output-enable;
12 nxp,current-reference-control;
13 nxp,termination-resistor;
17 input-enable;
18 nxp,current-reference-control;
19 nxp,termination-resistor;
25 pinctrl-0 = <&dspi0_default>;
26 pinctrl-names = "default";
30 compatible = "test-spi-loopback-slow";
[all …]
|
| /Zephyr-latest/dts/bindings/serial/ |
| D | uart-controller.yaml | 8 clock-frequency:
10 description: Clock frequency information for UART operation
11 current-speed:
14 hw-flow-control:
16 description: Set to enable RTS/CTS flow control at boot time
23 - "none"
24 - "odd"
25 - "even"
26 stop-bits:
31 - "0_5"
[all …]
|
| /Zephyr-latest/dts/bindings/clock/ |
| D | nordic,nrf-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Nordic nRF clock control node
6 compatible: "nordic,nrf-clock"
17 hfclkaudio-frequency:
20 Frequency of the HFCLKAUDIO clock in Hz. Adjustable with 3.3 ppm
21 resolution in two frequency bands - 11.176 MHz to 11.402 MHz, and
|
| D | renesas,ra-cgc-pclk.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Renesas RA Clock Control Peripheral Clock
6 compatible: "renesas,ra-cgc-pclk"
8 include: [clock-controller.yaml, base.yaml]
14 description: Prescale divider to calculate the subclock frequency from the
15 system clock frequency.
17 "#clock-cells":
20 clock-cells:
21 - mstp
22 - stop_bit
|
| D | adi,max32-gcr.yaml | 1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
4 description: MAX32 Global Control
6 compatible: "adi,max32-gcr"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
17 sysclk-prescaler:
20 - 1
21 - 2
22 - 4
[all …]
|
| /Zephyr-latest/include/zephyr/drivers/clock_control/ |
| D | clock_control_litex.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief LiteX Clock Control driver interface
16 * @brief LiteX Clock Control driver interface
17 * @defgroup clock_control_litex_interface LiteX Clock Control driver interface
18 * @brief LiteX Clock Control driver interface
29 * @brief Structure for interfacing with clock control API
32 * @param rate Frequency to set given in Hz
|
| /Zephyr-latest/subsys/logging/backends/ |
| D | log_backend_swo.c | 4 * SPDX-License-Identifier: Apache-2.0
13 * An SWO viewer program will typically set-up the SWO port including its
14 * frequency when connected to the debug probe. Such configuration can persist
16 * re-configure the SWO port upon boot and set the frequency as specified by
18 * this frequency should much the one set by the SWO viewer program.
20 * The initialization code assumes that SWO core frequency is equal to HCLK
21 * as defined by the clock-frequency property in the CPU node. This may require
35 /* If ITM has pin control properties, apply them for SWO pins */
40 /* Set TPIU prescaler for the current debug trace clock frequency. */
46 #error "SWO reference frequency is not configured"
[all …]
|
| /Zephyr-latest/dts/bindings/debug/ |
| D | arm,itm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 # Pin control property may be used for SWO pins
7 include: [base.yaml, pinctrl-device.yaml]
10 swo-ref-frequency:
12 description: Reference clock frequency for SWO if different than CPU clock.
|
| /Zephyr-latest/soc/nxp/imx/imx7d/ |
| D | soc_clk_freq.h | 4 * SPDX-License-Identifier: Apache-2.0
19 * @brief Get clock frequency applies to the PWM module
22 * @return clock frequency (in HZ) applies to the PWM module
31 /*! @brief Root control names for root clock setting. */
51 /*! @brief CCM CCGR gate control. */
|
| /Zephyr-latest/dts/bindings/pwm/ |
| D | intel,blinky-pwm.yaml | 3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "intel,blinky-pwm"
9 include: [pwm-controller.yaml, base.yaml]
15 reg-offset:
18 description: PWM control register offset from base
20 clock-frequency:
23 description: PWM Peripheral Clock frequency in Hz
25 max-pins:
30 "#pwm-cells":
33 pwm-cells:
[all …]
|
| /Zephyr-latest/tests/subsys/usb/uac2/ |
| D | app.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <dt-bindings/usb/audio.h>
13 full-speed;
14 high-speed;
15 audio-function = <AUDIO_FUNCTION_HEADSET>;
18 compatible = "zephyr,uac2-clock-source";
19 clock-type = "internal-programmable";
20 frequency-control = "host-programmable";
21 sampling-frequencies = <48000>;
25 compatible = "zephyr,uac2-input-terminal";
[all …]
|
| /Zephyr-latest/dts/bindings/dma/ |
| D | xilinx,axi-dma-base.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 include: dma-controller.yaml
13 description: DMA Control registers
21 interrupt-parent:
26 type: phandle-array
28 clock-frequency:
36 - 32
37 - 64
39 axistream-connected:
43 The axistream-connected and axistream-control-connected properties can easily cause circular
[all …]
|
| /Zephyr-latest/boards/infineon/cy8cproto_062_4343w/ |
| D | cy8cproto_062_4343w.dts | 3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "cy8cproto_062_4343w-common.dtsi"
10 #include "cy8cproto_062_4343w-pinctrl.dtsi"
17 uart-5 = &uart5;
18 i2c-0 = &i2c3;
27 zephyr,shell-uart = &uart5;
28 zephyr,bt-hci = &bt_hci_uart;
37 compatible = "infineon,cat1-uart";
39 current-speed = <115200>;
[all …]
|
| /Zephyr-latest/dts/bindings/video/ |
| D | ovti,ov2640.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 reset-gpios:
10 type: phandle-array
13 reset. The sensor receives this as an active-low signal.
15 clock-rate-control:
19 Define the value to the Clock Rate Control register. By changing
22 Bit[7] Internal frequency doublers ON/OFF selection.
29 include: i2c-device.yaml
|
12345678910>>...17
