Lines Matching +full:frequency +full:- +full:control

1 .. zephyr:code-sample:: clock-control-litex
2    :name: LiteX clock control driver
3    :relevant-api: clock_control_interface
5    Use LiteX clock control driver to generate multiple clock signals.
10 This sample is providing an overview of LiteX clock control driver capabilities.
11 …lock Manager (MMCM) module to generate up to 7 clocks with defined phase, frequency and duty cycle.
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
21 …e driver, including default settings for clock outputs, is held in Device Tree clock control nodes.
23 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
25    :start-at: clk0: clock-controller@0 {
26    :end-at: };
29 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
31    :start-at: clk1: clock-controller@1 {
32    :end-at: };
35 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
37    :start-at: clock0: clock@e0004800 {
38    :end-at: };
41 …frequency set to 100MHz, 0 degrees phase offset and 50% duty cycle. Special care should be taken w…
48 The driver is interfaced with the :ref:`Clock Control API <clock_control_api>` function ``clock_con…
51 | This code will try to set on ``clk0`` frequency 50MHz, 90 degrees of phase offset and 75% duty cy…
53 .. code-block:: c
70 … output status (frequency, duty and phase offset) can be acquired with function ``clock_control_ge…
79 * Frequency range,
82 * Setting frequency, duty and phase at once, then check clock status and rate,
96 .. code-block:: none
98   west build -b litex_vexriscv zephyr/samples/drivers/clock_control
105 .. code-block:: none
114   [00:00:00.440,000] <inf> CLK_CTRL_LITEX: LiteX Clock Control driver initialized
115   *** Booting Zephyr OS build zephyr-v2.2.0-2810-g1ca5dda196c3  ***
116   Clock Control Example! riscv32
118   clock control device is 0x40013460, name is clock0
135 - :ref:`litex-vexriscv`