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/Zephyr-latest/dts/bindings/pwm/
Draspberrypi,pico-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "raspberrypi,pico-pwm"
8 include: [pwm-controller.yaml, pinctrl-device.yaml, reset-device.yaml, base.yaml]
17 divider-int-0:
18 type: int
20 The integral part of the divider for pwm slice 0.
22 as the integer part of the divider.
26 divider-frac-0:
27 type: int
29 The fractional part of the divider for pwm slice 0.
[all …]
/Zephyr-latest/soc/nxp/kinetis/k8x/
DKconfig5 # SPDX-License-Identifier: Apache-2.0
35 int "Freescale K8x core clock divider"
42 int "Freescale K8x bus clock divider"
49 int "Freescale K8x FlexBus clock divider"
56 int "Freescale K8x flash clock divider"
57 default 5
/Zephyr-latest/dts/bindings/clock/
Dnordic,nrf-auxpll.yaml2 # SPDX-License-Identifier: Apache-2.0
9 f_out = ((R + A * 2^(-16)) * f_src) / B
13 - A: nordic,frequency
14 - B: nordic,outdiv
15 - R: nordic,range (3=low, 4=mid, 5=high, 6=statichigh)
16 - f_src: Source frequency, given by clocks
18 compatible: "nordic,nrf-auxpll"
21 - base.yaml
22 - clock-controller.yaml
23 - nordic-nrf-ficr-client.yaml
[all …]
Dnxp,kinetis-mcg.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-mcg"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
18 type: int
19 enum: [0, 1, 2, 3, 4, 5, 6, 7]
21 Internal Reference Clock Divider.
25 type: int
26 enum: [0, 1, 2, 3, 4, 5, 6, 7]
28 Second Low-frequency Internal Reference Clock Divider.
[all …]
Dnuvoton,npcm-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
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Dst,stm32h7rs-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
14 "clock-frequency" property.
20 clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7rs-rcc"
33 include: [clock-controller.yaml, base.yaml]
39 "#clock-cells":
42 clock-frequency:
44 type: int
49 type: int
[all …]
/Zephyr-latest/drivers/mdio/
Dmdio_xmc4xxx.c4 * SPDX-License-Identifier: Apache-2.0
30 uint8_t divider; member
35 {.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
36 {.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
37 {.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
51 static int mdio_xmc4xxx_transfer(const struct device *dev, uint8_t phy_addr, uint8_t reg_addr, in mdio_xmc4xxx_transfer()
54 const struct mdio_xmc4xxx_dev_config *const dev_cfg = dev->config; in mdio_xmc4xxx_transfer()
55 ETH_GLOBAL_TypeDef *const regs = dev_cfg->regs; in mdio_xmc4xxx_transfer()
56 struct mdio_xmc4xxx_dev_data *const dev_data = dev->data; in mdio_xmc4xxx_transfer()
58 int ret = 0; in mdio_xmc4xxx_transfer()
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/Zephyr-latest/drivers/clock_control/
Dclock_control_lpc11u6x.h4 * SPDX-License-Identifier: Apache-2.0
12 #define LPC11U6X_SYS_AHB_CLK_CTRL_I2C0 (1 << 5)
26 #define LPC11U6X_PDRUNCFG_SYSOSC_PD (1 << 5)
38 #define LPC11U6X_SYS_PLL_CTRL_PSEL_SHIFT 5
46 #define LPC11U6X_PRESET_CTRL_USART1 (1 << 5)
79 volatile uint32_t sys_ahb_clk_div; /* System clock divider */
83 volatile uint32_t ssp0_clk_div; /* SSP0 clock divider */
84 volatile uint32_t usart0_clk_div; /* USART0 clock divider */
85 volatile uint32_t ssp1_clk_div; /* SSP1 clock divider */
86 volatile uint32_t frg_clk_div; /* USART 1-4 fractional baud
[all …]
Dclock_control_r8a779f0_cpg_mssr.c7 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
17 #include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
82 static int r8a779f0_cpg_enable_disable_core(const struct device *dev, in r8a779f0_cpg_enable_disable_core()
85 int ret = 0; in r8a779f0_cpg_enable_disable_core()
88 switch (clk_info->module) { in r8a779f0_cpg_enable_disable_core()
90 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
100 ret = -ENOTSUP; in r8a779f0_cpg_enable_disable_core()
105 rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg); in r8a779f0_cpg_enable_disable_core()
[all …]
Dclock_control_r8a7795_cpg_mssr.c6 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
15 #include <zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h>
74 static int r8a7795_cpg_enable_disable_core(const struct device *dev, in r8a7795_cpg_enable_disable_core()
77 int ret = 0; in r8a7795_cpg_enable_disable_core()
82 switch (clk_info->module) { in r8a7795_cpg_enable_disable_core()
87 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
100 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
105 ret = -ENOTSUP; in r8a7795_cpg_enable_disable_core()
[all …]
Dclock_control_litex.c4 * SPDX-License-Identifier: Apache-2.0
47 if (i == 5) { in litex_clk_regs_addr_init()
52 m.clkout[5].reg1 = CLKOUT5_REG1; in litex_clk_regs_addr_init()
53 m.clkout[5].reg2 = CLKOUT5_REG2; in litex_clk_regs_addr_init()
66 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
213 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()
219 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()
234 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1; in litex_clk_assert_reg()
244 static int litex_clk_wait(uint32_t reg) in litex_clk_wait()
251 timeout = ldev->timeout.lock; in litex_clk_wait()
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Dclock_control_npcm.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/npcm_clock.h>
63 #define NPCM_CLOCK_BUS_APB1 5
78 #define NPCM_PWDWN_CTL5 5
91 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
92 /* APB1 clock divider */
93 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
94 /* APB2 clock divider */
95 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
96 /* APB3 clock divider */
[all …]
/Zephyr-latest/dts/bindings/timer/
Dambiq,stimer.yaml2 # SPDX-License-Identifier: Apache-2.0
17 clk-source:
18 type: int
21 clk-source specifies the clock source that used by the system timer.
23 0 - NOCLK : No clock enabled.
24 1 - HFRC_DIV16 : 3MHz from the HFRC clock divider.
25 2 - HFRC_DIV256 : 187.5KHz from the HFRC clock divider.
26 3 - XTAL_DIV1 : 32768Hz from the crystal oscillator.
27 4 - XTAL_DIV2 : 16384Hz from the crystal oscillator.
28 5 - XTAL_DIV32 : 1024Hz from the crystal oscillator.
[all …]
/Zephyr-latest/drivers/serial/
Duart_b91.c4 * SPDX-License-Identifier: Apache-2.0
22 ((const struct uart_b91_config *)dev->config)->uart_addr)
38 #define UART_STOP_BIT_2 BIT(5)
111 return (uart->bufcnt & FLD_UART_TX_BUF_CNT) >> FLD_UART_TX_BUF_CNT_OFFSET; in uart_b91_get_tx_bufcnt()
117 return (uart->bufcnt & FLD_UART_RX_BUF_CNT) >> FLD_UART_RX_BUF_CNT_OFFSET; in uart_b91_get_rx_bufcnt()
123 uint32_t i = 5; in uart_b91_is_prime()
131 for (i = 5; i * i < n; i += 6) { in uart_b91_is_prime()
142 uint16_t *divider, uint8_t *bwpc) in uart_b91_cal_div_and_bwpc() argument
151 primeDec = 10 * pclk / baudrate - 10 * primeInt; in uart_b91_cal_div_and_bwpc()
155 } else if (primeDec > 5) { in uart_b91_cal_div_and_bwpc()
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Duart_sy1xx.c2 * SPDX-License-Identifier: Apache-2.0
58 struct sy1xx_uart_config *config = (struct sy1xx_uart_config *)dev->config; in sy1xx_uart_configure()
60 if (uart_cfg->baudrate == 0) { in sy1xx_uart_configure()
61 return -1; in sy1xx_uart_configure()
66 * and then will restart from 0, so we must give div - 1 as in sy1xx_uart_configure()
67 * divider in sy1xx_uart_configure()
69 uint32_t divider = sy1xx_soc_get_peripheral_clock() / uart_cfg->baudrate - 1; in sy1xx_uart_configure() local
72 * [31:16]: clock divider (from SoC clock) in sy1xx_uart_configure()
77 * [2:1]: bits 00 = 5 bits in sy1xx_uart_configure()
85 volatile uint32_t setup = 0x0306 | uart_cfg->parity; in sy1xx_uart_configure()
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dinvensense,mpu9250.yaml2 # SPDX-License-Identifier: Apache-2.0
5 InvenSense MPU-9250 Nine-Axis (Gyro + Accelerometer + Compass). See more
6 info at https://www.invensense.com/products/motion-tracking/9-axis/mpu-9250/
10 include: [sensor-device.yaml, i2c-device.yaml]
13 irq-gpios:
14 type: phandle-array
16 The INT signal default configuration is active-high. The
21 gyro-sr-div:
22 type: int
25 Default gyrscope sample rate divider. This divider is only effective
[all …]
Dti,fdc2x1x.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 sd-gpios:
12 type: phandle-array
18 intb-gpios:
19 type: phandle-array
28 Set to identify the sensor as FDC2114 or FDC2214 (4-channel version)
33 Set the Auto-Scan Mode.
36 "active-channel" (single channel mode).
38 true = Auto-Scan conversions as selected by "rr-sequence"
[all …]
Dadi,adltc2990.yaml2 # SPDX-License-Identifier: Apache-2.0
9 include: [sensor-device.yaml, i2c-device.yaml]
12 temperature-format:
13 type: int
19 - 0
20 - 1
22 acquistion-format:
23 type: int
29 - 0
30 - 1
[all …]
/Zephyr-latest/dts/bindings/misc/
Dnxp,s32-emios.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-emios"
21 interrupt-names:
27 clock-divider:
28 type: int
31 Clock divider value for the global prescaler. Could be in range [1 ... 256]
33 internal-cnt:
34 type: int
39 child-binding:
40 child-binding:
[all …]
Drenesas,ra-agt.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,ra-agt"
15 type: int
18 renesas,count-source:
23 - "AGT_CLOCK_PCLKB"
24 - "AGT_CLOCK_LOCO"
28 AGT clock divider for LOCO and SUBCLOCK. timer clock = (clock-source / (1 << prescaler))
31 type: int
34 - 0
35 - 1
[all …]
/Zephyr-latest/dts/bindings/video/
Dovti,ov2640.yaml2 # SPDX-License-Identifier: Apache-2.0
9 reset-gpios:
10 type: phandle-array
13 reset. The sensor receives this as an active-low signal.
15 clock-rate-control:
16 type: int
25 Bit[5:0] Clock divider.
27 CLK = XVCLK /(decimal value of CLKRC[5:0] + 1)
29 include: i2c-device.yaml
/Zephyr-latest/drivers/sensor/st/lis3mdl/
Dlis3mdl.c4 * SPDX-License-Identifier: Apache-2.0
22 uint16_t divider) in lis3mdl_convert() argument
24 /* val = raw_val / divider */ in lis3mdl_convert()
25 val->val1 = raw_val / divider; in lis3mdl_convert()
26 val->val2 = (((int64_t)raw_val % divider) * 1000000L) / divider; in lis3mdl_convert()
29 static int lis3mdl_channel_get(const struct device *dev, in lis3mdl_channel_get()
33 struct lis3mdl_data *drv_data = dev->data; in lis3mdl_channel_get()
37 lis3mdl_convert(val, drv_data->x_sample, in lis3mdl_channel_get()
39 lis3mdl_convert(val + 1, drv_data->y_sample, in lis3mdl_channel_get()
41 lis3mdl_convert(val + 2, drv_data->z_sample, in lis3mdl_channel_get()
[all …]
/Zephyr-latest/drivers/watchdog/
Dwdt_iwdg_stm32.c2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
7 * SPDX-License-Identifier: Apache-2.0
48 * Status register needs 5 LSI clock cycles divided by prescaler to be updated.
66 uint16_t divider = 4U; in iwdg_stm32_convert_timeout() local
72 while ((ticks / divider) > IWDG_RELOAD_MAX) { in iwdg_stm32_convert_timeout()
74 divider = 4U << shift; in iwdg_stm32_convert_timeout()
82 *reload = (uint32_t)(ticks / divider) - 1U; in iwdg_stm32_convert_timeout()
85 static int iwdg_stm32_setup(const struct device *dev, uint8_t options) in iwdg_stm32_setup()
110 return -ENOTSUP; in iwdg_stm32_setup()
117 LL_IWDG_SetPrescaler(iwdg, data->prescaler); in iwdg_stm32_setup()
[all …]
/Zephyr-latest/include/zephyr/drivers/can/
Dcan_sja1000.h4 * SPDX-License-Identifier: Apache-2.0
26 #define CAN_SJA1000_OCR_OCPOL1 BIT(5)
38 * @name SJA1000 Clock Divider Register (CDR) bits
44 #define CAN_SJA1000_CDR_RXINTEN BIT(5)
54 #define CAN_SJA1000_CDR_CD_DIV12 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 5U)
84 * @brief SJA1000 driver front-end callback for writing a register value
93 * @brief SJA1000 driver front-end callback for reading a register value
121 * @param _cdr Initial SJA1000 Clock Divider Register (CDR) value
143 * @param _cdr Initial SJA1000 Clock Divider Register (CDR) value
189 int can_sja1000_set_timing(const struct device *dev, const struct can_timing *timing);
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,lpc11u6x-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
4 compatible: "nxp,lpc11u6x-pinctrl"
7 - name: base.yaml
8 - name: nxp,lpc-iocon-pinctrl.yaml
9 child-binding:
10 child-binding:
11 property-allowlist:
12 - pinmux
13 - nxp,invert
14 - nxp,analog-mode
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