Lines Matching +full:divider +full:- +full:int +full:- +full:5
2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
24 compatible: "nuvoton,npcm-pcc"
26 include: [clock-controller.yaml, base.yaml]
32 clock-frequency:
34 type: int
47 - 100000000
48 - 96000000
49 - 80000000
50 - 66000000
51 - 50000000
52 - 48000000
53 - 40000000
54 - 33000000
56 core-prescaler:
57 type: int
62 - The maximum CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
63 - Only the following values are allowed:
68 5, CORE_CLK = OFMCLK / 5
75 - 1
76 - 2
77 - 3
78 - 4
79 - 5
80 - 6
81 - 7
82 - 8
83 - 9
84 - 10
86 apb1-prescaler:
87 type: int
92 - The maximum APB1_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
93 - Only the following values are allowed:
98 5, APB1_CLK = OFMCLK / 5
105 - 1
106 - 2
107 - 3
108 - 4
109 - 5
110 - 6
111 - 7
112 - 8
113 - 9
114 - 10
116 apb2-prescaler:
117 type: int
122 - The maximum APB2_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
123 - Only the following values are allowed:
128 5, APB2_CLK = OFMCLK / 5
135 - 1
136 - 2
137 - 3
138 - 4
139 - 5
140 - 6
141 - 7
142 - 8
143 - 9
144 - 10
146 apb3-prescaler:
147 type: int
152 - The maximum APB3_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
153 - Only the following values are allowed:
158 5, APB3_CLK = OFMCLK / 5
165 - 1
166 - 2
167 - 3
168 - 4
169 - 5
170 - 6
171 - 7
172 - 8
173 - 9
174 - 10
176 ahb6-prescaler:
177 type: int
181 programmable divider controlled by the AHB6DIV field in HFCGP register.
183 - The maximum AHB6_CLK frequency is either the CLK frequency divided by 1 or 100 MHz.
184 - Only the following values are allowed:
189 - 1
190 - 2
191 - 4
193 fiu-prescaler:
194 type: int
198 programmable divider controlled by the FIUDIV field in HFCBCD1 register.
200 - The maximum FIUCLK frequency is either the CLK frequency divided by 1 or 100MHz.
201 - Only the following values are allowed:
206 - 1
207 - 2
208 - 4
210 i3c-prescaler:
211 type: int
217 - 1
218 - 2
219 - 4
221 clock-cells:
222 - clk_id