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Searched +full:core +full:- +full:clock +full:- +full:div (Results 1 – 25 of 42) sorted by relevance

12

/Zephyr-latest/boards/infineon/cy8cproto_063_ble/
Dcy8cproto_063_ble.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
11 #include "cy8cproto_063_ble-pinctrl.dtsi"
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 model = "CY8CPROTO-063-BLE PSOC™ 6 BLE Prototyping Kit";
19 uart-5 = &uart5;
29 zephyr,shell-uart = &uart5;
30 zephyr,bt-hci = &bluetooth;
33 /delete-node/ cpu@0;
36 compatible = "gpio-leds";
[all …]
/Zephyr-latest/boards/infineon/cy8ckit_062s2_ai/
Dcy8ckit_062s2_ai.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "CY8CKIT-062S2-AI PSOC 6 AI Evaluation Kit";
18 zephyr,shell-uart = &uart5;
30 compatible = "gpio-leds";
42 compatible = "gpio-keys";
53 clock-frequency = <100000000>;
57 clock-div = <1>;
61 /* CM4 core clock = 100MHz
[all …]
/Zephyr-latest/boards/infineon/cy8cproto_062_4343w/
Dcy8cproto_062_4343w.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "cy8cproto_062_4343w-common.dtsi"
10 #include "cy8cproto_062_4343w-pinctrl.dtsi"
17 uart-5 = &uart5;
18 i2c-0 = &i2c3;
27 zephyr,shell-uart = &uart5;
28 zephyr,bt-hci = &bt_hci_uart;
37 compatible = "infineon,cat1-uart";
39 current-speed = <115200>;
[all …]
/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dsoc.c2 * Copyright 2021-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/linker/linker-defs.h>
25 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
28 /* Memcpy macro to copy segments from secondary core image stored in flash
29 * to RAM section that secondary core boots from.
33 memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_##n) - ADJUSTED_LMA), \
47 /* Dual core mode is enabled, and messaging unit is present */
72 "ARM PLL must have clock-mult property");
74 "ARM PLL must have clock-div property");
[all …]
/Zephyr-latest/soc/nxp/imxrt/imxrt118x/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/linker/linker-defs.h>
24 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
29 * which is useful when debug reset, where the core has already get the
49 /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
60 /* Enable Sys Pll1 divide-by-2 clock or not */
62 /* Enable Sys Pll1 divide-by-5 clock or not */
80 * Description : FLEXSPI clock source safe configuration weak function.
81 * Called before clock source configuration.
82 * Note : Users need override this function to change FLEXSPI clock source to stable
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg4_i2c1_hsi_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
27 /delete-property/ clocks;
32 /delete-property/ clocks;
[all …]
Dg0_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
27 /delete-property/ clocks;
32 /delete-property/ clocks;
[all …]
Dl4_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
23 /delete-property/ msi-range;
27 /delete-property/ div-m;
28 /delete-property/ mul-n;
29 /delete-property/ div-p;
30 /delete-property/ div-q;
31 /delete-property/ div-r;
32 /delete-property/ clocks;
[all …]
Dl4_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
23 /delete-property/ msi-range;
27 /delete-property/ div-m;
28 /delete-property/ mul-n;
29 /delete-property/ div-p;
30 /delete-property/ div-q;
31 /delete-property/ div-r;
32 /delete-property/ clocks;
[all …]
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
27 /delete-property/ clocks;
32 /delete-property/ clocks;
[all …]
Dwb_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Df4_i2s2_pll.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
30 /delete-property/ mul;
31 /delete-property/ div;
32 /delete-property/ prediv;
33 /delete-property/ xtpre;
34 /delete-property/ clocks;
39 /delete-property/ clocks;
40 /delete-property/ clock-frequency;
[all …]
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwl_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwb_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Df0_i2c1_hsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
30 /delete-property/ mul;
31 /delete-property/ div;
32 /delete-property/ prediv;
33 /delete-property/ xtpre;
34 /delete-property/ clocks;
39 /delete-property/ clocks;
40 /delete-property/ clock-frequency;
[all …]
Df3_i2c1_hsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
30 /delete-property/ mul;
31 /delete-property/ div;
32 /delete-property/ prediv;
33 /delete-property/ xtpre;
34 /delete-property/ clocks;
39 /delete-property/ clocks;
40 /delete-property/ clock-frequency;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ hse-bypass;
20 /delete-property/ clock-frequency;
25 /delete-property/ hsi-div;
41 /delete-property/ div-m;
42 /delete-property/ mul-n;
43 /delete-property/ div-p;
44 /delete-property/ div-q;
45 /delete-property/ div-r;
46 /delete-property/ clocks;
[all …]
/Zephyr-latest/dts/bindings/clock/
Dmicrochip,xec-pcr.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Microchip XEC Power Clock Reset and VBAT register (PCR)
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
25 pll-32k-src:
28 description: 32 KHz clock source for PLL
[all …]
Dst,stm32wba-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-presacler = <1>;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ clock-frequency;
20 /delete-property/ hse-bypass;
33 /delete-property/ msi-range;
34 /delete-property/ msi-pll-mode;
39 /delete-property/ msi-range;
40 /delete-property/ msi-pll-mode;
44 /delete-property/ div-m;
45 /delete-property/ mul-n;
46 /delete-property/ div-q;
[all …]
/Zephyr-latest/boards/weact/stm32f405_core/
Dweact_stm32f405_core.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f4/stm32f405rgtx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "WeAct Studio STM32F405 Core Board";
14 compatible = "weact,stm32f405-core", "st,stm32f405";
18 zephyr,shell-uart = &usart1;
25 compatible = "gpio-leds";
33 compatible = "gpio-keys";
54 clock-frequency = <DT_FREQ_M(8)>;
[all …]
/Zephyr-latest/boards/arduino/opta/
Darduino_opta_stm32h747xx_m7.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include <st/h7/stm32h747xihx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include "arduino_opta-common.dtsi"
15 model = "Arduino OPTA M7 core Programmable Logic Controller";
16 compatible = "arduino,opta-m7";
21 zephyr,code-partition = &slot0_partition;
26 pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
27 pinctrl-names = "default";
[all …]
/Zephyr-latest/boards/weact/stm32g431_core/
Dweact_stm32g431_core.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/g4/stm32g431c(6-8-b)ux-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/usb-c/pd.h>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "WeAct Studio STM32G431 Core Board";
15 compatible = "weact,stm32g431-core";
19 zephyr,shell-uart = &usart2;
26 mcuboot-button0 = &button_0;
27 mcuboot-led0 = &led_0;
[all …]
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Dadsp_shim.h4 * SPDX-License-Identifier: Apache-2.0
102 #define CAVS_CLKCTL_SLIMFDCGB BIT(25) /* Slimbus force dynamic clock gating*/
103 #define CAVS_CLKCTL_TCPLCG(x) BIT(16 + x) /* Set bit: prevent clock gating on core x */
104 #define CAVS_CLKCTL_SLIMCSS BIT(6) /* Slimbus clock (0: XTAL, 1: Audio) */
105 #define CAVS_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */
107 #define CAVS_CLKCTL_OCS BIT(2) /* Oscillator clock (0: LP, 1: HP) */
108 #define CAVS_CLKCTL_LMCS BIT(1) /* LP mem divisor (0: div/2, 1: div/4) */
109 #define CAVS_CLKCTL_HMCS BIT(0) /* HP mem divisor (0: div/2, 1: div/4) */

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