| /Zephyr-latest/samples/drivers/clock_control_litex/ |
| D | README.rst | 1 .. zephyr:code-sample:: clock-control-litex
2 :name: LiteX clock control driver
3 :relevant-api: clock_control_interface
5 Use LiteX clock control driver to generate multiple clock signals.
10 This sample is providing an overview of LiteX clock control driver capabilities.
11 The driver uses Mixed Mode Clock Manager (MMCM) module to generate up to 7 clocks with defined phas…
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
17 * Optional: clock output signals redirected to output pins for testing
21 …guration of the driver, including default settings for clock outputs, is held in Device Tree clock…
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| /Zephyr-latest/include/zephyr/drivers/clock_control/ |
| D | clock_control_litex.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief LiteX Clock Control driver interface
16 * @brief LiteX Clock Control driver interface
17 * @defgroup clock_control_litex_interface LiteX Clock Control driver interface
18 * @brief LiteX Clock Control driver interface
29 * @brief Structure for interfacing with clock control API
31 * @param clkout_nr Number of clock output to be changed
33 * @param phase Phase offset in degrees
34 * @param duty Duty cycle of clock signal in percent
40 uint16_t phase; member
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| /Zephyr-latest/dts/bindings/clock/ |
| D | raspberrypi,pico-rosc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "raspberrypi,pico-rosc"
9 include: [fixed-clock.yaml, fixed-factor-clock.yaml]
17 - LOW: 8 (default)
18 - MEDIUM: 6
19 - HIGH: 4
20 - TOOHIGH: 2
22 stage-drive-strength:
29 phase-flip:
32 Flipping phase-shifter output.
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| D | silabs,series2-hfrcodpll.yaml | 1 compatible: "silabs,series2-hfrcodpll"
4 Silicon Labs HFRCODPLL peripheral (high-frequency RC oscillator with digital phase-locked loop).
5 Can be used as a free-running RC oscillator or with PLL lock to the crystal oscillators HFXO
7 the `dpll-*` options to desired values.
9 In PLL mode, `clock-frequency` represents the target PLL frequency.
10 In free-running mode, `clock-frequency` represents the HFRCO band to use.
12 include: fixed-clock.yaml
15 dpll-n:
18 dpll-m:
21 dpll-edge:
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| D | litex,clkout.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 LiteX Mixed Mode Clock Manager clock output binding
13 "#clock-cells":
17 Number of cells in a clock specifier;
18 Typically 0 for nodes with a single clock output
19 and 1 for nodes with multiple clock outputs.
22 clock-output-names:
26 string of clock output signal name.
28 litex,clock-frequency:
32 default frequency in Hz for clock output
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| D | litex,clk.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: [clock-controller.yaml, base.yaml]
7 LiteX Mixed Mode Clock Manager
8 Common clock driver with MMCM unit for dynamic reconfiguration
9 of up to 7 clock outputs with ability to change frequency, duty
10 cycle and phase offset
14 clock-cells:
15 - id
22 "#clock-cells":
26 clock-output-names:
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| /Zephyr-latest/dts/bindings/wifi/ |
| D | nordic,nrf70-qspi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: This is a representation of the nRF70 Wi-Fi chip.
8 on-bus: qspi
11 qspi-frequency:
15 Maximum clock speed (in Hz) supported by the device.
20 qspi-quad-mode:
24 SPI mode (2 IO lines - MOSI & MISO).
26 qspi-rx-delay:
30 Number of clock cycles from the rising edge of the SPI clock
33 qspi-cpha:
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| /Zephyr-latest/samples/drivers/clock_control_litex/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
13 /* Select clock outputs for tests [0-6] */
33 /* Values for phase test */
62 /* LiteX Common Clock Driver tests */
75 printf("CLKOUT%d: get_status: rate:%d phase:%d duty:%d\n", in litex_clk_test_getters()
76 i, setup.rate, setup.phase, setup.duty); in litex_clk_test_getters()
90 .phase = LITEX_TEST_SINGLE_PHASE_VAL in litex_clk_test_single()
96 .phase = LITEX_TEST_SINGLE_PHASE_VAL2, in litex_clk_test_single()
122 .phase = LITEX_TEST_FREQUENCY_PHASE_VAL in litex_clk_test_freq()
138 * specific clock output depends on devicetree config in litex_clk_test_freq()
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| /Zephyr-latest/dts/bindings/memory-controllers/ |
| D | st,stm32-fmc-nor-psram.yaml | 2 # SPDX-License-Identifier: Apache-2.0
11 - 8 bits
12 - 16 bits
13 - 32 bits
15 - Asynchronous mode
16 - Burst mode for synchronous accesses with configurable option to split burst
18 - Multiplexed or non-multiplexed
20 - Asynchronous mode
21 - Burst mode for synchronous accesses
22 - Multiplexed or non-multiplexed
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| D | renesas,smartbond-nor-psram.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "renesas,smartbond-nor-psram"
14 is-ram:
19 dev-size:
25 dev-type:
31 dev-density:
40 dev-id:
46 reset-delay-us:
52 read-cs-idle-min-ns:
59 erase-cs-idle-min-ns:
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| /Zephyr-latest/drivers/clock_control/ |
| D | Kconfig.litex | 1 # LiteX SoC Builder clock control driver
4 # SPDX-License-Identifier: Apache-2.0
7 bool "LiteX MMCM clock control"
11 This option enables LiteX clock control driver.
12 It gives ability to change clock parameters
13 such as phase, duty cycle, frequency for up to 7
14 clock outputs
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| D | clock_control_litex.c | 4 * SPDX-License-Identifier: Apache-2.0
66 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
213 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()
219 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()
234 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1; in litex_clk_assert_reg()
251 timeout = ldev->timeout.lock; in litex_clk_wait()
253 timeout = ldev->timeout.drdy; in litex_clk_wait()
257 timeout--; in litex_clk_wait()
262 return -ETIME; in litex_clk_wait()
303 ldev->g_config.mul = 1; in litex_clk_update_global_config()
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| D | clock_stm32f2_f4_f7.c | 5 * SPDX-License-Identifier: Apache-2.0
55 * @brief calculate the CK48 frequency depending on its clock source
100 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
119 * locking phase since the system will be stalled during the switch in config_pll_sysclock()
120 * (ODSW) but the PLL clock system will be running during the locking in config_pll_sysclock()
121 * phase. See reference manual (RM0431) §4.1.4 Voltage regulator in config_pll_sysclock()
122 * Sub section: Entering Over-drive mode. in config_pll_sysclock()
139 * And start waiting for the PLL locking phase to complete. in config_pll_sysclock()
176 /* Power Interface clock enabled by default */ in config_enable_default_clocks()
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| /Zephyr-latest/dts/bindings/mtd/ |
| D | nordic,qspi-nor.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "nordic,qspi-nor"
9 include: [base.yaml, "jedec,spi-nor-common.yaml"]
11 on-bus: qspi
17 jedec-id:
23 The size in bits. Set this or size-in-bytes, but not both.
25 size-in-bytes:
31 quad-enable-requirements:
37 - "fastread" # Single data line SPI, FAST_READ (0x0B)
38 - "read2o" # Dual data line SPI, READ2O (0x3B)
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | nxp,s32-emios-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
11 - Channel 0 for mode OPWFMB
12 - Channel 1 for mode OPWMB
13 - Channel 2 for mode OPWMCB with deadtime inserted at leading edge
14 - Channel 3 for mode SAIC, use internal timebase with input filter = 2 eMIOS clock
19 pwm-mode = "OPWFMB";
22 duty-cycle = <32768>;
28 master-bus = <&emios1_bus_a>;
29 pwm-mode = "OPWMB";
30 duty-cycle = <32768>;
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| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | adi_max32_clock.h | 2 * Copyright (c) 2023-2024 Analog Devices, Inc.
4 * SPDX-License-Identifier: Apache-2.0
10 /** Peripheral clock register */
15 /** Clock source for peripheral interfaces like UART, WDT... */
16 #define ADI_MAX32_PRPH_CLK_SRC_PCLK 0 /* Peripheral clock */
17 #define ADI_MAX32_PRPH_CLK_SRC_EXTCLK 1 /* External clock */
24 #define ADI_MAX32_PRPH_CLK_SRC_IPLL 8 /* Internal Phase Lock Loop Oscillator */
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| /Zephyr-latest/dts/bindings/sdhc/ |
| D | zephyr,sdhc-spi-slot.yaml | 3 compatible: "zephyr,sdhc-spi-slot"
5 include: [spi-device.yaml]
8 power-delay-ms:
16 spi-clock-mode-cpol:
19 Clock polarity to use for SPI SDHC. Some cards respond properly
20 only when the clock goes low when not active.
22 spi-clock-mode-cpha:
25 Clock phase: this dictates when is the data captured, and depends
26 on the clock's polarity. When mode-cpol is set and this option as well,
30 pwr-gpios:
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| /Zephyr-latest/include/zephyr/net/ |
| D | gptp.h | 4 * SPDX-License-Identifier: Apache-2.0
98 /* Pre-calculated constants */
128 /** Clock identity of the port. */
184 /** Control value. Sync: 0, Follow-up: 2, Others: 5. */
195 (uscaled_ns_ptr)->low = \
197 (uscaled_ns_ptr)->high = 0; \
204 * @brief Define callback that is called after a phase discontinuity has been
222 * @brief Phase discontinuity callback structure.
224 * Stores the phase discontinuity callback information. Caller must make sure
233 /** Phase discontinuity callback. */
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| /Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/ |
| D | Kconfig | 2 # SPDX-License-Identifier: Apache-2.0
8 SPI mode value (clock polarity and phase) used in the test.
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| /Zephyr-latest/dts/bindings/mspi/ |
| D | mspi-device.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 on-bus: mspi
14 mspi-max-frequency:
18 Maximum clock frequency of device to configure in Hz.
22 mspi-io-mode:
25 - "MSPI_IO_MODE_SINGLE"
26 - "MSPI_IO_MODE_DUAL"
27 - "MSPI_IO_MODE_DUAL_1_1_2"
28 - "MSPI_IO_MODE_DUAL_1_2_2"
29 - "MSPI_IO_MODE_QUAD"
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| /Zephyr-latest/dts/bindings/qspi/ |
| D | nxp,s32-qspi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
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| /Zephyr-latest/dts/bindings/mipi-dbi/ |
| D | mipi-dbi-spi-device.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 include: [mipi-dbi-device.yaml]
18 list (see dt-bindings/spi/spi.h)
21 mipi-cpol:
24 SPI clock polarity which indicates the clock idle state.
25 If it is used, the clock idle state is logic high; otherwise, low.
26 mipi-cpha:
29 SPI clock phase that indicates on which edge data is sampled.
31 mipi-hold-cs:
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| /Zephyr-latest/dts/bindings/adc/ |
| D | atmel,sam-adc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam-adc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
23 description: CPU clock prescaler applied to get the ADC clock.
25 startup-time:
29 ADC startup time in ADC clock cycles.
32 settling-time:
36 ADC settling time in ADC clock cycles. When the gain, offset
39 settling time before starting the tracking phase.
42 tracking-time:
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| /Zephyr-latest/tests/drivers/can/timing/ |
| D | Kconfig | 2 # SPDX-License-Identifier: Apache-2.0
11 impose limits on which bitrates can be met due to limitations in the CAN core clock
15 - 10 kbit/s
16 - 20 kbit/s
17 - 50 kbit/s
18 - 125 kbit/s
19 - 250 kbit/s
20 - 500 kbit/s
21 - 800 kbit/s
22 - 1 Mbit/s
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | nxp,mcux-qdec.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mcux-qdec"
8 include: [pinctrl-device.yaml, sensor-device.yaml]
17 counts-per-revolution:
24 single-phase-mode:
31 filter-count:
39 filter-sample-period:
42 The sampling period (in IPBus clock cycles) of the decoder input signals.
48 ((FILT_CNT + 3) * FILT_PER) FILT clock cycles + 2 IPBus clock periods.
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