| /cmsis-dsp-latest/.github/workflows/ |
| D | runcpptest.yaml | 31 cache: 'pip'
32 cache-dependency-path: Testing/requirements.txt
39 - name: Cache packs
40 uses: actions/cache@v4
45 path: /home/runner/.cache/arm/packs
50 cache: "-cmsis_dsp_vcpkg"
55 - name: Cache boost
56 id: cache-boost
57 uses: actions/cache@v4
65 if: steps.cache-boost.outputs.cache-hit != 'true'
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| D | runtest.yaml | 29 cache: 'pip'
30 cache-dependency-path: Testing/requirements.txt
37 - name: Cache packs
38 uses: actions/cache@v4
43 path: /home/runner/.cache/arm/packs
48 cache: "-cmsis_dsp_vcpkg"
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| /cmsis-dsp-latest/Testing/FrameworkSource/ |
| D | IORunner.cpp | 107 So to ensure the conditions are always the same, the instruction cache in IORunner()
123 We always call the empty function once to ensure it is in the cache in IORunner()
136 should not be in the cache. in IORunner()
139 the code not in cache. in IORunner()
141 While for the code itself we have the value for the code in cache. in IORunner()
270 // Run the test once to force the code to be in cache. in run()
282 /* If cache analysis mode, we don't force the code to be in cache. */ in run()
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| /cmsis-dsp-latest/Testing/cmsis_build/configs/ |
| D | ARMCA7neon_config.txt | 19 … # (bool , run-time ) default = '0' : Set whether L1 I-cache has stateful imple…
20 … # (bool , run-time ) default = '0' : Set whether L1 D-cache has stateful imple…
21 … # (bool , run-time ) default = '0' : Set whether L2 cache has stateful imple…
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| D | ARMCA5neon_config.txt | 19 … # (bool , run-time ) default = '0' : Set whether D-cache has stateful imple…
20 … # (bool , run-time ) default = '0' : Set whether I-cache has stateful imple…
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| D | ARMCA9neon_config.txt | 19 … # (bool , run-time ) default = '0' : Set whether D-cache has stateful imple…
20 … # (bool , run-time ) default = '0' : Set whether I-cache has stateful imple…
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| /cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCA5/ |
| D | system_ARMCA5.c | 63 // Invalidate instruction cache and flush branch target cache in SystemInit()
68 // Invalidate data cache in SystemInit()
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| D | mmu_ARMCA5.c | 80 // L1 Cache info and restrictions about architecture of the caches (CCSIR register):
87 …ng a region as shareable forces the processor to not cache that region regardless of the inner cac…
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| D | startup_ARMCA5.c | 89 "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache in Reset_Handler()
90 "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache in Reset_Handler()
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| /cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCA7/ |
| D | system_ARMCA7.c | 63 // Invalidate instruction cache and flush branch target cache in SystemInit()
68 // Invalidate data cache in SystemInit()
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| D | mmu_ARMCA7.c | 80 // L1 Cache info and restrictions about architecture of the caches (CCSIR register):
87 …ng a region as shareable forces the processor to not cache that region regardless of the inner cac…
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| D | startup_ARMCA7.c | 89 "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache in Reset_Handler()
90 "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache in Reset_Handler()
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| /cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCA9/ |
| D | system_ARMCA9.c | 63 // Invalidate instruction cache and flush branch target cache in SystemInit()
68 // Invalidate data cache in SystemInit()
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| D | mmu_ARMCA9.c | 80 // L1 Cache info and restrictions about architecture of the caches (CCSIR register):
87 …ng a region as shareable forces the processor to not cache that region regardless of the inner cac…
|
| D | startup_ARMCA9.c | 89 "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache in Reset_Handler()
90 "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache in Reset_Handler()
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| /cmsis-dsp-latest/Testing/ |
| D | summaryBench.py | 119 …er.add_argument('-f', nargs='?',type = str, default="Output.pickle", help="Test description cache")
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| /cmsis-dsp-latest/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/ |
| D | system_SSE310MPS3.c | 83 /* Enable Loop and branch info cache */ in SystemInit()
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| /cmsis-dsp-latest/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/ |
| D | system_SSE300MPS3.c | 81 /* Enable Loop and branch info cache */ in SystemInit()
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| /cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/ |
| D | system_SSE300MPS3.c | 81 /* Enable Loop and branch info cache */ in SystemInit()
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| /cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/SSE-310-MPS3/ |
| D | system_SSE310MPS3.c | 83 /* Enable Loop and branch info cache */ in SystemInit()
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| /cmsis-dsp-latest/dsppp/RTE/Device/SSE-300-MPS3/ |
| D | system_SSE300MPS3.c | 85 /* Enable Loop and branch info cache */ in SystemInit()
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| D | system_SSE300MPS3.c.base@1.1.1 | 85 /* Enable Loop and branch info cache */
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| /cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM55/ |
| D | system_ARMCM55.c | 97 /* Enable Loop and branch info cache */ in SystemInit()
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| /cmsis-dsp-latest/Documentation/Doxygen/ |
| D | dsp.dxy.in | 465 # The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This
466 # cache is used to resolve symbols given their name and scope. Since this can be
468 # code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small
469 # doxygen will become slower. If the cache is too large, memory is wasted. The
470 # cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range
471 # is 0..9, the default is 0, corresponding to a cache size of 2^16=65536
472 # symbols. At the end of a run doxygen will report the cache usage and suggest
473 # the optimal cache size from a speed point of view.
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| /cmsis-dsp-latest/Source/MatrixFunctions/ |
| D | arm_mat_add_f32.c | 157 So no blocking is used for taking into account cache effects.
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