1/*
2 * Copyright (c) 2009-2022 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19/*
20 * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c
21 * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c
22 */
23
24#include "SSE300MPS3.h"
25
26/*----------------------------------------------------------------------------
27  Define clocks
28 *----------------------------------------------------------------------------*/
29 #define  XTAL             (32000000UL)
30 #define  SYSTEM_CLOCK     (XTAL)
31 #define  PERIPHERAL_CLOCK (25000000UL)
32
33/*----------------------------------------------------------------------------
34  Exception / Interrupt Vector table
35 *----------------------------------------------------------------------------*/
36extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
37
38/*----------------------------------------------------------------------------
39  System Core Clock Variable
40 *----------------------------------------------------------------------------*/
41uint32_t SystemCoreClock = SYSTEM_CLOCK;
42uint32_t PeripheralClock = PERIPHERAL_CLOCK;
43
44/*----------------------------------------------------------------------------
45  System Core Clock update function
46 *----------------------------------------------------------------------------*/
47void SystemCoreClockUpdate (void)
48{
49    SystemCoreClock = SYSTEM_CLOCK;
50    PeripheralClock = PERIPHERAL_CLOCK;
51}
52
53/*----------------------------------------------------------------------------
54  System initialization function
55 *----------------------------------------------------------------------------*/
56void SystemInit (void)
57{
58#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
59    SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
60#endif
61
62#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
63    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
64    SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */
65                   (3U << 11U*2U)  );         /* enable CP11 Full Access */
66
67    /* Set low-power state for PDEPU                */
68    /*  0b00  | ON, PDEPU is not in low-power state */
69    /*  0b01  | ON, but the clock is off            */
70    /*  0b10  | RET(ention)                         */
71    /*  0b11  | OFF                                 */
72
73    /* Clear ELPSTATE, value is 0b11 on Cold reset */
74    PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);
75
76    /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
77    /* PDEPU ON, Clock OFF */
78    PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
79#endif
80
81#ifdef UNALIGNED_SUPPORT_DISABLE
82    SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
83#endif
84
85    /* Enable Loop and branch info cache */
86    SCB->CCR |= SCB_CCR_LOB_Msk;
87    __DSB();
88    __ISB();
89
90
91    SystemCoreClock = SYSTEM_CLOCK;
92    PeripheralClock = PERIPHERAL_CLOCK;
93}
94