1 /* 2 * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Licensed under the Apache License, Version 2.0 (the License); you may 7 * not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 /* 20 * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c 21 * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b 22 */ 23 24 #include "SSE300MPS3.h" 25 26 /*---------------------------------------------------------------------------- 27 Define clocks 28 *----------------------------------------------------------------------------*/ 29 #define XTAL (32000000UL) 30 #define SYSTEM_CLOCK (XTAL) 31 #define PERIPHERAL_CLOCK (25000000UL) 32 33 /*---------------------------------------------------------------------------- 34 Externals 35 *----------------------------------------------------------------------------*/ 36 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 37 extern uint32_t __VECTOR_TABLE; 38 #endif 39 40 /*---------------------------------------------------------------------------- 41 System Core Clock Variable 42 *----------------------------------------------------------------------------*/ 43 uint32_t SystemCoreClock = SYSTEM_CLOCK; 44 uint32_t PeripheralClock = PERIPHERAL_CLOCK; 45 46 /*---------------------------------------------------------------------------- 47 System Core Clock update function 48 *----------------------------------------------------------------------------*/ SystemCoreClockUpdate(void)49void SystemCoreClockUpdate (void) 50 { 51 SystemCoreClock = SYSTEM_CLOCK; 52 PeripheralClock = PERIPHERAL_CLOCK; 53 } 54 55 /*---------------------------------------------------------------------------- 56 System initialization function 57 *----------------------------------------------------------------------------*/ SystemInit(void)58void SystemInit (void) 59 { 60 61 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 62 SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); 63 #endif 64 65 #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ 66 (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE >= 1U)) 67 SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ 68 (3U << 11U*2U) ); /* enable CP11 Full Access */ 69 70 /* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set 71 * CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU 72 * into retention state 73 */ 74 PWRMODCTL->CPDLPSTATE &= 0xFFFFFF00UL; 75 #endif 76 77 #ifdef UNALIGNED_SUPPORT_DISABLE 78 SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 79 #endif 80 81 /* Enable Loop and branch info cache */ 82 SCB->CCR |= SCB_CCR_LOB_Msk; 83 __DSB(); 84 __ISB(); 85 86 } 87
