1 /*
2  * Copyright (c) 2009-2022 Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Licensed under the Apache License, Version 2.0 (the License); you may
7  * not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  * www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  * See the License for the specific language governing permissions and
16  * limitations under the License.
17  */
18 
19 /*
20  * This file is derivative of CMSIS system_ARMCM85.c
21  * Git SHA: 61ad1303bc50450130cfb540caa384875a260b91
22  */
23 
24 #include "SSE310MPS3.h"
25 
26 /*----------------------------------------------------------------------------
27   Define clocks
28  *----------------------------------------------------------------------------*/
29  #define  XTAL             (32000000UL)
30  #define  SYSTEM_CLOCK     (XTAL)
31  #define  PERIPHERAL_CLOCK (25000000UL)
32 
33 /*----------------------------------------------------------------------------
34   Exception / Interrupt Vector table
35  *----------------------------------------------------------------------------*/
36 extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
37 
38 /*----------------------------------------------------------------------------
39   System Core Clock Variable
40  *----------------------------------------------------------------------------*/
41 uint32_t SystemCoreClock = SYSTEM_CLOCK;
42 uint32_t PeripheralClock = PERIPHERAL_CLOCK;
43 
44 /*----------------------------------------------------------------------------
45   System Core Clock update function
46  *----------------------------------------------------------------------------*/
SystemCoreClockUpdate(void)47 void SystemCoreClockUpdate (void)
48 {
49     SystemCoreClock = SYSTEM_CLOCK;
50     PeripheralClock = PERIPHERAL_CLOCK;
51 }
52 
53 /*----------------------------------------------------------------------------
54   System initialization function
55  *----------------------------------------------------------------------------*/
SystemInit(void)56 void SystemInit (void)
57 {
58 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
59     SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
60 #endif
61 
62     /* Set CPDLPSTATE.RLPSTATE to 0
63        Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state.
64        Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */
65     PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk |
66                                PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk |
67                                PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk  );
68 
69 #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
70     (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
71     SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */
72                    (3U << 11U*2U)  );         /* enable CP11 Full Access */
73 
74     /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
75     /* PDEPU ON, Clock OFF */
76     PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
77 #endif
78 
79 #ifdef UNALIGNED_SUPPORT_DISABLE
80     SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
81 #endif
82 
83     /* Enable Loop and branch info cache */
84     SCB->CCR |= SCB_CCR_LOB_Msk;
85 
86     /* Enable Branch Prediction */
87     SCB->CCR |= SCB_CCR_BP_Msk;
88 
89     __DSB();
90     __ISB();
91 }
92