1 /******************************************************************************
2  * @file     system_ARMCA7.c
3  * @brief    CMSIS Device System Source File for Arm Cortex-A7 Device Series
4  * @version  V1.0.1
5  * @date     13. February 2019
6  *
7  * @note
8  *
9  ******************************************************************************/
10 /*
11  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
12  *
13  * SPDX-License-Identifier: Apache-2.0
14  *
15  * Licensed under the Apache License, Version 2.0 (the License); you may
16  * not use this file except in compliance with the License.
17  * You may obtain a copy of the License at
18  *
19  * www.apache.org/licenses/LICENSE-2.0
20  *
21  * Unless required by applicable law or agreed to in writing, software
22  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
23  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24  * See the License for the specific language governing permissions and
25  * limitations under the License.
26  */
27 
28 #include "RTE_Components.h"
29 #include CMSIS_device_header
30 #include "irq_ctrl.h"
31 
32 #define  SYSTEM_CLOCK  12000000U
33 
34 /*----------------------------------------------------------------------------
35   System Core Clock Variable
36  *----------------------------------------------------------------------------*/
37 uint32_t SystemCoreClock = SYSTEM_CLOCK;
38 
39 /*----------------------------------------------------------------------------
40   System Core Clock update function
41  *----------------------------------------------------------------------------*/
SystemCoreClockUpdate(void)42 void SystemCoreClockUpdate (void)
43 {
44   SystemCoreClock = SYSTEM_CLOCK;
45 }
46 
47 /*----------------------------------------------------------------------------
48   System Initialization
49  *----------------------------------------------------------------------------*/
SystemInit(void)50 void SystemInit (void)
51 {
52 /* do not use global variables because this function is called before
53    reaching pre-main. RW section may be overwritten afterwards.          */
54 
55   // Invalidate entire Unified TLB
56   __set_TLBIALL(0);
57 
58   // Invalidate entire branch predictor array
59   __set_BPIALL(0);
60   __DSB();
61   __ISB();
62 
63   //  Invalidate instruction cache and flush branch target cache
64   __set_ICIALLU(0);
65   __DSB();
66   __ISB();
67 
68   //  Invalidate data cache
69   L1C_InvalidateDCacheAll();
70 
71 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
72   // Enable FPU
73   __FPU_Enable();
74 #endif
75 
76   // Create Translation Table
77   MMU_CreateTranslationTable();
78 
79   // Enable MMU
80   MMU_Enable();
81 
82   // Enable Caches
83   L1C_EnableCaches();
84   L1C_EnableBTAC();
85 
86 #if (__L2C_PRESENT == 1)
87   // Enable GIC
88   L2C_Enable();
89 #endif
90 
91   // IRQ Initialize
92   IRQ_Initialize();
93 }
94