Searched full:additional (Results 1 – 25 of 72) sorted by relevance
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81 …__O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Re…82 …__O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables …83 …__I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Regi…1092 /* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */1093 #define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */1094 #define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */1095 #define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */1096 #define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */1097 #define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */1098 #define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */[all …]
84 …WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register …85 …WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Registe…86 RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */1213 /* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */1214 #define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */1215 #define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */1216 #define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */1217 #define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */1218 #define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */1219 #define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */[all …]
84 …__O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable R…85 …__O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable …86 …__I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Reg…1211 /* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */1212 #define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */1213 #define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */1214 #define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */1215 #define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */1216 #define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */1217 #define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */[all …]
140 #define REG_PWM_CAE0 (0x40000404U) /**< \brief (PWM) PWM Channel Additional Edge Regis…141 #define REG_PWM_CAEUPD0 (0x40000408U) /**< \brief (PWM) PWM Channel Additional Edge Updat…143 #define REG_PWM_CAE1 (0x40000424U) /**< \brief (PWM) PWM Channel Additional Edge Regis…144 #define REG_PWM_CAEUPD1 (0x40000428U) /**< \brief (PWM) PWM Channel Additional Edge Updat…146 #define REG_PWM_CAE2 (0x40000444U) /**< \brief (PWM) PWM Channel Additional Edge Regis…147 #define REG_PWM_CAEUPD2 (0x40000448U) /**< \brief (PWM) PWM Channel Additional Edge Updat…149 #define REG_PWM_CAE3 (0x40000464U) /**< \brief (PWM) PWM Channel Additional Edge Regis…150 #define REG_PWM_CAEUPD3 (0x40000468U) /**< \brief (PWM) PWM Channel Additional Edge Updat…257 #define REG_PWM_CAE0 (*(RwReg*)0x40000404U) /**< \brief (PWM) PWM Channel Additional Edge Regis…258 #define REG_PWM_CAEUPD0 (*(WoReg*)0x40000408U) /**< \brief (PWM) PWM Channel Additional Edge Updat…[all …]
5053 /* -------- PIO_AIMER : (PIO Offset: 0xb0) (/W 32) Additional Interrupt Modes Enable Register -----…5058 … uint32_t P0:1; /**< bit: 0 Additional Interrupt Modes Enable */5059 … uint32_t P1:1; /**< bit: 1 Additional Interrupt Modes Enable */5060 … uint32_t P2:1; /**< bit: 2 Additional Interrupt Modes Enable */5061 … uint32_t P3:1; /**< bit: 3 Additional Interrupt Modes Enable */5062 … uint32_t P4:1; /**< bit: 4 Additional Interrupt Modes Enable */5063 … uint32_t P5:1; /**< bit: 5 Additional Interrupt Modes Enable */5064 … uint32_t P6:1; /**< bit: 6 Additional Interrupt Modes Enable */5065 … uint32_t P7:1; /**< bit: 7 Additional Interrupt Modes Enable */5066 … uint32_t P8:1; /**< bit: 8 Additional Interrupt Modes Enable */[all …]
66 …#define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Mod…67 …#define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Mod…68 …#define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Mod…110 …#define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Mod…111 …#define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Mod…112 …#define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Mod…
66 …#define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Mod…67 …#define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Mod…68 …#define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Mod…110 …#define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Mod…111 …#define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Mod…112 …#define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Mod…
66 …#define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Mod…67 …#define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Mod…68 …#define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Mod…110 …#define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Mod…111 …#define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Mod…112 …#define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Mod…
66 …#define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Mod…67 …#define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Mod…68 …#define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Mod…110 …#define REG_PIOD_AIMER (*(__O uint32_t*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Mod…111 …#define REG_PIOD_AIMDR (*(__O uint32_t*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Mod…112 …#define REG_PIOD_AIMMR (*(__I uint32_t*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Mod…
66 …#define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Mod…67 …#define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Mod…68 …#define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Mod…110 …#define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Mod…111 …#define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Mod…112 …#define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Mod…
66 …#define REG_PIOF_AIMER (0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Mod…67 …#define REG_PIOF_AIMDR (0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Mod…68 …#define REG_PIOF_AIMMR (0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Mod…110 …#define REG_PIOF_AIMER (*(__O uint32_t*)0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Mod…111 …#define REG_PIOF_AIMDR (*(__O uint32_t*)0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Mod…112 …#define REG_PIOF_AIMMR (*(__I uint32_t*)0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Mod…
73 #define REG_PIOA_AIMER (0x400E0EB0) /**< (PIOA) Additional Interrupt Modes Enable Register…74 #define REG_PIOA_AIMDR (0x400E0EB4) /**< (PIOA) Additional Interrupt Modes Disable Registe…75 #define REG_PIOA_AIMMR (0x400E0EB8) /**< (PIOA) Additional Interrupt Modes Mask Register */133 #define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< (PIOA) Additional Interrupt Mod…134 #define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< (PIOA) Additional Interrupt Mod…135 #define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< (PIOA) Additional Interrupt Mod…
73 #define REG_PIOB_AIMER (0x400E10B0) /**< (PIOB) Additional Interrupt Modes Enable Register…74 #define REG_PIOB_AIMDR (0x400E10B4) /**< (PIOB) Additional Interrupt Modes Disable Registe…75 #define REG_PIOB_AIMMR (0x400E10B8) /**< (PIOB) Additional Interrupt Modes Mask Register */133 #define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< (PIOB) Additional Interrupt Mod…134 #define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< (PIOB) Additional Interrupt Mod…135 #define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< (PIOB) Additional Interrupt Mod…
73 #define REG_PIOC_AIMER (0x400E12B0) /**< (PIOC) Additional Interrupt Modes Enable Register…74 #define REG_PIOC_AIMDR (0x400E12B4) /**< (PIOC) Additional Interrupt Modes Disable Registe…75 #define REG_PIOC_AIMMR (0x400E12B8) /**< (PIOC) Additional Interrupt Modes Mask Register */133 #define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< (PIOC) Additional Interrupt Mod…134 #define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< (PIOC) Additional Interrupt Mod…135 #define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< (PIOC) Additional Interrupt Mod…
73 #define REG_PIOD_AIMER (0x400E14B0) /**< (PIOD) Additional Interrupt Modes Enable Register…74 #define REG_PIOD_AIMDR (0x400E14B4) /**< (PIOD) Additional Interrupt Modes Disable Registe…75 #define REG_PIOD_AIMMR (0x400E14B8) /**< (PIOD) Additional Interrupt Modes Mask Register */133 #define REG_PIOD_AIMER (*(__O uint32_t*)0x400E14B0U) /**< (PIOD) Additional Interrupt Mod…134 #define REG_PIOD_AIMDR (*(__O uint32_t*)0x400E14B4U) /**< (PIOD) Additional Interrupt Mod…135 #define REG_PIOD_AIMMR (*(__I uint32_t*)0x400E14B8U) /**< (PIOD) Additional Interrupt Mod…
73 #define REG_PIOE_AIMER (0x400E16B0) /**< (PIOE) Additional Interrupt Modes Enable Register…74 #define REG_PIOE_AIMDR (0x400E16B4) /**< (PIOE) Additional Interrupt Modes Disable Registe…75 #define REG_PIOE_AIMMR (0x400E16B8) /**< (PIOE) Additional Interrupt Modes Mask Register */133 #define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< (PIOE) Additional Interrupt Mod…134 #define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< (PIOE) Additional Interrupt Mod…135 #define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< (PIOE) Additional Interrupt Mod…
73 #define REG_PIOA_AIMER (0x400E0EB0) /**< (PIOA) Additional Interrupt Modes Enable Register…74 #define REG_PIOA_AIMDR (0x400E0EB4) /**< (PIOA) Additional Interrupt Modes Disable Registe…75 #define REG_PIOA_AIMMR (0x400E0EB8) /**< (PIOA) Additional Interrupt Modes Mask Register */132 #define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< (PIOA) Additional Interrupt Mod…133 #define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< (PIOA) Additional Interrupt Mod…134 #define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< (PIOA) Additional Interrupt Mod…
73 #define REG_PIOB_AIMER (0x400E10B0) /**< (PIOB) Additional Interrupt Modes Enable Register…74 #define REG_PIOB_AIMDR (0x400E10B4) /**< (PIOB) Additional Interrupt Modes Disable Registe…75 #define REG_PIOB_AIMMR (0x400E10B8) /**< (PIOB) Additional Interrupt Modes Mask Register */132 #define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< (PIOB) Additional Interrupt Mod…133 #define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< (PIOB) Additional Interrupt Mod…134 #define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< (PIOB) Additional Interrupt Mod…
73 #define REG_PIOC_AIMER (0x400E12B0) /**< (PIOC) Additional Interrupt Modes Enable Register…74 #define REG_PIOC_AIMDR (0x400E12B4) /**< (PIOC) Additional Interrupt Modes Disable Registe…75 #define REG_PIOC_AIMMR (0x400E12B8) /**< (PIOC) Additional Interrupt Modes Mask Register */132 #define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< (PIOC) Additional Interrupt Mod…133 #define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< (PIOC) Additional Interrupt Mod…134 #define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< (PIOC) Additional Interrupt Mod…
73 #define REG_PIOD_AIMER (0x400E14B0) /**< (PIOD) Additional Interrupt Modes Enable Register…74 #define REG_PIOD_AIMDR (0x400E14B4) /**< (PIOD) Additional Interrupt Modes Disable Registe…75 #define REG_PIOD_AIMMR (0x400E14B8) /**< (PIOD) Additional Interrupt Modes Mask Register */132 #define REG_PIOD_AIMER (*(__O uint32_t*)0x400E14B0U) /**< (PIOD) Additional Interrupt Mod…133 #define REG_PIOD_AIMDR (*(__O uint32_t*)0x400E14B4U) /**< (PIOD) Additional Interrupt Mod…134 #define REG_PIOD_AIMMR (*(__I uint32_t*)0x400E14B8U) /**< (PIOD) Additional Interrupt Mod…
73 #define REG_PIOE_AIMER (0x400E16B0) /**< (PIOE) Additional Interrupt Modes Enable Register…74 #define REG_PIOE_AIMDR (0x400E16B4) /**< (PIOE) Additional Interrupt Modes Disable Registe…75 #define REG_PIOE_AIMMR (0x400E16B8) /**< (PIOE) Additional Interrupt Modes Mask Register */132 #define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< (PIOE) Additional Interrupt Mod…133 #define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< (PIOE) Additional Interrupt Mod…134 #define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< (PIOE) Additional Interrupt Mod…
