1 /** 2 * \file 3 * 4 * \brief Instance description for PIOE 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_PIOE_INSTANCE_H_ 32 #define _SAMV71_PIOE_INSTANCE_H_ 33 34 /* ========== Register definition for PIOE peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_PIOE_PER (0x400E1600) /**< (PIOE) PIO Enable Register */ 38 #define REG_PIOE_PDR (0x400E1604) /**< (PIOE) PIO Disable Register */ 39 #define REG_PIOE_PSR (0x400E1608) /**< (PIOE) PIO Status Register */ 40 #define REG_PIOE_OER (0x400E1610) /**< (PIOE) Output Enable Register */ 41 #define REG_PIOE_ODR (0x400E1614) /**< (PIOE) Output Disable Register */ 42 #define REG_PIOE_OSR (0x400E1618) /**< (PIOE) Output Status Register */ 43 #define REG_PIOE_IFER (0x400E1620) /**< (PIOE) Glitch Input Filter Enable Register */ 44 #define REG_PIOE_IFDR (0x400E1624) /**< (PIOE) Glitch Input Filter Disable Register */ 45 #define REG_PIOE_IFSR (0x400E1628) /**< (PIOE) Glitch Input Filter Status Register */ 46 #define REG_PIOE_SODR (0x400E1630) /**< (PIOE) Set Output Data Register */ 47 #define REG_PIOE_CODR (0x400E1634) /**< (PIOE) Clear Output Data Register */ 48 #define REG_PIOE_ODSR (0x400E1638) /**< (PIOE) Output Data Status Register */ 49 #define REG_PIOE_PDSR (0x400E163C) /**< (PIOE) Pin Data Status Register */ 50 #define REG_PIOE_IER (0x400E1640) /**< (PIOE) Interrupt Enable Register */ 51 #define REG_PIOE_IDR (0x400E1644) /**< (PIOE) Interrupt Disable Register */ 52 #define REG_PIOE_IMR (0x400E1648) /**< (PIOE) Interrupt Mask Register */ 53 #define REG_PIOE_ISR (0x400E164C) /**< (PIOE) Interrupt Status Register */ 54 #define REG_PIOE_MDER (0x400E1650) /**< (PIOE) Multi-driver Enable Register */ 55 #define REG_PIOE_MDDR (0x400E1654) /**< (PIOE) Multi-driver Disable Register */ 56 #define REG_PIOE_MDSR (0x400E1658) /**< (PIOE) Multi-driver Status Register */ 57 #define REG_PIOE_PUDR (0x400E1660) /**< (PIOE) Pull-up Disable Register */ 58 #define REG_PIOE_PUER (0x400E1664) /**< (PIOE) Pull-up Enable Register */ 59 #define REG_PIOE_PUSR (0x400E1668) /**< (PIOE) Pad Pull-up Status Register */ 60 #define REG_PIOE_ABCDSR (0x400E1670) /**< (PIOE) Peripheral ABCD Select Register 0 */ 61 #define REG_PIOE_ABCDSR0 (0x400E1670) /**< (PIOE) Peripheral ABCD Select Register 0 */ 62 #define REG_PIOE_ABCDSR1 (0x400E1674) /**< (PIOE) Peripheral ABCD Select Register 1 */ 63 #define REG_PIOE_IFSCDR (0x400E1680) /**< (PIOE) Input Filter Slow Clock Disable Register */ 64 #define REG_PIOE_IFSCER (0x400E1684) /**< (PIOE) Input Filter Slow Clock Enable Register */ 65 #define REG_PIOE_IFSCSR (0x400E1688) /**< (PIOE) Input Filter Slow Clock Status Register */ 66 #define REG_PIOE_SCDR (0x400E168C) /**< (PIOE) Slow Clock Divider Debouncing Register */ 67 #define REG_PIOE_PPDDR (0x400E1690) /**< (PIOE) Pad Pull-down Disable Register */ 68 #define REG_PIOE_PPDER (0x400E1694) /**< (PIOE) Pad Pull-down Enable Register */ 69 #define REG_PIOE_PPDSR (0x400E1698) /**< (PIOE) Pad Pull-down Status Register */ 70 #define REG_PIOE_OWER (0x400E16A0) /**< (PIOE) Output Write Enable */ 71 #define REG_PIOE_OWDR (0x400E16A4) /**< (PIOE) Output Write Disable */ 72 #define REG_PIOE_OWSR (0x400E16A8) /**< (PIOE) Output Write Status Register */ 73 #define REG_PIOE_AIMER (0x400E16B0) /**< (PIOE) Additional Interrupt Modes Enable Register */ 74 #define REG_PIOE_AIMDR (0x400E16B4) /**< (PIOE) Additional Interrupt Modes Disable Register */ 75 #define REG_PIOE_AIMMR (0x400E16B8) /**< (PIOE) Additional Interrupt Modes Mask Register */ 76 #define REG_PIOE_ESR (0x400E16C0) /**< (PIOE) Edge Select Register */ 77 #define REG_PIOE_LSR (0x400E16C4) /**< (PIOE) Level Select Register */ 78 #define REG_PIOE_ELSR (0x400E16C8) /**< (PIOE) Edge/Level Status Register */ 79 #define REG_PIOE_FELLSR (0x400E16D0) /**< (PIOE) Falling Edge/Low-Level Select Register */ 80 #define REG_PIOE_REHLSR (0x400E16D4) /**< (PIOE) Rising Edge/High-Level Select Register */ 81 #define REG_PIOE_FRLHSR (0x400E16D8) /**< (PIOE) Fall/Rise - Low/High Status Register */ 82 #define REG_PIOE_LOCKSR (0x400E16E0) /**< (PIOE) Lock Status */ 83 #define REG_PIOE_WPMR (0x400E16E4) /**< (PIOE) Write Protection Mode Register */ 84 #define REG_PIOE_WPSR (0x400E16E8) /**< (PIOE) Write Protection Status Register */ 85 #define REG_PIOE_VERSION (0x400E16FC) /**< (PIOE) Version Register */ 86 #define REG_PIOE_SCHMITT (0x400E1700) /**< (PIOE) Schmitt Trigger Register */ 87 #define REG_PIOE_DRIVER (0x400E1718) /**< (PIOE) I/O Drive Register */ 88 #define REG_PIOE_PCMR (0x400E1750) /**< (PIOE) Parallel Capture Mode Register */ 89 #define REG_PIOE_PCIER (0x400E1754) /**< (PIOE) Parallel Capture Interrupt Enable Register */ 90 #define REG_PIOE_PCIDR (0x400E1758) /**< (PIOE) Parallel Capture Interrupt Disable Register */ 91 #define REG_PIOE_PCIMR (0x400E175C) /**< (PIOE) Parallel Capture Interrupt Mask Register */ 92 #define REG_PIOE_PCISR (0x400E1760) /**< (PIOE) Parallel Capture Interrupt Status Register */ 93 #define REG_PIOE_PCRHR (0x400E1764) /**< (PIOE) Parallel Capture Reception Holding Register */ 94 95 #else 96 97 #define REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) /**< (PIOE) PIO Enable Register */ 98 #define REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) /**< (PIOE) PIO Disable Register */ 99 #define REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) /**< (PIOE) PIO Status Register */ 100 #define REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) /**< (PIOE) Output Enable Register */ 101 #define REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) /**< (PIOE) Output Disable Register */ 102 #define REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) /**< (PIOE) Output Status Register */ 103 #define REG_PIOE_IFER (*(__O uint32_t*)0x400E1620U) /**< (PIOE) Glitch Input Filter Enable Register */ 104 #define REG_PIOE_IFDR (*(__O uint32_t*)0x400E1624U) /**< (PIOE) Glitch Input Filter Disable Register */ 105 #define REG_PIOE_IFSR (*(__I uint32_t*)0x400E1628U) /**< (PIOE) Glitch Input Filter Status Register */ 106 #define REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) /**< (PIOE) Set Output Data Register */ 107 #define REG_PIOE_CODR (*(__O uint32_t*)0x400E1634U) /**< (PIOE) Clear Output Data Register */ 108 #define REG_PIOE_ODSR (*(__IO uint32_t*)0x400E1638U) /**< (PIOE) Output Data Status Register */ 109 #define REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) /**< (PIOE) Pin Data Status Register */ 110 #define REG_PIOE_IER (*(__O uint32_t*)0x400E1640U) /**< (PIOE) Interrupt Enable Register */ 111 #define REG_PIOE_IDR (*(__O uint32_t*)0x400E1644U) /**< (PIOE) Interrupt Disable Register */ 112 #define REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) /**< (PIOE) Interrupt Mask Register */ 113 #define REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) /**< (PIOE) Interrupt Status Register */ 114 #define REG_PIOE_MDER (*(__O uint32_t*)0x400E1650U) /**< (PIOE) Multi-driver Enable Register */ 115 #define REG_PIOE_MDDR (*(__O uint32_t*)0x400E1654U) /**< (PIOE) Multi-driver Disable Register */ 116 #define REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) /**< (PIOE) Multi-driver Status Register */ 117 #define REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) /**< (PIOE) Pull-up Disable Register */ 118 #define REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) /**< (PIOE) Pull-up Enable Register */ 119 #define REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) /**< (PIOE) Pad Pull-up Status Register */ 120 #define REG_PIOE_ABCDSR (*(__IO uint32_t*)0x400E1670U) /**< (PIOE) Peripheral ABCD Select Register 0 */ 121 #define REG_PIOE_ABCDSR0 (*(__IO uint32_t*)0x400E1670U) /**< (PIOE) Peripheral ABCD Select Register 0 */ 122 #define REG_PIOE_ABCDSR1 (*(__IO uint32_t*)0x400E1674U) /**< (PIOE) Peripheral ABCD Select Register 1 */ 123 #define REG_PIOE_IFSCDR (*(__O uint32_t*)0x400E1680U) /**< (PIOE) Input Filter Slow Clock Disable Register */ 124 #define REG_PIOE_IFSCER (*(__O uint32_t*)0x400E1684U) /**< (PIOE) Input Filter Slow Clock Enable Register */ 125 #define REG_PIOE_IFSCSR (*(__I uint32_t*)0x400E1688U) /**< (PIOE) Input Filter Slow Clock Status Register */ 126 #define REG_PIOE_SCDR (*(__IO uint32_t*)0x400E168CU) /**< (PIOE) Slow Clock Divider Debouncing Register */ 127 #define REG_PIOE_PPDDR (*(__O uint32_t*)0x400E1690U) /**< (PIOE) Pad Pull-down Disable Register */ 128 #define REG_PIOE_PPDER (*(__O uint32_t*)0x400E1694U) /**< (PIOE) Pad Pull-down Enable Register */ 129 #define REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) /**< (PIOE) Pad Pull-down Status Register */ 130 #define REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) /**< (PIOE) Output Write Enable */ 131 #define REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) /**< (PIOE) Output Write Disable */ 132 #define REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) /**< (PIOE) Output Write Status Register */ 133 #define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< (PIOE) Additional Interrupt Modes Enable Register */ 134 #define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< (PIOE) Additional Interrupt Modes Disable Register */ 135 #define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< (PIOE) Additional Interrupt Modes Mask Register */ 136 #define REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) /**< (PIOE) Edge Select Register */ 137 #define REG_PIOE_LSR (*(__O uint32_t*)0x400E16C4U) /**< (PIOE) Level Select Register */ 138 #define REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) /**< (PIOE) Edge/Level Status Register */ 139 #define REG_PIOE_FELLSR (*(__O uint32_t*)0x400E16D0U) /**< (PIOE) Falling Edge/Low-Level Select Register */ 140 #define REG_PIOE_REHLSR (*(__O uint32_t*)0x400E16D4U) /**< (PIOE) Rising Edge/High-Level Select Register */ 141 #define REG_PIOE_FRLHSR (*(__I uint32_t*)0x400E16D8U) /**< (PIOE) Fall/Rise - Low/High Status Register */ 142 #define REG_PIOE_LOCKSR (*(__I uint32_t*)0x400E16E0U) /**< (PIOE) Lock Status */ 143 #define REG_PIOE_WPMR (*(__IO uint32_t*)0x400E16E4U) /**< (PIOE) Write Protection Mode Register */ 144 #define REG_PIOE_WPSR (*(__I uint32_t*)0x400E16E8U) /**< (PIOE) Write Protection Status Register */ 145 #define REG_PIOE_VERSION (*(__I uint32_t*)0x400E16FCU) /**< (PIOE) Version Register */ 146 #define REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) /**< (PIOE) Schmitt Trigger Register */ 147 #define REG_PIOE_DRIVER (*(__IO uint32_t*)0x400E1718U) /**< (PIOE) I/O Drive Register */ 148 #define REG_PIOE_PCMR (*(__IO uint32_t*)0x400E1750U) /**< (PIOE) Parallel Capture Mode Register */ 149 #define REG_PIOE_PCIER (*(__O uint32_t*)0x400E1754U) /**< (PIOE) Parallel Capture Interrupt Enable Register */ 150 #define REG_PIOE_PCIDR (*(__O uint32_t*)0x400E1758U) /**< (PIOE) Parallel Capture Interrupt Disable Register */ 151 #define REG_PIOE_PCIMR (*(__I uint32_t*)0x400E175CU) /**< (PIOE) Parallel Capture Interrupt Mask Register */ 152 #define REG_PIOE_PCISR (*(__I uint32_t*)0x400E1760U) /**< (PIOE) Parallel Capture Interrupt Status Register */ 153 #define REG_PIOE_PCRHR (*(__I uint32_t*)0x400E1764U) /**< (PIOE) Parallel Capture Reception Holding Register */ 154 155 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 156 157 /* ========== Instance Parameter definitions for PIOE peripheral ========== */ 158 #define PIOE_INSTANCE_ID 17 159 160 #endif /* _SAMV71_PIOE_INSTANCE_ */ 161
