1 /** 2 * \file 3 * 4 * \brief Component description for PIO 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_PIO_COMPONENT_H_ 32 #define _SAMV71_PIO_COMPONENT_H_ 33 #define _SAMV71_PIO_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Parallel Input/Output Controller 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR PIO */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define PIO_11004 /**< (PIO) Module ID */ 46 #define REV_PIO V /**< (PIO) Module revision */ 47 48 /* -------- PIO_PER : (PIO Offset: 0x00) (/W 32) PIO Enable Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t P0:1; /**< bit: 0 PIO Enable */ 54 uint32_t P1:1; /**< bit: 1 PIO Enable */ 55 uint32_t P2:1; /**< bit: 2 PIO Enable */ 56 uint32_t P3:1; /**< bit: 3 PIO Enable */ 57 uint32_t P4:1; /**< bit: 4 PIO Enable */ 58 uint32_t P5:1; /**< bit: 5 PIO Enable */ 59 uint32_t P6:1; /**< bit: 6 PIO Enable */ 60 uint32_t P7:1; /**< bit: 7 PIO Enable */ 61 uint32_t P8:1; /**< bit: 8 PIO Enable */ 62 uint32_t P9:1; /**< bit: 9 PIO Enable */ 63 uint32_t P10:1; /**< bit: 10 PIO Enable */ 64 uint32_t P11:1; /**< bit: 11 PIO Enable */ 65 uint32_t P12:1; /**< bit: 12 PIO Enable */ 66 uint32_t P13:1; /**< bit: 13 PIO Enable */ 67 uint32_t P14:1; /**< bit: 14 PIO Enable */ 68 uint32_t P15:1; /**< bit: 15 PIO Enable */ 69 uint32_t P16:1; /**< bit: 16 PIO Enable */ 70 uint32_t P17:1; /**< bit: 17 PIO Enable */ 71 uint32_t P18:1; /**< bit: 18 PIO Enable */ 72 uint32_t P19:1; /**< bit: 19 PIO Enable */ 73 uint32_t P20:1; /**< bit: 20 PIO Enable */ 74 uint32_t P21:1; /**< bit: 21 PIO Enable */ 75 uint32_t P22:1; /**< bit: 22 PIO Enable */ 76 uint32_t P23:1; /**< bit: 23 PIO Enable */ 77 uint32_t P24:1; /**< bit: 24 PIO Enable */ 78 uint32_t P25:1; /**< bit: 25 PIO Enable */ 79 uint32_t P26:1; /**< bit: 26 PIO Enable */ 80 uint32_t P27:1; /**< bit: 27 PIO Enable */ 81 uint32_t P28:1; /**< bit: 28 PIO Enable */ 82 uint32_t P29:1; /**< bit: 29 PIO Enable */ 83 uint32_t P30:1; /**< bit: 30 PIO Enable */ 84 uint32_t P31:1; /**< bit: 31 PIO Enable */ 85 } bit; /**< Structure used for bit access */ 86 struct { 87 uint32_t P:32; /**< bit: 0..31 PIO Enable */ 88 } vec; /**< Structure used for vec access */ 89 uint32_t reg; /**< Type used for register access */ 90 } PIO_PER_Type; 91 #endif 92 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 93 94 #define PIO_PER_OFFSET (0x00) /**< (PIO_PER) PIO Enable Register Offset */ 95 96 #define PIO_PER_P0_Pos 0 /**< (PIO_PER) PIO Enable Position */ 97 #define PIO_PER_P0_Msk (_U_(0x1) << PIO_PER_P0_Pos) /**< (PIO_PER) PIO Enable Mask */ 98 #define PIO_PER_P0 PIO_PER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P0_Msk instead */ 99 #define PIO_PER_P1_Pos 1 /**< (PIO_PER) PIO Enable Position */ 100 #define PIO_PER_P1_Msk (_U_(0x1) << PIO_PER_P1_Pos) /**< (PIO_PER) PIO Enable Mask */ 101 #define PIO_PER_P1 PIO_PER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P1_Msk instead */ 102 #define PIO_PER_P2_Pos 2 /**< (PIO_PER) PIO Enable Position */ 103 #define PIO_PER_P2_Msk (_U_(0x1) << PIO_PER_P2_Pos) /**< (PIO_PER) PIO Enable Mask */ 104 #define PIO_PER_P2 PIO_PER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P2_Msk instead */ 105 #define PIO_PER_P3_Pos 3 /**< (PIO_PER) PIO Enable Position */ 106 #define PIO_PER_P3_Msk (_U_(0x1) << PIO_PER_P3_Pos) /**< (PIO_PER) PIO Enable Mask */ 107 #define PIO_PER_P3 PIO_PER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P3_Msk instead */ 108 #define PIO_PER_P4_Pos 4 /**< (PIO_PER) PIO Enable Position */ 109 #define PIO_PER_P4_Msk (_U_(0x1) << PIO_PER_P4_Pos) /**< (PIO_PER) PIO Enable Mask */ 110 #define PIO_PER_P4 PIO_PER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P4_Msk instead */ 111 #define PIO_PER_P5_Pos 5 /**< (PIO_PER) PIO Enable Position */ 112 #define PIO_PER_P5_Msk (_U_(0x1) << PIO_PER_P5_Pos) /**< (PIO_PER) PIO Enable Mask */ 113 #define PIO_PER_P5 PIO_PER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P5_Msk instead */ 114 #define PIO_PER_P6_Pos 6 /**< (PIO_PER) PIO Enable Position */ 115 #define PIO_PER_P6_Msk (_U_(0x1) << PIO_PER_P6_Pos) /**< (PIO_PER) PIO Enable Mask */ 116 #define PIO_PER_P6 PIO_PER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P6_Msk instead */ 117 #define PIO_PER_P7_Pos 7 /**< (PIO_PER) PIO Enable Position */ 118 #define PIO_PER_P7_Msk (_U_(0x1) << PIO_PER_P7_Pos) /**< (PIO_PER) PIO Enable Mask */ 119 #define PIO_PER_P7 PIO_PER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P7_Msk instead */ 120 #define PIO_PER_P8_Pos 8 /**< (PIO_PER) PIO Enable Position */ 121 #define PIO_PER_P8_Msk (_U_(0x1) << PIO_PER_P8_Pos) /**< (PIO_PER) PIO Enable Mask */ 122 #define PIO_PER_P8 PIO_PER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P8_Msk instead */ 123 #define PIO_PER_P9_Pos 9 /**< (PIO_PER) PIO Enable Position */ 124 #define PIO_PER_P9_Msk (_U_(0x1) << PIO_PER_P9_Pos) /**< (PIO_PER) PIO Enable Mask */ 125 #define PIO_PER_P9 PIO_PER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P9_Msk instead */ 126 #define PIO_PER_P10_Pos 10 /**< (PIO_PER) PIO Enable Position */ 127 #define PIO_PER_P10_Msk (_U_(0x1) << PIO_PER_P10_Pos) /**< (PIO_PER) PIO Enable Mask */ 128 #define PIO_PER_P10 PIO_PER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P10_Msk instead */ 129 #define PIO_PER_P11_Pos 11 /**< (PIO_PER) PIO Enable Position */ 130 #define PIO_PER_P11_Msk (_U_(0x1) << PIO_PER_P11_Pos) /**< (PIO_PER) PIO Enable Mask */ 131 #define PIO_PER_P11 PIO_PER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P11_Msk instead */ 132 #define PIO_PER_P12_Pos 12 /**< (PIO_PER) PIO Enable Position */ 133 #define PIO_PER_P12_Msk (_U_(0x1) << PIO_PER_P12_Pos) /**< (PIO_PER) PIO Enable Mask */ 134 #define PIO_PER_P12 PIO_PER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P12_Msk instead */ 135 #define PIO_PER_P13_Pos 13 /**< (PIO_PER) PIO Enable Position */ 136 #define PIO_PER_P13_Msk (_U_(0x1) << PIO_PER_P13_Pos) /**< (PIO_PER) PIO Enable Mask */ 137 #define PIO_PER_P13 PIO_PER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P13_Msk instead */ 138 #define PIO_PER_P14_Pos 14 /**< (PIO_PER) PIO Enable Position */ 139 #define PIO_PER_P14_Msk (_U_(0x1) << PIO_PER_P14_Pos) /**< (PIO_PER) PIO Enable Mask */ 140 #define PIO_PER_P14 PIO_PER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P14_Msk instead */ 141 #define PIO_PER_P15_Pos 15 /**< (PIO_PER) PIO Enable Position */ 142 #define PIO_PER_P15_Msk (_U_(0x1) << PIO_PER_P15_Pos) /**< (PIO_PER) PIO Enable Mask */ 143 #define PIO_PER_P15 PIO_PER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P15_Msk instead */ 144 #define PIO_PER_P16_Pos 16 /**< (PIO_PER) PIO Enable Position */ 145 #define PIO_PER_P16_Msk (_U_(0x1) << PIO_PER_P16_Pos) /**< (PIO_PER) PIO Enable Mask */ 146 #define PIO_PER_P16 PIO_PER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P16_Msk instead */ 147 #define PIO_PER_P17_Pos 17 /**< (PIO_PER) PIO Enable Position */ 148 #define PIO_PER_P17_Msk (_U_(0x1) << PIO_PER_P17_Pos) /**< (PIO_PER) PIO Enable Mask */ 149 #define PIO_PER_P17 PIO_PER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P17_Msk instead */ 150 #define PIO_PER_P18_Pos 18 /**< (PIO_PER) PIO Enable Position */ 151 #define PIO_PER_P18_Msk (_U_(0x1) << PIO_PER_P18_Pos) /**< (PIO_PER) PIO Enable Mask */ 152 #define PIO_PER_P18 PIO_PER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P18_Msk instead */ 153 #define PIO_PER_P19_Pos 19 /**< (PIO_PER) PIO Enable Position */ 154 #define PIO_PER_P19_Msk (_U_(0x1) << PIO_PER_P19_Pos) /**< (PIO_PER) PIO Enable Mask */ 155 #define PIO_PER_P19 PIO_PER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P19_Msk instead */ 156 #define PIO_PER_P20_Pos 20 /**< (PIO_PER) PIO Enable Position */ 157 #define PIO_PER_P20_Msk (_U_(0x1) << PIO_PER_P20_Pos) /**< (PIO_PER) PIO Enable Mask */ 158 #define PIO_PER_P20 PIO_PER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P20_Msk instead */ 159 #define PIO_PER_P21_Pos 21 /**< (PIO_PER) PIO Enable Position */ 160 #define PIO_PER_P21_Msk (_U_(0x1) << PIO_PER_P21_Pos) /**< (PIO_PER) PIO Enable Mask */ 161 #define PIO_PER_P21 PIO_PER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P21_Msk instead */ 162 #define PIO_PER_P22_Pos 22 /**< (PIO_PER) PIO Enable Position */ 163 #define PIO_PER_P22_Msk (_U_(0x1) << PIO_PER_P22_Pos) /**< (PIO_PER) PIO Enable Mask */ 164 #define PIO_PER_P22 PIO_PER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P22_Msk instead */ 165 #define PIO_PER_P23_Pos 23 /**< (PIO_PER) PIO Enable Position */ 166 #define PIO_PER_P23_Msk (_U_(0x1) << PIO_PER_P23_Pos) /**< (PIO_PER) PIO Enable Mask */ 167 #define PIO_PER_P23 PIO_PER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P23_Msk instead */ 168 #define PIO_PER_P24_Pos 24 /**< (PIO_PER) PIO Enable Position */ 169 #define PIO_PER_P24_Msk (_U_(0x1) << PIO_PER_P24_Pos) /**< (PIO_PER) PIO Enable Mask */ 170 #define PIO_PER_P24 PIO_PER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P24_Msk instead */ 171 #define PIO_PER_P25_Pos 25 /**< (PIO_PER) PIO Enable Position */ 172 #define PIO_PER_P25_Msk (_U_(0x1) << PIO_PER_P25_Pos) /**< (PIO_PER) PIO Enable Mask */ 173 #define PIO_PER_P25 PIO_PER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P25_Msk instead */ 174 #define PIO_PER_P26_Pos 26 /**< (PIO_PER) PIO Enable Position */ 175 #define PIO_PER_P26_Msk (_U_(0x1) << PIO_PER_P26_Pos) /**< (PIO_PER) PIO Enable Mask */ 176 #define PIO_PER_P26 PIO_PER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P26_Msk instead */ 177 #define PIO_PER_P27_Pos 27 /**< (PIO_PER) PIO Enable Position */ 178 #define PIO_PER_P27_Msk (_U_(0x1) << PIO_PER_P27_Pos) /**< (PIO_PER) PIO Enable Mask */ 179 #define PIO_PER_P27 PIO_PER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P27_Msk instead */ 180 #define PIO_PER_P28_Pos 28 /**< (PIO_PER) PIO Enable Position */ 181 #define PIO_PER_P28_Msk (_U_(0x1) << PIO_PER_P28_Pos) /**< (PIO_PER) PIO Enable Mask */ 182 #define PIO_PER_P28 PIO_PER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P28_Msk instead */ 183 #define PIO_PER_P29_Pos 29 /**< (PIO_PER) PIO Enable Position */ 184 #define PIO_PER_P29_Msk (_U_(0x1) << PIO_PER_P29_Pos) /**< (PIO_PER) PIO Enable Mask */ 185 #define PIO_PER_P29 PIO_PER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P29_Msk instead */ 186 #define PIO_PER_P30_Pos 30 /**< (PIO_PER) PIO Enable Position */ 187 #define PIO_PER_P30_Msk (_U_(0x1) << PIO_PER_P30_Pos) /**< (PIO_PER) PIO Enable Mask */ 188 #define PIO_PER_P30 PIO_PER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P30_Msk instead */ 189 #define PIO_PER_P31_Pos 31 /**< (PIO_PER) PIO Enable Position */ 190 #define PIO_PER_P31_Msk (_U_(0x1) << PIO_PER_P31_Pos) /**< (PIO_PER) PIO Enable Mask */ 191 #define PIO_PER_P31 PIO_PER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P31_Msk instead */ 192 #define PIO_PER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PER) Register MASK (Use PIO_PER_Msk instead) */ 193 #define PIO_PER_Msk _U_(0xFFFFFFFF) /**< (PIO_PER) Register Mask */ 194 195 #define PIO_PER_P_Pos 0 /**< (PIO_PER Position) PIO Enable */ 196 #define PIO_PER_P_Msk (_U_(0xFFFFFFFF) << PIO_PER_P_Pos) /**< (PIO_PER Mask) P */ 197 #define PIO_PER_P(value) (PIO_PER_P_Msk & ((value) << PIO_PER_P_Pos)) 198 199 /* -------- PIO_PDR : (PIO Offset: 0x04) (/W 32) PIO Disable Register -------- */ 200 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 201 #if COMPONENT_TYPEDEF_STYLE == 'N' 202 typedef union { 203 struct { 204 uint32_t P0:1; /**< bit: 0 PIO Disable */ 205 uint32_t P1:1; /**< bit: 1 PIO Disable */ 206 uint32_t P2:1; /**< bit: 2 PIO Disable */ 207 uint32_t P3:1; /**< bit: 3 PIO Disable */ 208 uint32_t P4:1; /**< bit: 4 PIO Disable */ 209 uint32_t P5:1; /**< bit: 5 PIO Disable */ 210 uint32_t P6:1; /**< bit: 6 PIO Disable */ 211 uint32_t P7:1; /**< bit: 7 PIO Disable */ 212 uint32_t P8:1; /**< bit: 8 PIO Disable */ 213 uint32_t P9:1; /**< bit: 9 PIO Disable */ 214 uint32_t P10:1; /**< bit: 10 PIO Disable */ 215 uint32_t P11:1; /**< bit: 11 PIO Disable */ 216 uint32_t P12:1; /**< bit: 12 PIO Disable */ 217 uint32_t P13:1; /**< bit: 13 PIO Disable */ 218 uint32_t P14:1; /**< bit: 14 PIO Disable */ 219 uint32_t P15:1; /**< bit: 15 PIO Disable */ 220 uint32_t P16:1; /**< bit: 16 PIO Disable */ 221 uint32_t P17:1; /**< bit: 17 PIO Disable */ 222 uint32_t P18:1; /**< bit: 18 PIO Disable */ 223 uint32_t P19:1; /**< bit: 19 PIO Disable */ 224 uint32_t P20:1; /**< bit: 20 PIO Disable */ 225 uint32_t P21:1; /**< bit: 21 PIO Disable */ 226 uint32_t P22:1; /**< bit: 22 PIO Disable */ 227 uint32_t P23:1; /**< bit: 23 PIO Disable */ 228 uint32_t P24:1; /**< bit: 24 PIO Disable */ 229 uint32_t P25:1; /**< bit: 25 PIO Disable */ 230 uint32_t P26:1; /**< bit: 26 PIO Disable */ 231 uint32_t P27:1; /**< bit: 27 PIO Disable */ 232 uint32_t P28:1; /**< bit: 28 PIO Disable */ 233 uint32_t P29:1; /**< bit: 29 PIO Disable */ 234 uint32_t P30:1; /**< bit: 30 PIO Disable */ 235 uint32_t P31:1; /**< bit: 31 PIO Disable */ 236 } bit; /**< Structure used for bit access */ 237 struct { 238 uint32_t P:32; /**< bit: 0..31 PIO Disable */ 239 } vec; /**< Structure used for vec access */ 240 uint32_t reg; /**< Type used for register access */ 241 } PIO_PDR_Type; 242 #endif 243 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 244 245 #define PIO_PDR_OFFSET (0x04) /**< (PIO_PDR) PIO Disable Register Offset */ 246 247 #define PIO_PDR_P0_Pos 0 /**< (PIO_PDR) PIO Disable Position */ 248 #define PIO_PDR_P0_Msk (_U_(0x1) << PIO_PDR_P0_Pos) /**< (PIO_PDR) PIO Disable Mask */ 249 #define PIO_PDR_P0 PIO_PDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P0_Msk instead */ 250 #define PIO_PDR_P1_Pos 1 /**< (PIO_PDR) PIO Disable Position */ 251 #define PIO_PDR_P1_Msk (_U_(0x1) << PIO_PDR_P1_Pos) /**< (PIO_PDR) PIO Disable Mask */ 252 #define PIO_PDR_P1 PIO_PDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P1_Msk instead */ 253 #define PIO_PDR_P2_Pos 2 /**< (PIO_PDR) PIO Disable Position */ 254 #define PIO_PDR_P2_Msk (_U_(0x1) << PIO_PDR_P2_Pos) /**< (PIO_PDR) PIO Disable Mask */ 255 #define PIO_PDR_P2 PIO_PDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P2_Msk instead */ 256 #define PIO_PDR_P3_Pos 3 /**< (PIO_PDR) PIO Disable Position */ 257 #define PIO_PDR_P3_Msk (_U_(0x1) << PIO_PDR_P3_Pos) /**< (PIO_PDR) PIO Disable Mask */ 258 #define PIO_PDR_P3 PIO_PDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P3_Msk instead */ 259 #define PIO_PDR_P4_Pos 4 /**< (PIO_PDR) PIO Disable Position */ 260 #define PIO_PDR_P4_Msk (_U_(0x1) << PIO_PDR_P4_Pos) /**< (PIO_PDR) PIO Disable Mask */ 261 #define PIO_PDR_P4 PIO_PDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P4_Msk instead */ 262 #define PIO_PDR_P5_Pos 5 /**< (PIO_PDR) PIO Disable Position */ 263 #define PIO_PDR_P5_Msk (_U_(0x1) << PIO_PDR_P5_Pos) /**< (PIO_PDR) PIO Disable Mask */ 264 #define PIO_PDR_P5 PIO_PDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P5_Msk instead */ 265 #define PIO_PDR_P6_Pos 6 /**< (PIO_PDR) PIO Disable Position */ 266 #define PIO_PDR_P6_Msk (_U_(0x1) << PIO_PDR_P6_Pos) /**< (PIO_PDR) PIO Disable Mask */ 267 #define PIO_PDR_P6 PIO_PDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P6_Msk instead */ 268 #define PIO_PDR_P7_Pos 7 /**< (PIO_PDR) PIO Disable Position */ 269 #define PIO_PDR_P7_Msk (_U_(0x1) << PIO_PDR_P7_Pos) /**< (PIO_PDR) PIO Disable Mask */ 270 #define PIO_PDR_P7 PIO_PDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P7_Msk instead */ 271 #define PIO_PDR_P8_Pos 8 /**< (PIO_PDR) PIO Disable Position */ 272 #define PIO_PDR_P8_Msk (_U_(0x1) << PIO_PDR_P8_Pos) /**< (PIO_PDR) PIO Disable Mask */ 273 #define PIO_PDR_P8 PIO_PDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P8_Msk instead */ 274 #define PIO_PDR_P9_Pos 9 /**< (PIO_PDR) PIO Disable Position */ 275 #define PIO_PDR_P9_Msk (_U_(0x1) << PIO_PDR_P9_Pos) /**< (PIO_PDR) PIO Disable Mask */ 276 #define PIO_PDR_P9 PIO_PDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P9_Msk instead */ 277 #define PIO_PDR_P10_Pos 10 /**< (PIO_PDR) PIO Disable Position */ 278 #define PIO_PDR_P10_Msk (_U_(0x1) << PIO_PDR_P10_Pos) /**< (PIO_PDR) PIO Disable Mask */ 279 #define PIO_PDR_P10 PIO_PDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P10_Msk instead */ 280 #define PIO_PDR_P11_Pos 11 /**< (PIO_PDR) PIO Disable Position */ 281 #define PIO_PDR_P11_Msk (_U_(0x1) << PIO_PDR_P11_Pos) /**< (PIO_PDR) PIO Disable Mask */ 282 #define PIO_PDR_P11 PIO_PDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P11_Msk instead */ 283 #define PIO_PDR_P12_Pos 12 /**< (PIO_PDR) PIO Disable Position */ 284 #define PIO_PDR_P12_Msk (_U_(0x1) << PIO_PDR_P12_Pos) /**< (PIO_PDR) PIO Disable Mask */ 285 #define PIO_PDR_P12 PIO_PDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P12_Msk instead */ 286 #define PIO_PDR_P13_Pos 13 /**< (PIO_PDR) PIO Disable Position */ 287 #define PIO_PDR_P13_Msk (_U_(0x1) << PIO_PDR_P13_Pos) /**< (PIO_PDR) PIO Disable Mask */ 288 #define PIO_PDR_P13 PIO_PDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P13_Msk instead */ 289 #define PIO_PDR_P14_Pos 14 /**< (PIO_PDR) PIO Disable Position */ 290 #define PIO_PDR_P14_Msk (_U_(0x1) << PIO_PDR_P14_Pos) /**< (PIO_PDR) PIO Disable Mask */ 291 #define PIO_PDR_P14 PIO_PDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P14_Msk instead */ 292 #define PIO_PDR_P15_Pos 15 /**< (PIO_PDR) PIO Disable Position */ 293 #define PIO_PDR_P15_Msk (_U_(0x1) << PIO_PDR_P15_Pos) /**< (PIO_PDR) PIO Disable Mask */ 294 #define PIO_PDR_P15 PIO_PDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P15_Msk instead */ 295 #define PIO_PDR_P16_Pos 16 /**< (PIO_PDR) PIO Disable Position */ 296 #define PIO_PDR_P16_Msk (_U_(0x1) << PIO_PDR_P16_Pos) /**< (PIO_PDR) PIO Disable Mask */ 297 #define PIO_PDR_P16 PIO_PDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P16_Msk instead */ 298 #define PIO_PDR_P17_Pos 17 /**< (PIO_PDR) PIO Disable Position */ 299 #define PIO_PDR_P17_Msk (_U_(0x1) << PIO_PDR_P17_Pos) /**< (PIO_PDR) PIO Disable Mask */ 300 #define PIO_PDR_P17 PIO_PDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P17_Msk instead */ 301 #define PIO_PDR_P18_Pos 18 /**< (PIO_PDR) PIO Disable Position */ 302 #define PIO_PDR_P18_Msk (_U_(0x1) << PIO_PDR_P18_Pos) /**< (PIO_PDR) PIO Disable Mask */ 303 #define PIO_PDR_P18 PIO_PDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P18_Msk instead */ 304 #define PIO_PDR_P19_Pos 19 /**< (PIO_PDR) PIO Disable Position */ 305 #define PIO_PDR_P19_Msk (_U_(0x1) << PIO_PDR_P19_Pos) /**< (PIO_PDR) PIO Disable Mask */ 306 #define PIO_PDR_P19 PIO_PDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P19_Msk instead */ 307 #define PIO_PDR_P20_Pos 20 /**< (PIO_PDR) PIO Disable Position */ 308 #define PIO_PDR_P20_Msk (_U_(0x1) << PIO_PDR_P20_Pos) /**< (PIO_PDR) PIO Disable Mask */ 309 #define PIO_PDR_P20 PIO_PDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P20_Msk instead */ 310 #define PIO_PDR_P21_Pos 21 /**< (PIO_PDR) PIO Disable Position */ 311 #define PIO_PDR_P21_Msk (_U_(0x1) << PIO_PDR_P21_Pos) /**< (PIO_PDR) PIO Disable Mask */ 312 #define PIO_PDR_P21 PIO_PDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P21_Msk instead */ 313 #define PIO_PDR_P22_Pos 22 /**< (PIO_PDR) PIO Disable Position */ 314 #define PIO_PDR_P22_Msk (_U_(0x1) << PIO_PDR_P22_Pos) /**< (PIO_PDR) PIO Disable Mask */ 315 #define PIO_PDR_P22 PIO_PDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P22_Msk instead */ 316 #define PIO_PDR_P23_Pos 23 /**< (PIO_PDR) PIO Disable Position */ 317 #define PIO_PDR_P23_Msk (_U_(0x1) << PIO_PDR_P23_Pos) /**< (PIO_PDR) PIO Disable Mask */ 318 #define PIO_PDR_P23 PIO_PDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P23_Msk instead */ 319 #define PIO_PDR_P24_Pos 24 /**< (PIO_PDR) PIO Disable Position */ 320 #define PIO_PDR_P24_Msk (_U_(0x1) << PIO_PDR_P24_Pos) /**< (PIO_PDR) PIO Disable Mask */ 321 #define PIO_PDR_P24 PIO_PDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P24_Msk instead */ 322 #define PIO_PDR_P25_Pos 25 /**< (PIO_PDR) PIO Disable Position */ 323 #define PIO_PDR_P25_Msk (_U_(0x1) << PIO_PDR_P25_Pos) /**< (PIO_PDR) PIO Disable Mask */ 324 #define PIO_PDR_P25 PIO_PDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P25_Msk instead */ 325 #define PIO_PDR_P26_Pos 26 /**< (PIO_PDR) PIO Disable Position */ 326 #define PIO_PDR_P26_Msk (_U_(0x1) << PIO_PDR_P26_Pos) /**< (PIO_PDR) PIO Disable Mask */ 327 #define PIO_PDR_P26 PIO_PDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P26_Msk instead */ 328 #define PIO_PDR_P27_Pos 27 /**< (PIO_PDR) PIO Disable Position */ 329 #define PIO_PDR_P27_Msk (_U_(0x1) << PIO_PDR_P27_Pos) /**< (PIO_PDR) PIO Disable Mask */ 330 #define PIO_PDR_P27 PIO_PDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P27_Msk instead */ 331 #define PIO_PDR_P28_Pos 28 /**< (PIO_PDR) PIO Disable Position */ 332 #define PIO_PDR_P28_Msk (_U_(0x1) << PIO_PDR_P28_Pos) /**< (PIO_PDR) PIO Disable Mask */ 333 #define PIO_PDR_P28 PIO_PDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P28_Msk instead */ 334 #define PIO_PDR_P29_Pos 29 /**< (PIO_PDR) PIO Disable Position */ 335 #define PIO_PDR_P29_Msk (_U_(0x1) << PIO_PDR_P29_Pos) /**< (PIO_PDR) PIO Disable Mask */ 336 #define PIO_PDR_P29 PIO_PDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P29_Msk instead */ 337 #define PIO_PDR_P30_Pos 30 /**< (PIO_PDR) PIO Disable Position */ 338 #define PIO_PDR_P30_Msk (_U_(0x1) << PIO_PDR_P30_Pos) /**< (PIO_PDR) PIO Disable Mask */ 339 #define PIO_PDR_P30 PIO_PDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P30_Msk instead */ 340 #define PIO_PDR_P31_Pos 31 /**< (PIO_PDR) PIO Disable Position */ 341 #define PIO_PDR_P31_Msk (_U_(0x1) << PIO_PDR_P31_Pos) /**< (PIO_PDR) PIO Disable Mask */ 342 #define PIO_PDR_P31 PIO_PDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P31_Msk instead */ 343 #define PIO_PDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PDR) Register MASK (Use PIO_PDR_Msk instead) */ 344 #define PIO_PDR_Msk _U_(0xFFFFFFFF) /**< (PIO_PDR) Register Mask */ 345 346 #define PIO_PDR_P_Pos 0 /**< (PIO_PDR Position) PIO Disable */ 347 #define PIO_PDR_P_Msk (_U_(0xFFFFFFFF) << PIO_PDR_P_Pos) /**< (PIO_PDR Mask) P */ 348 #define PIO_PDR_P(value) (PIO_PDR_P_Msk & ((value) << PIO_PDR_P_Pos)) 349 350 /* -------- PIO_PSR : (PIO Offset: 0x08) (R/ 32) PIO Status Register -------- */ 351 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 352 #if COMPONENT_TYPEDEF_STYLE == 'N' 353 typedef union { 354 struct { 355 uint32_t P0:1; /**< bit: 0 PIO Status */ 356 uint32_t P1:1; /**< bit: 1 PIO Status */ 357 uint32_t P2:1; /**< bit: 2 PIO Status */ 358 uint32_t P3:1; /**< bit: 3 PIO Status */ 359 uint32_t P4:1; /**< bit: 4 PIO Status */ 360 uint32_t P5:1; /**< bit: 5 PIO Status */ 361 uint32_t P6:1; /**< bit: 6 PIO Status */ 362 uint32_t P7:1; /**< bit: 7 PIO Status */ 363 uint32_t P8:1; /**< bit: 8 PIO Status */ 364 uint32_t P9:1; /**< bit: 9 PIO Status */ 365 uint32_t P10:1; /**< bit: 10 PIO Status */ 366 uint32_t P11:1; /**< bit: 11 PIO Status */ 367 uint32_t P12:1; /**< bit: 12 PIO Status */ 368 uint32_t P13:1; /**< bit: 13 PIO Status */ 369 uint32_t P14:1; /**< bit: 14 PIO Status */ 370 uint32_t P15:1; /**< bit: 15 PIO Status */ 371 uint32_t P16:1; /**< bit: 16 PIO Status */ 372 uint32_t P17:1; /**< bit: 17 PIO Status */ 373 uint32_t P18:1; /**< bit: 18 PIO Status */ 374 uint32_t P19:1; /**< bit: 19 PIO Status */ 375 uint32_t P20:1; /**< bit: 20 PIO Status */ 376 uint32_t P21:1; /**< bit: 21 PIO Status */ 377 uint32_t P22:1; /**< bit: 22 PIO Status */ 378 uint32_t P23:1; /**< bit: 23 PIO Status */ 379 uint32_t P24:1; /**< bit: 24 PIO Status */ 380 uint32_t P25:1; /**< bit: 25 PIO Status */ 381 uint32_t P26:1; /**< bit: 26 PIO Status */ 382 uint32_t P27:1; /**< bit: 27 PIO Status */ 383 uint32_t P28:1; /**< bit: 28 PIO Status */ 384 uint32_t P29:1; /**< bit: 29 PIO Status */ 385 uint32_t P30:1; /**< bit: 30 PIO Status */ 386 uint32_t P31:1; /**< bit: 31 PIO Status */ 387 } bit; /**< Structure used for bit access */ 388 struct { 389 uint32_t P:32; /**< bit: 0..31 PIO Status */ 390 } vec; /**< Structure used for vec access */ 391 uint32_t reg; /**< Type used for register access */ 392 } PIO_PSR_Type; 393 #endif 394 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 395 396 #define PIO_PSR_OFFSET (0x08) /**< (PIO_PSR) PIO Status Register Offset */ 397 398 #define PIO_PSR_P0_Pos 0 /**< (PIO_PSR) PIO Status Position */ 399 #define PIO_PSR_P0_Msk (_U_(0x1) << PIO_PSR_P0_Pos) /**< (PIO_PSR) PIO Status Mask */ 400 #define PIO_PSR_P0 PIO_PSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P0_Msk instead */ 401 #define PIO_PSR_P1_Pos 1 /**< (PIO_PSR) PIO Status Position */ 402 #define PIO_PSR_P1_Msk (_U_(0x1) << PIO_PSR_P1_Pos) /**< (PIO_PSR) PIO Status Mask */ 403 #define PIO_PSR_P1 PIO_PSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P1_Msk instead */ 404 #define PIO_PSR_P2_Pos 2 /**< (PIO_PSR) PIO Status Position */ 405 #define PIO_PSR_P2_Msk (_U_(0x1) << PIO_PSR_P2_Pos) /**< (PIO_PSR) PIO Status Mask */ 406 #define PIO_PSR_P2 PIO_PSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P2_Msk instead */ 407 #define PIO_PSR_P3_Pos 3 /**< (PIO_PSR) PIO Status Position */ 408 #define PIO_PSR_P3_Msk (_U_(0x1) << PIO_PSR_P3_Pos) /**< (PIO_PSR) PIO Status Mask */ 409 #define PIO_PSR_P3 PIO_PSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P3_Msk instead */ 410 #define PIO_PSR_P4_Pos 4 /**< (PIO_PSR) PIO Status Position */ 411 #define PIO_PSR_P4_Msk (_U_(0x1) << PIO_PSR_P4_Pos) /**< (PIO_PSR) PIO Status Mask */ 412 #define PIO_PSR_P4 PIO_PSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P4_Msk instead */ 413 #define PIO_PSR_P5_Pos 5 /**< (PIO_PSR) PIO Status Position */ 414 #define PIO_PSR_P5_Msk (_U_(0x1) << PIO_PSR_P5_Pos) /**< (PIO_PSR) PIO Status Mask */ 415 #define PIO_PSR_P5 PIO_PSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P5_Msk instead */ 416 #define PIO_PSR_P6_Pos 6 /**< (PIO_PSR) PIO Status Position */ 417 #define PIO_PSR_P6_Msk (_U_(0x1) << PIO_PSR_P6_Pos) /**< (PIO_PSR) PIO Status Mask */ 418 #define PIO_PSR_P6 PIO_PSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P6_Msk instead */ 419 #define PIO_PSR_P7_Pos 7 /**< (PIO_PSR) PIO Status Position */ 420 #define PIO_PSR_P7_Msk (_U_(0x1) << PIO_PSR_P7_Pos) /**< (PIO_PSR) PIO Status Mask */ 421 #define PIO_PSR_P7 PIO_PSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P7_Msk instead */ 422 #define PIO_PSR_P8_Pos 8 /**< (PIO_PSR) PIO Status Position */ 423 #define PIO_PSR_P8_Msk (_U_(0x1) << PIO_PSR_P8_Pos) /**< (PIO_PSR) PIO Status Mask */ 424 #define PIO_PSR_P8 PIO_PSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P8_Msk instead */ 425 #define PIO_PSR_P9_Pos 9 /**< (PIO_PSR) PIO Status Position */ 426 #define PIO_PSR_P9_Msk (_U_(0x1) << PIO_PSR_P9_Pos) /**< (PIO_PSR) PIO Status Mask */ 427 #define PIO_PSR_P9 PIO_PSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P9_Msk instead */ 428 #define PIO_PSR_P10_Pos 10 /**< (PIO_PSR) PIO Status Position */ 429 #define PIO_PSR_P10_Msk (_U_(0x1) << PIO_PSR_P10_Pos) /**< (PIO_PSR) PIO Status Mask */ 430 #define PIO_PSR_P10 PIO_PSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P10_Msk instead */ 431 #define PIO_PSR_P11_Pos 11 /**< (PIO_PSR) PIO Status Position */ 432 #define PIO_PSR_P11_Msk (_U_(0x1) << PIO_PSR_P11_Pos) /**< (PIO_PSR) PIO Status Mask */ 433 #define PIO_PSR_P11 PIO_PSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P11_Msk instead */ 434 #define PIO_PSR_P12_Pos 12 /**< (PIO_PSR) PIO Status Position */ 435 #define PIO_PSR_P12_Msk (_U_(0x1) << PIO_PSR_P12_Pos) /**< (PIO_PSR) PIO Status Mask */ 436 #define PIO_PSR_P12 PIO_PSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P12_Msk instead */ 437 #define PIO_PSR_P13_Pos 13 /**< (PIO_PSR) PIO Status Position */ 438 #define PIO_PSR_P13_Msk (_U_(0x1) << PIO_PSR_P13_Pos) /**< (PIO_PSR) PIO Status Mask */ 439 #define PIO_PSR_P13 PIO_PSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P13_Msk instead */ 440 #define PIO_PSR_P14_Pos 14 /**< (PIO_PSR) PIO Status Position */ 441 #define PIO_PSR_P14_Msk (_U_(0x1) << PIO_PSR_P14_Pos) /**< (PIO_PSR) PIO Status Mask */ 442 #define PIO_PSR_P14 PIO_PSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P14_Msk instead */ 443 #define PIO_PSR_P15_Pos 15 /**< (PIO_PSR) PIO Status Position */ 444 #define PIO_PSR_P15_Msk (_U_(0x1) << PIO_PSR_P15_Pos) /**< (PIO_PSR) PIO Status Mask */ 445 #define PIO_PSR_P15 PIO_PSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P15_Msk instead */ 446 #define PIO_PSR_P16_Pos 16 /**< (PIO_PSR) PIO Status Position */ 447 #define PIO_PSR_P16_Msk (_U_(0x1) << PIO_PSR_P16_Pos) /**< (PIO_PSR) PIO Status Mask */ 448 #define PIO_PSR_P16 PIO_PSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P16_Msk instead */ 449 #define PIO_PSR_P17_Pos 17 /**< (PIO_PSR) PIO Status Position */ 450 #define PIO_PSR_P17_Msk (_U_(0x1) << PIO_PSR_P17_Pos) /**< (PIO_PSR) PIO Status Mask */ 451 #define PIO_PSR_P17 PIO_PSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P17_Msk instead */ 452 #define PIO_PSR_P18_Pos 18 /**< (PIO_PSR) PIO Status Position */ 453 #define PIO_PSR_P18_Msk (_U_(0x1) << PIO_PSR_P18_Pos) /**< (PIO_PSR) PIO Status Mask */ 454 #define PIO_PSR_P18 PIO_PSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P18_Msk instead */ 455 #define PIO_PSR_P19_Pos 19 /**< (PIO_PSR) PIO Status Position */ 456 #define PIO_PSR_P19_Msk (_U_(0x1) << PIO_PSR_P19_Pos) /**< (PIO_PSR) PIO Status Mask */ 457 #define PIO_PSR_P19 PIO_PSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P19_Msk instead */ 458 #define PIO_PSR_P20_Pos 20 /**< (PIO_PSR) PIO Status Position */ 459 #define PIO_PSR_P20_Msk (_U_(0x1) << PIO_PSR_P20_Pos) /**< (PIO_PSR) PIO Status Mask */ 460 #define PIO_PSR_P20 PIO_PSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P20_Msk instead */ 461 #define PIO_PSR_P21_Pos 21 /**< (PIO_PSR) PIO Status Position */ 462 #define PIO_PSR_P21_Msk (_U_(0x1) << PIO_PSR_P21_Pos) /**< (PIO_PSR) PIO Status Mask */ 463 #define PIO_PSR_P21 PIO_PSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P21_Msk instead */ 464 #define PIO_PSR_P22_Pos 22 /**< (PIO_PSR) PIO Status Position */ 465 #define PIO_PSR_P22_Msk (_U_(0x1) << PIO_PSR_P22_Pos) /**< (PIO_PSR) PIO Status Mask */ 466 #define PIO_PSR_P22 PIO_PSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P22_Msk instead */ 467 #define PIO_PSR_P23_Pos 23 /**< (PIO_PSR) PIO Status Position */ 468 #define PIO_PSR_P23_Msk (_U_(0x1) << PIO_PSR_P23_Pos) /**< (PIO_PSR) PIO Status Mask */ 469 #define PIO_PSR_P23 PIO_PSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P23_Msk instead */ 470 #define PIO_PSR_P24_Pos 24 /**< (PIO_PSR) PIO Status Position */ 471 #define PIO_PSR_P24_Msk (_U_(0x1) << PIO_PSR_P24_Pos) /**< (PIO_PSR) PIO Status Mask */ 472 #define PIO_PSR_P24 PIO_PSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P24_Msk instead */ 473 #define PIO_PSR_P25_Pos 25 /**< (PIO_PSR) PIO Status Position */ 474 #define PIO_PSR_P25_Msk (_U_(0x1) << PIO_PSR_P25_Pos) /**< (PIO_PSR) PIO Status Mask */ 475 #define PIO_PSR_P25 PIO_PSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P25_Msk instead */ 476 #define PIO_PSR_P26_Pos 26 /**< (PIO_PSR) PIO Status Position */ 477 #define PIO_PSR_P26_Msk (_U_(0x1) << PIO_PSR_P26_Pos) /**< (PIO_PSR) PIO Status Mask */ 478 #define PIO_PSR_P26 PIO_PSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P26_Msk instead */ 479 #define PIO_PSR_P27_Pos 27 /**< (PIO_PSR) PIO Status Position */ 480 #define PIO_PSR_P27_Msk (_U_(0x1) << PIO_PSR_P27_Pos) /**< (PIO_PSR) PIO Status Mask */ 481 #define PIO_PSR_P27 PIO_PSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P27_Msk instead */ 482 #define PIO_PSR_P28_Pos 28 /**< (PIO_PSR) PIO Status Position */ 483 #define PIO_PSR_P28_Msk (_U_(0x1) << PIO_PSR_P28_Pos) /**< (PIO_PSR) PIO Status Mask */ 484 #define PIO_PSR_P28 PIO_PSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P28_Msk instead */ 485 #define PIO_PSR_P29_Pos 29 /**< (PIO_PSR) PIO Status Position */ 486 #define PIO_PSR_P29_Msk (_U_(0x1) << PIO_PSR_P29_Pos) /**< (PIO_PSR) PIO Status Mask */ 487 #define PIO_PSR_P29 PIO_PSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P29_Msk instead */ 488 #define PIO_PSR_P30_Pos 30 /**< (PIO_PSR) PIO Status Position */ 489 #define PIO_PSR_P30_Msk (_U_(0x1) << PIO_PSR_P30_Pos) /**< (PIO_PSR) PIO Status Mask */ 490 #define PIO_PSR_P30 PIO_PSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P30_Msk instead */ 491 #define PIO_PSR_P31_Pos 31 /**< (PIO_PSR) PIO Status Position */ 492 #define PIO_PSR_P31_Msk (_U_(0x1) << PIO_PSR_P31_Pos) /**< (PIO_PSR) PIO Status Mask */ 493 #define PIO_PSR_P31 PIO_PSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P31_Msk instead */ 494 #define PIO_PSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PSR) Register MASK (Use PIO_PSR_Msk instead) */ 495 #define PIO_PSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PSR) Register Mask */ 496 497 #define PIO_PSR_P_Pos 0 /**< (PIO_PSR Position) PIO Status */ 498 #define PIO_PSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PSR_P_Pos) /**< (PIO_PSR Mask) P */ 499 #define PIO_PSR_P(value) (PIO_PSR_P_Msk & ((value) << PIO_PSR_P_Pos)) 500 501 /* -------- PIO_OER : (PIO Offset: 0x10) (/W 32) Output Enable Register -------- */ 502 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 503 #if COMPONENT_TYPEDEF_STYLE == 'N' 504 typedef union { 505 struct { 506 uint32_t P0:1; /**< bit: 0 Output Enable */ 507 uint32_t P1:1; /**< bit: 1 Output Enable */ 508 uint32_t P2:1; /**< bit: 2 Output Enable */ 509 uint32_t P3:1; /**< bit: 3 Output Enable */ 510 uint32_t P4:1; /**< bit: 4 Output Enable */ 511 uint32_t P5:1; /**< bit: 5 Output Enable */ 512 uint32_t P6:1; /**< bit: 6 Output Enable */ 513 uint32_t P7:1; /**< bit: 7 Output Enable */ 514 uint32_t P8:1; /**< bit: 8 Output Enable */ 515 uint32_t P9:1; /**< bit: 9 Output Enable */ 516 uint32_t P10:1; /**< bit: 10 Output Enable */ 517 uint32_t P11:1; /**< bit: 11 Output Enable */ 518 uint32_t P12:1; /**< bit: 12 Output Enable */ 519 uint32_t P13:1; /**< bit: 13 Output Enable */ 520 uint32_t P14:1; /**< bit: 14 Output Enable */ 521 uint32_t P15:1; /**< bit: 15 Output Enable */ 522 uint32_t P16:1; /**< bit: 16 Output Enable */ 523 uint32_t P17:1; /**< bit: 17 Output Enable */ 524 uint32_t P18:1; /**< bit: 18 Output Enable */ 525 uint32_t P19:1; /**< bit: 19 Output Enable */ 526 uint32_t P20:1; /**< bit: 20 Output Enable */ 527 uint32_t P21:1; /**< bit: 21 Output Enable */ 528 uint32_t P22:1; /**< bit: 22 Output Enable */ 529 uint32_t P23:1; /**< bit: 23 Output Enable */ 530 uint32_t P24:1; /**< bit: 24 Output Enable */ 531 uint32_t P25:1; /**< bit: 25 Output Enable */ 532 uint32_t P26:1; /**< bit: 26 Output Enable */ 533 uint32_t P27:1; /**< bit: 27 Output Enable */ 534 uint32_t P28:1; /**< bit: 28 Output Enable */ 535 uint32_t P29:1; /**< bit: 29 Output Enable */ 536 uint32_t P30:1; /**< bit: 30 Output Enable */ 537 uint32_t P31:1; /**< bit: 31 Output Enable */ 538 } bit; /**< Structure used for bit access */ 539 struct { 540 uint32_t P:32; /**< bit: 0..31 Output Enable */ 541 } vec; /**< Structure used for vec access */ 542 uint32_t reg; /**< Type used for register access */ 543 } PIO_OER_Type; 544 #endif 545 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 546 547 #define PIO_OER_OFFSET (0x10) /**< (PIO_OER) Output Enable Register Offset */ 548 549 #define PIO_OER_P0_Pos 0 /**< (PIO_OER) Output Enable Position */ 550 #define PIO_OER_P0_Msk (_U_(0x1) << PIO_OER_P0_Pos) /**< (PIO_OER) Output Enable Mask */ 551 #define PIO_OER_P0 PIO_OER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P0_Msk instead */ 552 #define PIO_OER_P1_Pos 1 /**< (PIO_OER) Output Enable Position */ 553 #define PIO_OER_P1_Msk (_U_(0x1) << PIO_OER_P1_Pos) /**< (PIO_OER) Output Enable Mask */ 554 #define PIO_OER_P1 PIO_OER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P1_Msk instead */ 555 #define PIO_OER_P2_Pos 2 /**< (PIO_OER) Output Enable Position */ 556 #define PIO_OER_P2_Msk (_U_(0x1) << PIO_OER_P2_Pos) /**< (PIO_OER) Output Enable Mask */ 557 #define PIO_OER_P2 PIO_OER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P2_Msk instead */ 558 #define PIO_OER_P3_Pos 3 /**< (PIO_OER) Output Enable Position */ 559 #define PIO_OER_P3_Msk (_U_(0x1) << PIO_OER_P3_Pos) /**< (PIO_OER) Output Enable Mask */ 560 #define PIO_OER_P3 PIO_OER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P3_Msk instead */ 561 #define PIO_OER_P4_Pos 4 /**< (PIO_OER) Output Enable Position */ 562 #define PIO_OER_P4_Msk (_U_(0x1) << PIO_OER_P4_Pos) /**< (PIO_OER) Output Enable Mask */ 563 #define PIO_OER_P4 PIO_OER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P4_Msk instead */ 564 #define PIO_OER_P5_Pos 5 /**< (PIO_OER) Output Enable Position */ 565 #define PIO_OER_P5_Msk (_U_(0x1) << PIO_OER_P5_Pos) /**< (PIO_OER) Output Enable Mask */ 566 #define PIO_OER_P5 PIO_OER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P5_Msk instead */ 567 #define PIO_OER_P6_Pos 6 /**< (PIO_OER) Output Enable Position */ 568 #define PIO_OER_P6_Msk (_U_(0x1) << PIO_OER_P6_Pos) /**< (PIO_OER) Output Enable Mask */ 569 #define PIO_OER_P6 PIO_OER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P6_Msk instead */ 570 #define PIO_OER_P7_Pos 7 /**< (PIO_OER) Output Enable Position */ 571 #define PIO_OER_P7_Msk (_U_(0x1) << PIO_OER_P7_Pos) /**< (PIO_OER) Output Enable Mask */ 572 #define PIO_OER_P7 PIO_OER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P7_Msk instead */ 573 #define PIO_OER_P8_Pos 8 /**< (PIO_OER) Output Enable Position */ 574 #define PIO_OER_P8_Msk (_U_(0x1) << PIO_OER_P8_Pos) /**< (PIO_OER) Output Enable Mask */ 575 #define PIO_OER_P8 PIO_OER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P8_Msk instead */ 576 #define PIO_OER_P9_Pos 9 /**< (PIO_OER) Output Enable Position */ 577 #define PIO_OER_P9_Msk (_U_(0x1) << PIO_OER_P9_Pos) /**< (PIO_OER) Output Enable Mask */ 578 #define PIO_OER_P9 PIO_OER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P9_Msk instead */ 579 #define PIO_OER_P10_Pos 10 /**< (PIO_OER) Output Enable Position */ 580 #define PIO_OER_P10_Msk (_U_(0x1) << PIO_OER_P10_Pos) /**< (PIO_OER) Output Enable Mask */ 581 #define PIO_OER_P10 PIO_OER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P10_Msk instead */ 582 #define PIO_OER_P11_Pos 11 /**< (PIO_OER) Output Enable Position */ 583 #define PIO_OER_P11_Msk (_U_(0x1) << PIO_OER_P11_Pos) /**< (PIO_OER) Output Enable Mask */ 584 #define PIO_OER_P11 PIO_OER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P11_Msk instead */ 585 #define PIO_OER_P12_Pos 12 /**< (PIO_OER) Output Enable Position */ 586 #define PIO_OER_P12_Msk (_U_(0x1) << PIO_OER_P12_Pos) /**< (PIO_OER) Output Enable Mask */ 587 #define PIO_OER_P12 PIO_OER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P12_Msk instead */ 588 #define PIO_OER_P13_Pos 13 /**< (PIO_OER) Output Enable Position */ 589 #define PIO_OER_P13_Msk (_U_(0x1) << PIO_OER_P13_Pos) /**< (PIO_OER) Output Enable Mask */ 590 #define PIO_OER_P13 PIO_OER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P13_Msk instead */ 591 #define PIO_OER_P14_Pos 14 /**< (PIO_OER) Output Enable Position */ 592 #define PIO_OER_P14_Msk (_U_(0x1) << PIO_OER_P14_Pos) /**< (PIO_OER) Output Enable Mask */ 593 #define PIO_OER_P14 PIO_OER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P14_Msk instead */ 594 #define PIO_OER_P15_Pos 15 /**< (PIO_OER) Output Enable Position */ 595 #define PIO_OER_P15_Msk (_U_(0x1) << PIO_OER_P15_Pos) /**< (PIO_OER) Output Enable Mask */ 596 #define PIO_OER_P15 PIO_OER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P15_Msk instead */ 597 #define PIO_OER_P16_Pos 16 /**< (PIO_OER) Output Enable Position */ 598 #define PIO_OER_P16_Msk (_U_(0x1) << PIO_OER_P16_Pos) /**< (PIO_OER) Output Enable Mask */ 599 #define PIO_OER_P16 PIO_OER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P16_Msk instead */ 600 #define PIO_OER_P17_Pos 17 /**< (PIO_OER) Output Enable Position */ 601 #define PIO_OER_P17_Msk (_U_(0x1) << PIO_OER_P17_Pos) /**< (PIO_OER) Output Enable Mask */ 602 #define PIO_OER_P17 PIO_OER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P17_Msk instead */ 603 #define PIO_OER_P18_Pos 18 /**< (PIO_OER) Output Enable Position */ 604 #define PIO_OER_P18_Msk (_U_(0x1) << PIO_OER_P18_Pos) /**< (PIO_OER) Output Enable Mask */ 605 #define PIO_OER_P18 PIO_OER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P18_Msk instead */ 606 #define PIO_OER_P19_Pos 19 /**< (PIO_OER) Output Enable Position */ 607 #define PIO_OER_P19_Msk (_U_(0x1) << PIO_OER_P19_Pos) /**< (PIO_OER) Output Enable Mask */ 608 #define PIO_OER_P19 PIO_OER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P19_Msk instead */ 609 #define PIO_OER_P20_Pos 20 /**< (PIO_OER) Output Enable Position */ 610 #define PIO_OER_P20_Msk (_U_(0x1) << PIO_OER_P20_Pos) /**< (PIO_OER) Output Enable Mask */ 611 #define PIO_OER_P20 PIO_OER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P20_Msk instead */ 612 #define PIO_OER_P21_Pos 21 /**< (PIO_OER) Output Enable Position */ 613 #define PIO_OER_P21_Msk (_U_(0x1) << PIO_OER_P21_Pos) /**< (PIO_OER) Output Enable Mask */ 614 #define PIO_OER_P21 PIO_OER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P21_Msk instead */ 615 #define PIO_OER_P22_Pos 22 /**< (PIO_OER) Output Enable Position */ 616 #define PIO_OER_P22_Msk (_U_(0x1) << PIO_OER_P22_Pos) /**< (PIO_OER) Output Enable Mask */ 617 #define PIO_OER_P22 PIO_OER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P22_Msk instead */ 618 #define PIO_OER_P23_Pos 23 /**< (PIO_OER) Output Enable Position */ 619 #define PIO_OER_P23_Msk (_U_(0x1) << PIO_OER_P23_Pos) /**< (PIO_OER) Output Enable Mask */ 620 #define PIO_OER_P23 PIO_OER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P23_Msk instead */ 621 #define PIO_OER_P24_Pos 24 /**< (PIO_OER) Output Enable Position */ 622 #define PIO_OER_P24_Msk (_U_(0x1) << PIO_OER_P24_Pos) /**< (PIO_OER) Output Enable Mask */ 623 #define PIO_OER_P24 PIO_OER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P24_Msk instead */ 624 #define PIO_OER_P25_Pos 25 /**< (PIO_OER) Output Enable Position */ 625 #define PIO_OER_P25_Msk (_U_(0x1) << PIO_OER_P25_Pos) /**< (PIO_OER) Output Enable Mask */ 626 #define PIO_OER_P25 PIO_OER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P25_Msk instead */ 627 #define PIO_OER_P26_Pos 26 /**< (PIO_OER) Output Enable Position */ 628 #define PIO_OER_P26_Msk (_U_(0x1) << PIO_OER_P26_Pos) /**< (PIO_OER) Output Enable Mask */ 629 #define PIO_OER_P26 PIO_OER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P26_Msk instead */ 630 #define PIO_OER_P27_Pos 27 /**< (PIO_OER) Output Enable Position */ 631 #define PIO_OER_P27_Msk (_U_(0x1) << PIO_OER_P27_Pos) /**< (PIO_OER) Output Enable Mask */ 632 #define PIO_OER_P27 PIO_OER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P27_Msk instead */ 633 #define PIO_OER_P28_Pos 28 /**< (PIO_OER) Output Enable Position */ 634 #define PIO_OER_P28_Msk (_U_(0x1) << PIO_OER_P28_Pos) /**< (PIO_OER) Output Enable Mask */ 635 #define PIO_OER_P28 PIO_OER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P28_Msk instead */ 636 #define PIO_OER_P29_Pos 29 /**< (PIO_OER) Output Enable Position */ 637 #define PIO_OER_P29_Msk (_U_(0x1) << PIO_OER_P29_Pos) /**< (PIO_OER) Output Enable Mask */ 638 #define PIO_OER_P29 PIO_OER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P29_Msk instead */ 639 #define PIO_OER_P30_Pos 30 /**< (PIO_OER) Output Enable Position */ 640 #define PIO_OER_P30_Msk (_U_(0x1) << PIO_OER_P30_Pos) /**< (PIO_OER) Output Enable Mask */ 641 #define PIO_OER_P30 PIO_OER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P30_Msk instead */ 642 #define PIO_OER_P31_Pos 31 /**< (PIO_OER) Output Enable Position */ 643 #define PIO_OER_P31_Msk (_U_(0x1) << PIO_OER_P31_Pos) /**< (PIO_OER) Output Enable Mask */ 644 #define PIO_OER_P31 PIO_OER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P31_Msk instead */ 645 #define PIO_OER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_OER) Register MASK (Use PIO_OER_Msk instead) */ 646 #define PIO_OER_Msk _U_(0xFFFFFFFF) /**< (PIO_OER) Register Mask */ 647 648 #define PIO_OER_P_Pos 0 /**< (PIO_OER Position) Output Enable */ 649 #define PIO_OER_P_Msk (_U_(0xFFFFFFFF) << PIO_OER_P_Pos) /**< (PIO_OER Mask) P */ 650 #define PIO_OER_P(value) (PIO_OER_P_Msk & ((value) << PIO_OER_P_Pos)) 651 652 /* -------- PIO_ODR : (PIO Offset: 0x14) (/W 32) Output Disable Register -------- */ 653 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 654 #if COMPONENT_TYPEDEF_STYLE == 'N' 655 typedef union { 656 struct { 657 uint32_t P0:1; /**< bit: 0 Output Disable */ 658 uint32_t P1:1; /**< bit: 1 Output Disable */ 659 uint32_t P2:1; /**< bit: 2 Output Disable */ 660 uint32_t P3:1; /**< bit: 3 Output Disable */ 661 uint32_t P4:1; /**< bit: 4 Output Disable */ 662 uint32_t P5:1; /**< bit: 5 Output Disable */ 663 uint32_t P6:1; /**< bit: 6 Output Disable */ 664 uint32_t P7:1; /**< bit: 7 Output Disable */ 665 uint32_t P8:1; /**< bit: 8 Output Disable */ 666 uint32_t P9:1; /**< bit: 9 Output Disable */ 667 uint32_t P10:1; /**< bit: 10 Output Disable */ 668 uint32_t P11:1; /**< bit: 11 Output Disable */ 669 uint32_t P12:1; /**< bit: 12 Output Disable */ 670 uint32_t P13:1; /**< bit: 13 Output Disable */ 671 uint32_t P14:1; /**< bit: 14 Output Disable */ 672 uint32_t P15:1; /**< bit: 15 Output Disable */ 673 uint32_t P16:1; /**< bit: 16 Output Disable */ 674 uint32_t P17:1; /**< bit: 17 Output Disable */ 675 uint32_t P18:1; /**< bit: 18 Output Disable */ 676 uint32_t P19:1; /**< bit: 19 Output Disable */ 677 uint32_t P20:1; /**< bit: 20 Output Disable */ 678 uint32_t P21:1; /**< bit: 21 Output Disable */ 679 uint32_t P22:1; /**< bit: 22 Output Disable */ 680 uint32_t P23:1; /**< bit: 23 Output Disable */ 681 uint32_t P24:1; /**< bit: 24 Output Disable */ 682 uint32_t P25:1; /**< bit: 25 Output Disable */ 683 uint32_t P26:1; /**< bit: 26 Output Disable */ 684 uint32_t P27:1; /**< bit: 27 Output Disable */ 685 uint32_t P28:1; /**< bit: 28 Output Disable */ 686 uint32_t P29:1; /**< bit: 29 Output Disable */ 687 uint32_t P30:1; /**< bit: 30 Output Disable */ 688 uint32_t P31:1; /**< bit: 31 Output Disable */ 689 } bit; /**< Structure used for bit access */ 690 struct { 691 uint32_t P:32; /**< bit: 0..31 Output Disable */ 692 } vec; /**< Structure used for vec access */ 693 uint32_t reg; /**< Type used for register access */ 694 } PIO_ODR_Type; 695 #endif 696 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 697 698 #define PIO_ODR_OFFSET (0x14) /**< (PIO_ODR) Output Disable Register Offset */ 699 700 #define PIO_ODR_P0_Pos 0 /**< (PIO_ODR) Output Disable Position */ 701 #define PIO_ODR_P0_Msk (_U_(0x1) << PIO_ODR_P0_Pos) /**< (PIO_ODR) Output Disable Mask */ 702 #define PIO_ODR_P0 PIO_ODR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P0_Msk instead */ 703 #define PIO_ODR_P1_Pos 1 /**< (PIO_ODR) Output Disable Position */ 704 #define PIO_ODR_P1_Msk (_U_(0x1) << PIO_ODR_P1_Pos) /**< (PIO_ODR) Output Disable Mask */ 705 #define PIO_ODR_P1 PIO_ODR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P1_Msk instead */ 706 #define PIO_ODR_P2_Pos 2 /**< (PIO_ODR) Output Disable Position */ 707 #define PIO_ODR_P2_Msk (_U_(0x1) << PIO_ODR_P2_Pos) /**< (PIO_ODR) Output Disable Mask */ 708 #define PIO_ODR_P2 PIO_ODR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P2_Msk instead */ 709 #define PIO_ODR_P3_Pos 3 /**< (PIO_ODR) Output Disable Position */ 710 #define PIO_ODR_P3_Msk (_U_(0x1) << PIO_ODR_P3_Pos) /**< (PIO_ODR) Output Disable Mask */ 711 #define PIO_ODR_P3 PIO_ODR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P3_Msk instead */ 712 #define PIO_ODR_P4_Pos 4 /**< (PIO_ODR) Output Disable Position */ 713 #define PIO_ODR_P4_Msk (_U_(0x1) << PIO_ODR_P4_Pos) /**< (PIO_ODR) Output Disable Mask */ 714 #define PIO_ODR_P4 PIO_ODR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P4_Msk instead */ 715 #define PIO_ODR_P5_Pos 5 /**< (PIO_ODR) Output Disable Position */ 716 #define PIO_ODR_P5_Msk (_U_(0x1) << PIO_ODR_P5_Pos) /**< (PIO_ODR) Output Disable Mask */ 717 #define PIO_ODR_P5 PIO_ODR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P5_Msk instead */ 718 #define PIO_ODR_P6_Pos 6 /**< (PIO_ODR) Output Disable Position */ 719 #define PIO_ODR_P6_Msk (_U_(0x1) << PIO_ODR_P6_Pos) /**< (PIO_ODR) Output Disable Mask */ 720 #define PIO_ODR_P6 PIO_ODR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P6_Msk instead */ 721 #define PIO_ODR_P7_Pos 7 /**< (PIO_ODR) Output Disable Position */ 722 #define PIO_ODR_P7_Msk (_U_(0x1) << PIO_ODR_P7_Pos) /**< (PIO_ODR) Output Disable Mask */ 723 #define PIO_ODR_P7 PIO_ODR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P7_Msk instead */ 724 #define PIO_ODR_P8_Pos 8 /**< (PIO_ODR) Output Disable Position */ 725 #define PIO_ODR_P8_Msk (_U_(0x1) << PIO_ODR_P8_Pos) /**< (PIO_ODR) Output Disable Mask */ 726 #define PIO_ODR_P8 PIO_ODR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P8_Msk instead */ 727 #define PIO_ODR_P9_Pos 9 /**< (PIO_ODR) Output Disable Position */ 728 #define PIO_ODR_P9_Msk (_U_(0x1) << PIO_ODR_P9_Pos) /**< (PIO_ODR) Output Disable Mask */ 729 #define PIO_ODR_P9 PIO_ODR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P9_Msk instead */ 730 #define PIO_ODR_P10_Pos 10 /**< (PIO_ODR) Output Disable Position */ 731 #define PIO_ODR_P10_Msk (_U_(0x1) << PIO_ODR_P10_Pos) /**< (PIO_ODR) Output Disable Mask */ 732 #define PIO_ODR_P10 PIO_ODR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P10_Msk instead */ 733 #define PIO_ODR_P11_Pos 11 /**< (PIO_ODR) Output Disable Position */ 734 #define PIO_ODR_P11_Msk (_U_(0x1) << PIO_ODR_P11_Pos) /**< (PIO_ODR) Output Disable Mask */ 735 #define PIO_ODR_P11 PIO_ODR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P11_Msk instead */ 736 #define PIO_ODR_P12_Pos 12 /**< (PIO_ODR) Output Disable Position */ 737 #define PIO_ODR_P12_Msk (_U_(0x1) << PIO_ODR_P12_Pos) /**< (PIO_ODR) Output Disable Mask */ 738 #define PIO_ODR_P12 PIO_ODR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P12_Msk instead */ 739 #define PIO_ODR_P13_Pos 13 /**< (PIO_ODR) Output Disable Position */ 740 #define PIO_ODR_P13_Msk (_U_(0x1) << PIO_ODR_P13_Pos) /**< (PIO_ODR) Output Disable Mask */ 741 #define PIO_ODR_P13 PIO_ODR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P13_Msk instead */ 742 #define PIO_ODR_P14_Pos 14 /**< (PIO_ODR) Output Disable Position */ 743 #define PIO_ODR_P14_Msk (_U_(0x1) << PIO_ODR_P14_Pos) /**< (PIO_ODR) Output Disable Mask */ 744 #define PIO_ODR_P14 PIO_ODR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P14_Msk instead */ 745 #define PIO_ODR_P15_Pos 15 /**< (PIO_ODR) Output Disable Position */ 746 #define PIO_ODR_P15_Msk (_U_(0x1) << PIO_ODR_P15_Pos) /**< (PIO_ODR) Output Disable Mask */ 747 #define PIO_ODR_P15 PIO_ODR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P15_Msk instead */ 748 #define PIO_ODR_P16_Pos 16 /**< (PIO_ODR) Output Disable Position */ 749 #define PIO_ODR_P16_Msk (_U_(0x1) << PIO_ODR_P16_Pos) /**< (PIO_ODR) Output Disable Mask */ 750 #define PIO_ODR_P16 PIO_ODR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P16_Msk instead */ 751 #define PIO_ODR_P17_Pos 17 /**< (PIO_ODR) Output Disable Position */ 752 #define PIO_ODR_P17_Msk (_U_(0x1) << PIO_ODR_P17_Pos) /**< (PIO_ODR) Output Disable Mask */ 753 #define PIO_ODR_P17 PIO_ODR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P17_Msk instead */ 754 #define PIO_ODR_P18_Pos 18 /**< (PIO_ODR) Output Disable Position */ 755 #define PIO_ODR_P18_Msk (_U_(0x1) << PIO_ODR_P18_Pos) /**< (PIO_ODR) Output Disable Mask */ 756 #define PIO_ODR_P18 PIO_ODR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P18_Msk instead */ 757 #define PIO_ODR_P19_Pos 19 /**< (PIO_ODR) Output Disable Position */ 758 #define PIO_ODR_P19_Msk (_U_(0x1) << PIO_ODR_P19_Pos) /**< (PIO_ODR) Output Disable Mask */ 759 #define PIO_ODR_P19 PIO_ODR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P19_Msk instead */ 760 #define PIO_ODR_P20_Pos 20 /**< (PIO_ODR) Output Disable Position */ 761 #define PIO_ODR_P20_Msk (_U_(0x1) << PIO_ODR_P20_Pos) /**< (PIO_ODR) Output Disable Mask */ 762 #define PIO_ODR_P20 PIO_ODR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P20_Msk instead */ 763 #define PIO_ODR_P21_Pos 21 /**< (PIO_ODR) Output Disable Position */ 764 #define PIO_ODR_P21_Msk (_U_(0x1) << PIO_ODR_P21_Pos) /**< (PIO_ODR) Output Disable Mask */ 765 #define PIO_ODR_P21 PIO_ODR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P21_Msk instead */ 766 #define PIO_ODR_P22_Pos 22 /**< (PIO_ODR) Output Disable Position */ 767 #define PIO_ODR_P22_Msk (_U_(0x1) << PIO_ODR_P22_Pos) /**< (PIO_ODR) Output Disable Mask */ 768 #define PIO_ODR_P22 PIO_ODR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P22_Msk instead */ 769 #define PIO_ODR_P23_Pos 23 /**< (PIO_ODR) Output Disable Position */ 770 #define PIO_ODR_P23_Msk (_U_(0x1) << PIO_ODR_P23_Pos) /**< (PIO_ODR) Output Disable Mask */ 771 #define PIO_ODR_P23 PIO_ODR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P23_Msk instead */ 772 #define PIO_ODR_P24_Pos 24 /**< (PIO_ODR) Output Disable Position */ 773 #define PIO_ODR_P24_Msk (_U_(0x1) << PIO_ODR_P24_Pos) /**< (PIO_ODR) Output Disable Mask */ 774 #define PIO_ODR_P24 PIO_ODR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P24_Msk instead */ 775 #define PIO_ODR_P25_Pos 25 /**< (PIO_ODR) Output Disable Position */ 776 #define PIO_ODR_P25_Msk (_U_(0x1) << PIO_ODR_P25_Pos) /**< (PIO_ODR) Output Disable Mask */ 777 #define PIO_ODR_P25 PIO_ODR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P25_Msk instead */ 778 #define PIO_ODR_P26_Pos 26 /**< (PIO_ODR) Output Disable Position */ 779 #define PIO_ODR_P26_Msk (_U_(0x1) << PIO_ODR_P26_Pos) /**< (PIO_ODR) Output Disable Mask */ 780 #define PIO_ODR_P26 PIO_ODR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P26_Msk instead */ 781 #define PIO_ODR_P27_Pos 27 /**< (PIO_ODR) Output Disable Position */ 782 #define PIO_ODR_P27_Msk (_U_(0x1) << PIO_ODR_P27_Pos) /**< (PIO_ODR) Output Disable Mask */ 783 #define PIO_ODR_P27 PIO_ODR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P27_Msk instead */ 784 #define PIO_ODR_P28_Pos 28 /**< (PIO_ODR) Output Disable Position */ 785 #define PIO_ODR_P28_Msk (_U_(0x1) << PIO_ODR_P28_Pos) /**< (PIO_ODR) Output Disable Mask */ 786 #define PIO_ODR_P28 PIO_ODR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P28_Msk instead */ 787 #define PIO_ODR_P29_Pos 29 /**< (PIO_ODR) Output Disable Position */ 788 #define PIO_ODR_P29_Msk (_U_(0x1) << PIO_ODR_P29_Pos) /**< (PIO_ODR) Output Disable Mask */ 789 #define PIO_ODR_P29 PIO_ODR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P29_Msk instead */ 790 #define PIO_ODR_P30_Pos 30 /**< (PIO_ODR) Output Disable Position */ 791 #define PIO_ODR_P30_Msk (_U_(0x1) << PIO_ODR_P30_Pos) /**< (PIO_ODR) Output Disable Mask */ 792 #define PIO_ODR_P30 PIO_ODR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P30_Msk instead */ 793 #define PIO_ODR_P31_Pos 31 /**< (PIO_ODR) Output Disable Position */ 794 #define PIO_ODR_P31_Msk (_U_(0x1) << PIO_ODR_P31_Pos) /**< (PIO_ODR) Output Disable Mask */ 795 #define PIO_ODR_P31 PIO_ODR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P31_Msk instead */ 796 #define PIO_ODR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_ODR) Register MASK (Use PIO_ODR_Msk instead) */ 797 #define PIO_ODR_Msk _U_(0xFFFFFFFF) /**< (PIO_ODR) Register Mask */ 798 799 #define PIO_ODR_P_Pos 0 /**< (PIO_ODR Position) Output Disable */ 800 #define PIO_ODR_P_Msk (_U_(0xFFFFFFFF) << PIO_ODR_P_Pos) /**< (PIO_ODR Mask) P */ 801 #define PIO_ODR_P(value) (PIO_ODR_P_Msk & ((value) << PIO_ODR_P_Pos)) 802 803 /* -------- PIO_OSR : (PIO Offset: 0x18) (R/ 32) Output Status Register -------- */ 804 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 805 #if COMPONENT_TYPEDEF_STYLE == 'N' 806 typedef union { 807 struct { 808 uint32_t P0:1; /**< bit: 0 Output Status */ 809 uint32_t P1:1; /**< bit: 1 Output Status */ 810 uint32_t P2:1; /**< bit: 2 Output Status */ 811 uint32_t P3:1; /**< bit: 3 Output Status */ 812 uint32_t P4:1; /**< bit: 4 Output Status */ 813 uint32_t P5:1; /**< bit: 5 Output Status */ 814 uint32_t P6:1; /**< bit: 6 Output Status */ 815 uint32_t P7:1; /**< bit: 7 Output Status */ 816 uint32_t P8:1; /**< bit: 8 Output Status */ 817 uint32_t P9:1; /**< bit: 9 Output Status */ 818 uint32_t P10:1; /**< bit: 10 Output Status */ 819 uint32_t P11:1; /**< bit: 11 Output Status */ 820 uint32_t P12:1; /**< bit: 12 Output Status */ 821 uint32_t P13:1; /**< bit: 13 Output Status */ 822 uint32_t P14:1; /**< bit: 14 Output Status */ 823 uint32_t P15:1; /**< bit: 15 Output Status */ 824 uint32_t P16:1; /**< bit: 16 Output Status */ 825 uint32_t P17:1; /**< bit: 17 Output Status */ 826 uint32_t P18:1; /**< bit: 18 Output Status */ 827 uint32_t P19:1; /**< bit: 19 Output Status */ 828 uint32_t P20:1; /**< bit: 20 Output Status */ 829 uint32_t P21:1; /**< bit: 21 Output Status */ 830 uint32_t P22:1; /**< bit: 22 Output Status */ 831 uint32_t P23:1; /**< bit: 23 Output Status */ 832 uint32_t P24:1; /**< bit: 24 Output Status */ 833 uint32_t P25:1; /**< bit: 25 Output Status */ 834 uint32_t P26:1; /**< bit: 26 Output Status */ 835 uint32_t P27:1; /**< bit: 27 Output Status */ 836 uint32_t P28:1; /**< bit: 28 Output Status */ 837 uint32_t P29:1; /**< bit: 29 Output Status */ 838 uint32_t P30:1; /**< bit: 30 Output Status */ 839 uint32_t P31:1; /**< bit: 31 Output Status */ 840 } bit; /**< Structure used for bit access */ 841 struct { 842 uint32_t P:32; /**< bit: 0..31 Output Status */ 843 } vec; /**< Structure used for vec access */ 844 uint32_t reg; /**< Type used for register access */ 845 } PIO_OSR_Type; 846 #endif 847 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 848 849 #define PIO_OSR_OFFSET (0x18) /**< (PIO_OSR) Output Status Register Offset */ 850 851 #define PIO_OSR_P0_Pos 0 /**< (PIO_OSR) Output Status Position */ 852 #define PIO_OSR_P0_Msk (_U_(0x1) << PIO_OSR_P0_Pos) /**< (PIO_OSR) Output Status Mask */ 853 #define PIO_OSR_P0 PIO_OSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P0_Msk instead */ 854 #define PIO_OSR_P1_Pos 1 /**< (PIO_OSR) Output Status Position */ 855 #define PIO_OSR_P1_Msk (_U_(0x1) << PIO_OSR_P1_Pos) /**< (PIO_OSR) Output Status Mask */ 856 #define PIO_OSR_P1 PIO_OSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P1_Msk instead */ 857 #define PIO_OSR_P2_Pos 2 /**< (PIO_OSR) Output Status Position */ 858 #define PIO_OSR_P2_Msk (_U_(0x1) << PIO_OSR_P2_Pos) /**< (PIO_OSR) Output Status Mask */ 859 #define PIO_OSR_P2 PIO_OSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P2_Msk instead */ 860 #define PIO_OSR_P3_Pos 3 /**< (PIO_OSR) Output Status Position */ 861 #define PIO_OSR_P3_Msk (_U_(0x1) << PIO_OSR_P3_Pos) /**< (PIO_OSR) Output Status Mask */ 862 #define PIO_OSR_P3 PIO_OSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P3_Msk instead */ 863 #define PIO_OSR_P4_Pos 4 /**< (PIO_OSR) Output Status Position */ 864 #define PIO_OSR_P4_Msk (_U_(0x1) << PIO_OSR_P4_Pos) /**< (PIO_OSR) Output Status Mask */ 865 #define PIO_OSR_P4 PIO_OSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P4_Msk instead */ 866 #define PIO_OSR_P5_Pos 5 /**< (PIO_OSR) Output Status Position */ 867 #define PIO_OSR_P5_Msk (_U_(0x1) << PIO_OSR_P5_Pos) /**< (PIO_OSR) Output Status Mask */ 868 #define PIO_OSR_P5 PIO_OSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P5_Msk instead */ 869 #define PIO_OSR_P6_Pos 6 /**< (PIO_OSR) Output Status Position */ 870 #define PIO_OSR_P6_Msk (_U_(0x1) << PIO_OSR_P6_Pos) /**< (PIO_OSR) Output Status Mask */ 871 #define PIO_OSR_P6 PIO_OSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P6_Msk instead */ 872 #define PIO_OSR_P7_Pos 7 /**< (PIO_OSR) Output Status Position */ 873 #define PIO_OSR_P7_Msk (_U_(0x1) << PIO_OSR_P7_Pos) /**< (PIO_OSR) Output Status Mask */ 874 #define PIO_OSR_P7 PIO_OSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P7_Msk instead */ 875 #define PIO_OSR_P8_Pos 8 /**< (PIO_OSR) Output Status Position */ 876 #define PIO_OSR_P8_Msk (_U_(0x1) << PIO_OSR_P8_Pos) /**< (PIO_OSR) Output Status Mask */ 877 #define PIO_OSR_P8 PIO_OSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P8_Msk instead */ 878 #define PIO_OSR_P9_Pos 9 /**< (PIO_OSR) Output Status Position */ 879 #define PIO_OSR_P9_Msk (_U_(0x1) << PIO_OSR_P9_Pos) /**< (PIO_OSR) Output Status Mask */ 880 #define PIO_OSR_P9 PIO_OSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P9_Msk instead */ 881 #define PIO_OSR_P10_Pos 10 /**< (PIO_OSR) Output Status Position */ 882 #define PIO_OSR_P10_Msk (_U_(0x1) << PIO_OSR_P10_Pos) /**< (PIO_OSR) Output Status Mask */ 883 #define PIO_OSR_P10 PIO_OSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P10_Msk instead */ 884 #define PIO_OSR_P11_Pos 11 /**< (PIO_OSR) Output Status Position */ 885 #define PIO_OSR_P11_Msk (_U_(0x1) << PIO_OSR_P11_Pos) /**< (PIO_OSR) Output Status Mask */ 886 #define PIO_OSR_P11 PIO_OSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P11_Msk instead */ 887 #define PIO_OSR_P12_Pos 12 /**< (PIO_OSR) Output Status Position */ 888 #define PIO_OSR_P12_Msk (_U_(0x1) << PIO_OSR_P12_Pos) /**< (PIO_OSR) Output Status Mask */ 889 #define PIO_OSR_P12 PIO_OSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P12_Msk instead */ 890 #define PIO_OSR_P13_Pos 13 /**< (PIO_OSR) Output Status Position */ 891 #define PIO_OSR_P13_Msk (_U_(0x1) << PIO_OSR_P13_Pos) /**< (PIO_OSR) Output Status Mask */ 892 #define PIO_OSR_P13 PIO_OSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P13_Msk instead */ 893 #define PIO_OSR_P14_Pos 14 /**< (PIO_OSR) Output Status Position */ 894 #define PIO_OSR_P14_Msk (_U_(0x1) << PIO_OSR_P14_Pos) /**< (PIO_OSR) Output Status Mask */ 895 #define PIO_OSR_P14 PIO_OSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P14_Msk instead */ 896 #define PIO_OSR_P15_Pos 15 /**< (PIO_OSR) Output Status Position */ 897 #define PIO_OSR_P15_Msk (_U_(0x1) << PIO_OSR_P15_Pos) /**< (PIO_OSR) Output Status Mask */ 898 #define PIO_OSR_P15 PIO_OSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P15_Msk instead */ 899 #define PIO_OSR_P16_Pos 16 /**< (PIO_OSR) Output Status Position */ 900 #define PIO_OSR_P16_Msk (_U_(0x1) << PIO_OSR_P16_Pos) /**< (PIO_OSR) Output Status Mask */ 901 #define PIO_OSR_P16 PIO_OSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P16_Msk instead */ 902 #define PIO_OSR_P17_Pos 17 /**< (PIO_OSR) Output Status Position */ 903 #define PIO_OSR_P17_Msk (_U_(0x1) << PIO_OSR_P17_Pos) /**< (PIO_OSR) Output Status Mask */ 904 #define PIO_OSR_P17 PIO_OSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P17_Msk instead */ 905 #define PIO_OSR_P18_Pos 18 /**< (PIO_OSR) Output Status Position */ 906 #define PIO_OSR_P18_Msk (_U_(0x1) << PIO_OSR_P18_Pos) /**< (PIO_OSR) Output Status Mask */ 907 #define PIO_OSR_P18 PIO_OSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P18_Msk instead */ 908 #define PIO_OSR_P19_Pos 19 /**< (PIO_OSR) Output Status Position */ 909 #define PIO_OSR_P19_Msk (_U_(0x1) << PIO_OSR_P19_Pos) /**< (PIO_OSR) Output Status Mask */ 910 #define PIO_OSR_P19 PIO_OSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P19_Msk instead */ 911 #define PIO_OSR_P20_Pos 20 /**< (PIO_OSR) Output Status Position */ 912 #define PIO_OSR_P20_Msk (_U_(0x1) << PIO_OSR_P20_Pos) /**< (PIO_OSR) Output Status Mask */ 913 #define PIO_OSR_P20 PIO_OSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P20_Msk instead */ 914 #define PIO_OSR_P21_Pos 21 /**< (PIO_OSR) Output Status Position */ 915 #define PIO_OSR_P21_Msk (_U_(0x1) << PIO_OSR_P21_Pos) /**< (PIO_OSR) Output Status Mask */ 916 #define PIO_OSR_P21 PIO_OSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P21_Msk instead */ 917 #define PIO_OSR_P22_Pos 22 /**< (PIO_OSR) Output Status Position */ 918 #define PIO_OSR_P22_Msk (_U_(0x1) << PIO_OSR_P22_Pos) /**< (PIO_OSR) Output Status Mask */ 919 #define PIO_OSR_P22 PIO_OSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P22_Msk instead */ 920 #define PIO_OSR_P23_Pos 23 /**< (PIO_OSR) Output Status Position */ 921 #define PIO_OSR_P23_Msk (_U_(0x1) << PIO_OSR_P23_Pos) /**< (PIO_OSR) Output Status Mask */ 922 #define PIO_OSR_P23 PIO_OSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P23_Msk instead */ 923 #define PIO_OSR_P24_Pos 24 /**< (PIO_OSR) Output Status Position */ 924 #define PIO_OSR_P24_Msk (_U_(0x1) << PIO_OSR_P24_Pos) /**< (PIO_OSR) Output Status Mask */ 925 #define PIO_OSR_P24 PIO_OSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P24_Msk instead */ 926 #define PIO_OSR_P25_Pos 25 /**< (PIO_OSR) Output Status Position */ 927 #define PIO_OSR_P25_Msk (_U_(0x1) << PIO_OSR_P25_Pos) /**< (PIO_OSR) Output Status Mask */ 928 #define PIO_OSR_P25 PIO_OSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P25_Msk instead */ 929 #define PIO_OSR_P26_Pos 26 /**< (PIO_OSR) Output Status Position */ 930 #define PIO_OSR_P26_Msk (_U_(0x1) << PIO_OSR_P26_Pos) /**< (PIO_OSR) Output Status Mask */ 931 #define PIO_OSR_P26 PIO_OSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P26_Msk instead */ 932 #define PIO_OSR_P27_Pos 27 /**< (PIO_OSR) Output Status Position */ 933 #define PIO_OSR_P27_Msk (_U_(0x1) << PIO_OSR_P27_Pos) /**< (PIO_OSR) Output Status Mask */ 934 #define PIO_OSR_P27 PIO_OSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P27_Msk instead */ 935 #define PIO_OSR_P28_Pos 28 /**< (PIO_OSR) Output Status Position */ 936 #define PIO_OSR_P28_Msk (_U_(0x1) << PIO_OSR_P28_Pos) /**< (PIO_OSR) Output Status Mask */ 937 #define PIO_OSR_P28 PIO_OSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P28_Msk instead */ 938 #define PIO_OSR_P29_Pos 29 /**< (PIO_OSR) Output Status Position */ 939 #define PIO_OSR_P29_Msk (_U_(0x1) << PIO_OSR_P29_Pos) /**< (PIO_OSR) Output Status Mask */ 940 #define PIO_OSR_P29 PIO_OSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P29_Msk instead */ 941 #define PIO_OSR_P30_Pos 30 /**< (PIO_OSR) Output Status Position */ 942 #define PIO_OSR_P30_Msk (_U_(0x1) << PIO_OSR_P30_Pos) /**< (PIO_OSR) Output Status Mask */ 943 #define PIO_OSR_P30 PIO_OSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P30_Msk instead */ 944 #define PIO_OSR_P31_Pos 31 /**< (PIO_OSR) Output Status Position */ 945 #define PIO_OSR_P31_Msk (_U_(0x1) << PIO_OSR_P31_Pos) /**< (PIO_OSR) Output Status Mask */ 946 #define PIO_OSR_P31 PIO_OSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P31_Msk instead */ 947 #define PIO_OSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_OSR) Register MASK (Use PIO_OSR_Msk instead) */ 948 #define PIO_OSR_Msk _U_(0xFFFFFFFF) /**< (PIO_OSR) Register Mask */ 949 950 #define PIO_OSR_P_Pos 0 /**< (PIO_OSR Position) Output Status */ 951 #define PIO_OSR_P_Msk (_U_(0xFFFFFFFF) << PIO_OSR_P_Pos) /**< (PIO_OSR Mask) P */ 952 #define PIO_OSR_P(value) (PIO_OSR_P_Msk & ((value) << PIO_OSR_P_Pos)) 953 954 /* -------- PIO_IFER : (PIO Offset: 0x20) (/W 32) Glitch Input Filter Enable Register -------- */ 955 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 956 #if COMPONENT_TYPEDEF_STYLE == 'N' 957 typedef union { 958 struct { 959 uint32_t P0:1; /**< bit: 0 Input Filter Enable */ 960 uint32_t P1:1; /**< bit: 1 Input Filter Enable */ 961 uint32_t P2:1; /**< bit: 2 Input Filter Enable */ 962 uint32_t P3:1; /**< bit: 3 Input Filter Enable */ 963 uint32_t P4:1; /**< bit: 4 Input Filter Enable */ 964 uint32_t P5:1; /**< bit: 5 Input Filter Enable */ 965 uint32_t P6:1; /**< bit: 6 Input Filter Enable */ 966 uint32_t P7:1; /**< bit: 7 Input Filter Enable */ 967 uint32_t P8:1; /**< bit: 8 Input Filter Enable */ 968 uint32_t P9:1; /**< bit: 9 Input Filter Enable */ 969 uint32_t P10:1; /**< bit: 10 Input Filter Enable */ 970 uint32_t P11:1; /**< bit: 11 Input Filter Enable */ 971 uint32_t P12:1; /**< bit: 12 Input Filter Enable */ 972 uint32_t P13:1; /**< bit: 13 Input Filter Enable */ 973 uint32_t P14:1; /**< bit: 14 Input Filter Enable */ 974 uint32_t P15:1; /**< bit: 15 Input Filter Enable */ 975 uint32_t P16:1; /**< bit: 16 Input Filter Enable */ 976 uint32_t P17:1; /**< bit: 17 Input Filter Enable */ 977 uint32_t P18:1; /**< bit: 18 Input Filter Enable */ 978 uint32_t P19:1; /**< bit: 19 Input Filter Enable */ 979 uint32_t P20:1; /**< bit: 20 Input Filter Enable */ 980 uint32_t P21:1; /**< bit: 21 Input Filter Enable */ 981 uint32_t P22:1; /**< bit: 22 Input Filter Enable */ 982 uint32_t P23:1; /**< bit: 23 Input Filter Enable */ 983 uint32_t P24:1; /**< bit: 24 Input Filter Enable */ 984 uint32_t P25:1; /**< bit: 25 Input Filter Enable */ 985 uint32_t P26:1; /**< bit: 26 Input Filter Enable */ 986 uint32_t P27:1; /**< bit: 27 Input Filter Enable */ 987 uint32_t P28:1; /**< bit: 28 Input Filter Enable */ 988 uint32_t P29:1; /**< bit: 29 Input Filter Enable */ 989 uint32_t P30:1; /**< bit: 30 Input Filter Enable */ 990 uint32_t P31:1; /**< bit: 31 Input Filter Enable */ 991 } bit; /**< Structure used for bit access */ 992 struct { 993 uint32_t P:32; /**< bit: 0..31 Input Filter Enable */ 994 } vec; /**< Structure used for vec access */ 995 uint32_t reg; /**< Type used for register access */ 996 } PIO_IFER_Type; 997 #endif 998 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 999 1000 #define PIO_IFER_OFFSET (0x20) /**< (PIO_IFER) Glitch Input Filter Enable Register Offset */ 1001 1002 #define PIO_IFER_P0_Pos 0 /**< (PIO_IFER) Input Filter Enable Position */ 1003 #define PIO_IFER_P0_Msk (_U_(0x1) << PIO_IFER_P0_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1004 #define PIO_IFER_P0 PIO_IFER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P0_Msk instead */ 1005 #define PIO_IFER_P1_Pos 1 /**< (PIO_IFER) Input Filter Enable Position */ 1006 #define PIO_IFER_P1_Msk (_U_(0x1) << PIO_IFER_P1_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1007 #define PIO_IFER_P1 PIO_IFER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P1_Msk instead */ 1008 #define PIO_IFER_P2_Pos 2 /**< (PIO_IFER) Input Filter Enable Position */ 1009 #define PIO_IFER_P2_Msk (_U_(0x1) << PIO_IFER_P2_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1010 #define PIO_IFER_P2 PIO_IFER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P2_Msk instead */ 1011 #define PIO_IFER_P3_Pos 3 /**< (PIO_IFER) Input Filter Enable Position */ 1012 #define PIO_IFER_P3_Msk (_U_(0x1) << PIO_IFER_P3_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1013 #define PIO_IFER_P3 PIO_IFER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P3_Msk instead */ 1014 #define PIO_IFER_P4_Pos 4 /**< (PIO_IFER) Input Filter Enable Position */ 1015 #define PIO_IFER_P4_Msk (_U_(0x1) << PIO_IFER_P4_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1016 #define PIO_IFER_P4 PIO_IFER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P4_Msk instead */ 1017 #define PIO_IFER_P5_Pos 5 /**< (PIO_IFER) Input Filter Enable Position */ 1018 #define PIO_IFER_P5_Msk (_U_(0x1) << PIO_IFER_P5_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1019 #define PIO_IFER_P5 PIO_IFER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P5_Msk instead */ 1020 #define PIO_IFER_P6_Pos 6 /**< (PIO_IFER) Input Filter Enable Position */ 1021 #define PIO_IFER_P6_Msk (_U_(0x1) << PIO_IFER_P6_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1022 #define PIO_IFER_P6 PIO_IFER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P6_Msk instead */ 1023 #define PIO_IFER_P7_Pos 7 /**< (PIO_IFER) Input Filter Enable Position */ 1024 #define PIO_IFER_P7_Msk (_U_(0x1) << PIO_IFER_P7_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1025 #define PIO_IFER_P7 PIO_IFER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P7_Msk instead */ 1026 #define PIO_IFER_P8_Pos 8 /**< (PIO_IFER) Input Filter Enable Position */ 1027 #define PIO_IFER_P8_Msk (_U_(0x1) << PIO_IFER_P8_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1028 #define PIO_IFER_P8 PIO_IFER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P8_Msk instead */ 1029 #define PIO_IFER_P9_Pos 9 /**< (PIO_IFER) Input Filter Enable Position */ 1030 #define PIO_IFER_P9_Msk (_U_(0x1) << PIO_IFER_P9_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1031 #define PIO_IFER_P9 PIO_IFER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P9_Msk instead */ 1032 #define PIO_IFER_P10_Pos 10 /**< (PIO_IFER) Input Filter Enable Position */ 1033 #define PIO_IFER_P10_Msk (_U_(0x1) << PIO_IFER_P10_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1034 #define PIO_IFER_P10 PIO_IFER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P10_Msk instead */ 1035 #define PIO_IFER_P11_Pos 11 /**< (PIO_IFER) Input Filter Enable Position */ 1036 #define PIO_IFER_P11_Msk (_U_(0x1) << PIO_IFER_P11_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1037 #define PIO_IFER_P11 PIO_IFER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P11_Msk instead */ 1038 #define PIO_IFER_P12_Pos 12 /**< (PIO_IFER) Input Filter Enable Position */ 1039 #define PIO_IFER_P12_Msk (_U_(0x1) << PIO_IFER_P12_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1040 #define PIO_IFER_P12 PIO_IFER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P12_Msk instead */ 1041 #define PIO_IFER_P13_Pos 13 /**< (PIO_IFER) Input Filter Enable Position */ 1042 #define PIO_IFER_P13_Msk (_U_(0x1) << PIO_IFER_P13_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1043 #define PIO_IFER_P13 PIO_IFER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P13_Msk instead */ 1044 #define PIO_IFER_P14_Pos 14 /**< (PIO_IFER) Input Filter Enable Position */ 1045 #define PIO_IFER_P14_Msk (_U_(0x1) << PIO_IFER_P14_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1046 #define PIO_IFER_P14 PIO_IFER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P14_Msk instead */ 1047 #define PIO_IFER_P15_Pos 15 /**< (PIO_IFER) Input Filter Enable Position */ 1048 #define PIO_IFER_P15_Msk (_U_(0x1) << PIO_IFER_P15_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1049 #define PIO_IFER_P15 PIO_IFER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P15_Msk instead */ 1050 #define PIO_IFER_P16_Pos 16 /**< (PIO_IFER) Input Filter Enable Position */ 1051 #define PIO_IFER_P16_Msk (_U_(0x1) << PIO_IFER_P16_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1052 #define PIO_IFER_P16 PIO_IFER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P16_Msk instead */ 1053 #define PIO_IFER_P17_Pos 17 /**< (PIO_IFER) Input Filter Enable Position */ 1054 #define PIO_IFER_P17_Msk (_U_(0x1) << PIO_IFER_P17_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1055 #define PIO_IFER_P17 PIO_IFER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P17_Msk instead */ 1056 #define PIO_IFER_P18_Pos 18 /**< (PIO_IFER) Input Filter Enable Position */ 1057 #define PIO_IFER_P18_Msk (_U_(0x1) << PIO_IFER_P18_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1058 #define PIO_IFER_P18 PIO_IFER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P18_Msk instead */ 1059 #define PIO_IFER_P19_Pos 19 /**< (PIO_IFER) Input Filter Enable Position */ 1060 #define PIO_IFER_P19_Msk (_U_(0x1) << PIO_IFER_P19_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1061 #define PIO_IFER_P19 PIO_IFER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P19_Msk instead */ 1062 #define PIO_IFER_P20_Pos 20 /**< (PIO_IFER) Input Filter Enable Position */ 1063 #define PIO_IFER_P20_Msk (_U_(0x1) << PIO_IFER_P20_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1064 #define PIO_IFER_P20 PIO_IFER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P20_Msk instead */ 1065 #define PIO_IFER_P21_Pos 21 /**< (PIO_IFER) Input Filter Enable Position */ 1066 #define PIO_IFER_P21_Msk (_U_(0x1) << PIO_IFER_P21_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1067 #define PIO_IFER_P21 PIO_IFER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P21_Msk instead */ 1068 #define PIO_IFER_P22_Pos 22 /**< (PIO_IFER) Input Filter Enable Position */ 1069 #define PIO_IFER_P22_Msk (_U_(0x1) << PIO_IFER_P22_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1070 #define PIO_IFER_P22 PIO_IFER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P22_Msk instead */ 1071 #define PIO_IFER_P23_Pos 23 /**< (PIO_IFER) Input Filter Enable Position */ 1072 #define PIO_IFER_P23_Msk (_U_(0x1) << PIO_IFER_P23_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1073 #define PIO_IFER_P23 PIO_IFER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P23_Msk instead */ 1074 #define PIO_IFER_P24_Pos 24 /**< (PIO_IFER) Input Filter Enable Position */ 1075 #define PIO_IFER_P24_Msk (_U_(0x1) << PIO_IFER_P24_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1076 #define PIO_IFER_P24 PIO_IFER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P24_Msk instead */ 1077 #define PIO_IFER_P25_Pos 25 /**< (PIO_IFER) Input Filter Enable Position */ 1078 #define PIO_IFER_P25_Msk (_U_(0x1) << PIO_IFER_P25_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1079 #define PIO_IFER_P25 PIO_IFER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P25_Msk instead */ 1080 #define PIO_IFER_P26_Pos 26 /**< (PIO_IFER) Input Filter Enable Position */ 1081 #define PIO_IFER_P26_Msk (_U_(0x1) << PIO_IFER_P26_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1082 #define PIO_IFER_P26 PIO_IFER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P26_Msk instead */ 1083 #define PIO_IFER_P27_Pos 27 /**< (PIO_IFER) Input Filter Enable Position */ 1084 #define PIO_IFER_P27_Msk (_U_(0x1) << PIO_IFER_P27_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1085 #define PIO_IFER_P27 PIO_IFER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P27_Msk instead */ 1086 #define PIO_IFER_P28_Pos 28 /**< (PIO_IFER) Input Filter Enable Position */ 1087 #define PIO_IFER_P28_Msk (_U_(0x1) << PIO_IFER_P28_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1088 #define PIO_IFER_P28 PIO_IFER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P28_Msk instead */ 1089 #define PIO_IFER_P29_Pos 29 /**< (PIO_IFER) Input Filter Enable Position */ 1090 #define PIO_IFER_P29_Msk (_U_(0x1) << PIO_IFER_P29_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1091 #define PIO_IFER_P29 PIO_IFER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P29_Msk instead */ 1092 #define PIO_IFER_P30_Pos 30 /**< (PIO_IFER) Input Filter Enable Position */ 1093 #define PIO_IFER_P30_Msk (_U_(0x1) << PIO_IFER_P30_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1094 #define PIO_IFER_P30 PIO_IFER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P30_Msk instead */ 1095 #define PIO_IFER_P31_Pos 31 /**< (PIO_IFER) Input Filter Enable Position */ 1096 #define PIO_IFER_P31_Msk (_U_(0x1) << PIO_IFER_P31_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ 1097 #define PIO_IFER_P31 PIO_IFER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P31_Msk instead */ 1098 #define PIO_IFER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IFER) Register MASK (Use PIO_IFER_Msk instead) */ 1099 #define PIO_IFER_Msk _U_(0xFFFFFFFF) /**< (PIO_IFER) Register Mask */ 1100 1101 #define PIO_IFER_P_Pos 0 /**< (PIO_IFER Position) Input Filter Enable */ 1102 #define PIO_IFER_P_Msk (_U_(0xFFFFFFFF) << PIO_IFER_P_Pos) /**< (PIO_IFER Mask) P */ 1103 #define PIO_IFER_P(value) (PIO_IFER_P_Msk & ((value) << PIO_IFER_P_Pos)) 1104 1105 /* -------- PIO_IFDR : (PIO Offset: 0x24) (/W 32) Glitch Input Filter Disable Register -------- */ 1106 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1107 #if COMPONENT_TYPEDEF_STYLE == 'N' 1108 typedef union { 1109 struct { 1110 uint32_t P0:1; /**< bit: 0 Input Filter Disable */ 1111 uint32_t P1:1; /**< bit: 1 Input Filter Disable */ 1112 uint32_t P2:1; /**< bit: 2 Input Filter Disable */ 1113 uint32_t P3:1; /**< bit: 3 Input Filter Disable */ 1114 uint32_t P4:1; /**< bit: 4 Input Filter Disable */ 1115 uint32_t P5:1; /**< bit: 5 Input Filter Disable */ 1116 uint32_t P6:1; /**< bit: 6 Input Filter Disable */ 1117 uint32_t P7:1; /**< bit: 7 Input Filter Disable */ 1118 uint32_t P8:1; /**< bit: 8 Input Filter Disable */ 1119 uint32_t P9:1; /**< bit: 9 Input Filter Disable */ 1120 uint32_t P10:1; /**< bit: 10 Input Filter Disable */ 1121 uint32_t P11:1; /**< bit: 11 Input Filter Disable */ 1122 uint32_t P12:1; /**< bit: 12 Input Filter Disable */ 1123 uint32_t P13:1; /**< bit: 13 Input Filter Disable */ 1124 uint32_t P14:1; /**< bit: 14 Input Filter Disable */ 1125 uint32_t P15:1; /**< bit: 15 Input Filter Disable */ 1126 uint32_t P16:1; /**< bit: 16 Input Filter Disable */ 1127 uint32_t P17:1; /**< bit: 17 Input Filter Disable */ 1128 uint32_t P18:1; /**< bit: 18 Input Filter Disable */ 1129 uint32_t P19:1; /**< bit: 19 Input Filter Disable */ 1130 uint32_t P20:1; /**< bit: 20 Input Filter Disable */ 1131 uint32_t P21:1; /**< bit: 21 Input Filter Disable */ 1132 uint32_t P22:1; /**< bit: 22 Input Filter Disable */ 1133 uint32_t P23:1; /**< bit: 23 Input Filter Disable */ 1134 uint32_t P24:1; /**< bit: 24 Input Filter Disable */ 1135 uint32_t P25:1; /**< bit: 25 Input Filter Disable */ 1136 uint32_t P26:1; /**< bit: 26 Input Filter Disable */ 1137 uint32_t P27:1; /**< bit: 27 Input Filter Disable */ 1138 uint32_t P28:1; /**< bit: 28 Input Filter Disable */ 1139 uint32_t P29:1; /**< bit: 29 Input Filter Disable */ 1140 uint32_t P30:1; /**< bit: 30 Input Filter Disable */ 1141 uint32_t P31:1; /**< bit: 31 Input Filter Disable */ 1142 } bit; /**< Structure used for bit access */ 1143 struct { 1144 uint32_t P:32; /**< bit: 0..31 Input Filter Disable */ 1145 } vec; /**< Structure used for vec access */ 1146 uint32_t reg; /**< Type used for register access */ 1147 } PIO_IFDR_Type; 1148 #endif 1149 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1150 1151 #define PIO_IFDR_OFFSET (0x24) /**< (PIO_IFDR) Glitch Input Filter Disable Register Offset */ 1152 1153 #define PIO_IFDR_P0_Pos 0 /**< (PIO_IFDR) Input Filter Disable Position */ 1154 #define PIO_IFDR_P0_Msk (_U_(0x1) << PIO_IFDR_P0_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1155 #define PIO_IFDR_P0 PIO_IFDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P0_Msk instead */ 1156 #define PIO_IFDR_P1_Pos 1 /**< (PIO_IFDR) Input Filter Disable Position */ 1157 #define PIO_IFDR_P1_Msk (_U_(0x1) << PIO_IFDR_P1_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1158 #define PIO_IFDR_P1 PIO_IFDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P1_Msk instead */ 1159 #define PIO_IFDR_P2_Pos 2 /**< (PIO_IFDR) Input Filter Disable Position */ 1160 #define PIO_IFDR_P2_Msk (_U_(0x1) << PIO_IFDR_P2_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1161 #define PIO_IFDR_P2 PIO_IFDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P2_Msk instead */ 1162 #define PIO_IFDR_P3_Pos 3 /**< (PIO_IFDR) Input Filter Disable Position */ 1163 #define PIO_IFDR_P3_Msk (_U_(0x1) << PIO_IFDR_P3_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1164 #define PIO_IFDR_P3 PIO_IFDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P3_Msk instead */ 1165 #define PIO_IFDR_P4_Pos 4 /**< (PIO_IFDR) Input Filter Disable Position */ 1166 #define PIO_IFDR_P4_Msk (_U_(0x1) << PIO_IFDR_P4_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1167 #define PIO_IFDR_P4 PIO_IFDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P4_Msk instead */ 1168 #define PIO_IFDR_P5_Pos 5 /**< (PIO_IFDR) Input Filter Disable Position */ 1169 #define PIO_IFDR_P5_Msk (_U_(0x1) << PIO_IFDR_P5_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1170 #define PIO_IFDR_P5 PIO_IFDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P5_Msk instead */ 1171 #define PIO_IFDR_P6_Pos 6 /**< (PIO_IFDR) Input Filter Disable Position */ 1172 #define PIO_IFDR_P6_Msk (_U_(0x1) << PIO_IFDR_P6_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1173 #define PIO_IFDR_P6 PIO_IFDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P6_Msk instead */ 1174 #define PIO_IFDR_P7_Pos 7 /**< (PIO_IFDR) Input Filter Disable Position */ 1175 #define PIO_IFDR_P7_Msk (_U_(0x1) << PIO_IFDR_P7_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1176 #define PIO_IFDR_P7 PIO_IFDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P7_Msk instead */ 1177 #define PIO_IFDR_P8_Pos 8 /**< (PIO_IFDR) Input Filter Disable Position */ 1178 #define PIO_IFDR_P8_Msk (_U_(0x1) << PIO_IFDR_P8_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1179 #define PIO_IFDR_P8 PIO_IFDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P8_Msk instead */ 1180 #define PIO_IFDR_P9_Pos 9 /**< (PIO_IFDR) Input Filter Disable Position */ 1181 #define PIO_IFDR_P9_Msk (_U_(0x1) << PIO_IFDR_P9_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1182 #define PIO_IFDR_P9 PIO_IFDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P9_Msk instead */ 1183 #define PIO_IFDR_P10_Pos 10 /**< (PIO_IFDR) Input Filter Disable Position */ 1184 #define PIO_IFDR_P10_Msk (_U_(0x1) << PIO_IFDR_P10_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1185 #define PIO_IFDR_P10 PIO_IFDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P10_Msk instead */ 1186 #define PIO_IFDR_P11_Pos 11 /**< (PIO_IFDR) Input Filter Disable Position */ 1187 #define PIO_IFDR_P11_Msk (_U_(0x1) << PIO_IFDR_P11_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1188 #define PIO_IFDR_P11 PIO_IFDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P11_Msk instead */ 1189 #define PIO_IFDR_P12_Pos 12 /**< (PIO_IFDR) Input Filter Disable Position */ 1190 #define PIO_IFDR_P12_Msk (_U_(0x1) << PIO_IFDR_P12_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1191 #define PIO_IFDR_P12 PIO_IFDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P12_Msk instead */ 1192 #define PIO_IFDR_P13_Pos 13 /**< (PIO_IFDR) Input Filter Disable Position */ 1193 #define PIO_IFDR_P13_Msk (_U_(0x1) << PIO_IFDR_P13_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1194 #define PIO_IFDR_P13 PIO_IFDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P13_Msk instead */ 1195 #define PIO_IFDR_P14_Pos 14 /**< (PIO_IFDR) Input Filter Disable Position */ 1196 #define PIO_IFDR_P14_Msk (_U_(0x1) << PIO_IFDR_P14_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1197 #define PIO_IFDR_P14 PIO_IFDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P14_Msk instead */ 1198 #define PIO_IFDR_P15_Pos 15 /**< (PIO_IFDR) Input Filter Disable Position */ 1199 #define PIO_IFDR_P15_Msk (_U_(0x1) << PIO_IFDR_P15_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1200 #define PIO_IFDR_P15 PIO_IFDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P15_Msk instead */ 1201 #define PIO_IFDR_P16_Pos 16 /**< (PIO_IFDR) Input Filter Disable Position */ 1202 #define PIO_IFDR_P16_Msk (_U_(0x1) << PIO_IFDR_P16_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1203 #define PIO_IFDR_P16 PIO_IFDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P16_Msk instead */ 1204 #define PIO_IFDR_P17_Pos 17 /**< (PIO_IFDR) Input Filter Disable Position */ 1205 #define PIO_IFDR_P17_Msk (_U_(0x1) << PIO_IFDR_P17_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1206 #define PIO_IFDR_P17 PIO_IFDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P17_Msk instead */ 1207 #define PIO_IFDR_P18_Pos 18 /**< (PIO_IFDR) Input Filter Disable Position */ 1208 #define PIO_IFDR_P18_Msk (_U_(0x1) << PIO_IFDR_P18_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1209 #define PIO_IFDR_P18 PIO_IFDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P18_Msk instead */ 1210 #define PIO_IFDR_P19_Pos 19 /**< (PIO_IFDR) Input Filter Disable Position */ 1211 #define PIO_IFDR_P19_Msk (_U_(0x1) << PIO_IFDR_P19_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1212 #define PIO_IFDR_P19 PIO_IFDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P19_Msk instead */ 1213 #define PIO_IFDR_P20_Pos 20 /**< (PIO_IFDR) Input Filter Disable Position */ 1214 #define PIO_IFDR_P20_Msk (_U_(0x1) << PIO_IFDR_P20_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1215 #define PIO_IFDR_P20 PIO_IFDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P20_Msk instead */ 1216 #define PIO_IFDR_P21_Pos 21 /**< (PIO_IFDR) Input Filter Disable Position */ 1217 #define PIO_IFDR_P21_Msk (_U_(0x1) << PIO_IFDR_P21_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1218 #define PIO_IFDR_P21 PIO_IFDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P21_Msk instead */ 1219 #define PIO_IFDR_P22_Pos 22 /**< (PIO_IFDR) Input Filter Disable Position */ 1220 #define PIO_IFDR_P22_Msk (_U_(0x1) << PIO_IFDR_P22_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1221 #define PIO_IFDR_P22 PIO_IFDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P22_Msk instead */ 1222 #define PIO_IFDR_P23_Pos 23 /**< (PIO_IFDR) Input Filter Disable Position */ 1223 #define PIO_IFDR_P23_Msk (_U_(0x1) << PIO_IFDR_P23_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1224 #define PIO_IFDR_P23 PIO_IFDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P23_Msk instead */ 1225 #define PIO_IFDR_P24_Pos 24 /**< (PIO_IFDR) Input Filter Disable Position */ 1226 #define PIO_IFDR_P24_Msk (_U_(0x1) << PIO_IFDR_P24_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1227 #define PIO_IFDR_P24 PIO_IFDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P24_Msk instead */ 1228 #define PIO_IFDR_P25_Pos 25 /**< (PIO_IFDR) Input Filter Disable Position */ 1229 #define PIO_IFDR_P25_Msk (_U_(0x1) << PIO_IFDR_P25_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1230 #define PIO_IFDR_P25 PIO_IFDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P25_Msk instead */ 1231 #define PIO_IFDR_P26_Pos 26 /**< (PIO_IFDR) Input Filter Disable Position */ 1232 #define PIO_IFDR_P26_Msk (_U_(0x1) << PIO_IFDR_P26_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1233 #define PIO_IFDR_P26 PIO_IFDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P26_Msk instead */ 1234 #define PIO_IFDR_P27_Pos 27 /**< (PIO_IFDR) Input Filter Disable Position */ 1235 #define PIO_IFDR_P27_Msk (_U_(0x1) << PIO_IFDR_P27_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1236 #define PIO_IFDR_P27 PIO_IFDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P27_Msk instead */ 1237 #define PIO_IFDR_P28_Pos 28 /**< (PIO_IFDR) Input Filter Disable Position */ 1238 #define PIO_IFDR_P28_Msk (_U_(0x1) << PIO_IFDR_P28_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1239 #define PIO_IFDR_P28 PIO_IFDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P28_Msk instead */ 1240 #define PIO_IFDR_P29_Pos 29 /**< (PIO_IFDR) Input Filter Disable Position */ 1241 #define PIO_IFDR_P29_Msk (_U_(0x1) << PIO_IFDR_P29_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1242 #define PIO_IFDR_P29 PIO_IFDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P29_Msk instead */ 1243 #define PIO_IFDR_P30_Pos 30 /**< (PIO_IFDR) Input Filter Disable Position */ 1244 #define PIO_IFDR_P30_Msk (_U_(0x1) << PIO_IFDR_P30_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1245 #define PIO_IFDR_P30 PIO_IFDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P30_Msk instead */ 1246 #define PIO_IFDR_P31_Pos 31 /**< (PIO_IFDR) Input Filter Disable Position */ 1247 #define PIO_IFDR_P31_Msk (_U_(0x1) << PIO_IFDR_P31_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ 1248 #define PIO_IFDR_P31 PIO_IFDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P31_Msk instead */ 1249 #define PIO_IFDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IFDR) Register MASK (Use PIO_IFDR_Msk instead) */ 1250 #define PIO_IFDR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFDR) Register Mask */ 1251 1252 #define PIO_IFDR_P_Pos 0 /**< (PIO_IFDR Position) Input Filter Disable */ 1253 #define PIO_IFDR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFDR_P_Pos) /**< (PIO_IFDR Mask) P */ 1254 #define PIO_IFDR_P(value) (PIO_IFDR_P_Msk & ((value) << PIO_IFDR_P_Pos)) 1255 1256 /* -------- PIO_IFSR : (PIO Offset: 0x28) (R/ 32) Glitch Input Filter Status Register -------- */ 1257 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1258 #if COMPONENT_TYPEDEF_STYLE == 'N' 1259 typedef union { 1260 struct { 1261 uint32_t P0:1; /**< bit: 0 Input Filter Status */ 1262 uint32_t P1:1; /**< bit: 1 Input Filter Status */ 1263 uint32_t P2:1; /**< bit: 2 Input Filter Status */ 1264 uint32_t P3:1; /**< bit: 3 Input Filter Status */ 1265 uint32_t P4:1; /**< bit: 4 Input Filter Status */ 1266 uint32_t P5:1; /**< bit: 5 Input Filter Status */ 1267 uint32_t P6:1; /**< bit: 6 Input Filter Status */ 1268 uint32_t P7:1; /**< bit: 7 Input Filter Status */ 1269 uint32_t P8:1; /**< bit: 8 Input Filter Status */ 1270 uint32_t P9:1; /**< bit: 9 Input Filter Status */ 1271 uint32_t P10:1; /**< bit: 10 Input Filter Status */ 1272 uint32_t P11:1; /**< bit: 11 Input Filter Status */ 1273 uint32_t P12:1; /**< bit: 12 Input Filter Status */ 1274 uint32_t P13:1; /**< bit: 13 Input Filter Status */ 1275 uint32_t P14:1; /**< bit: 14 Input Filter Status */ 1276 uint32_t P15:1; /**< bit: 15 Input Filter Status */ 1277 uint32_t P16:1; /**< bit: 16 Input Filter Status */ 1278 uint32_t P17:1; /**< bit: 17 Input Filter Status */ 1279 uint32_t P18:1; /**< bit: 18 Input Filter Status */ 1280 uint32_t P19:1; /**< bit: 19 Input Filter Status */ 1281 uint32_t P20:1; /**< bit: 20 Input Filter Status */ 1282 uint32_t P21:1; /**< bit: 21 Input Filter Status */ 1283 uint32_t P22:1; /**< bit: 22 Input Filter Status */ 1284 uint32_t P23:1; /**< bit: 23 Input Filter Status */ 1285 uint32_t P24:1; /**< bit: 24 Input Filter Status */ 1286 uint32_t P25:1; /**< bit: 25 Input Filter Status */ 1287 uint32_t P26:1; /**< bit: 26 Input Filter Status */ 1288 uint32_t P27:1; /**< bit: 27 Input Filter Status */ 1289 uint32_t P28:1; /**< bit: 28 Input Filter Status */ 1290 uint32_t P29:1; /**< bit: 29 Input Filter Status */ 1291 uint32_t P30:1; /**< bit: 30 Input Filter Status */ 1292 uint32_t P31:1; /**< bit: 31 Input Filter Status */ 1293 } bit; /**< Structure used for bit access */ 1294 struct { 1295 uint32_t P:32; /**< bit: 0..31 Input Filter Status */ 1296 } vec; /**< Structure used for vec access */ 1297 uint32_t reg; /**< Type used for register access */ 1298 } PIO_IFSR_Type; 1299 #endif 1300 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1301 1302 #define PIO_IFSR_OFFSET (0x28) /**< (PIO_IFSR) Glitch Input Filter Status Register Offset */ 1303 1304 #define PIO_IFSR_P0_Pos 0 /**< (PIO_IFSR) Input Filter Status Position */ 1305 #define PIO_IFSR_P0_Msk (_U_(0x1) << PIO_IFSR_P0_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1306 #define PIO_IFSR_P0 PIO_IFSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P0_Msk instead */ 1307 #define PIO_IFSR_P1_Pos 1 /**< (PIO_IFSR) Input Filter Status Position */ 1308 #define PIO_IFSR_P1_Msk (_U_(0x1) << PIO_IFSR_P1_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1309 #define PIO_IFSR_P1 PIO_IFSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P1_Msk instead */ 1310 #define PIO_IFSR_P2_Pos 2 /**< (PIO_IFSR) Input Filter Status Position */ 1311 #define PIO_IFSR_P2_Msk (_U_(0x1) << PIO_IFSR_P2_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1312 #define PIO_IFSR_P2 PIO_IFSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P2_Msk instead */ 1313 #define PIO_IFSR_P3_Pos 3 /**< (PIO_IFSR) Input Filter Status Position */ 1314 #define PIO_IFSR_P3_Msk (_U_(0x1) << PIO_IFSR_P3_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1315 #define PIO_IFSR_P3 PIO_IFSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P3_Msk instead */ 1316 #define PIO_IFSR_P4_Pos 4 /**< (PIO_IFSR) Input Filter Status Position */ 1317 #define PIO_IFSR_P4_Msk (_U_(0x1) << PIO_IFSR_P4_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1318 #define PIO_IFSR_P4 PIO_IFSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P4_Msk instead */ 1319 #define PIO_IFSR_P5_Pos 5 /**< (PIO_IFSR) Input Filter Status Position */ 1320 #define PIO_IFSR_P5_Msk (_U_(0x1) << PIO_IFSR_P5_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1321 #define PIO_IFSR_P5 PIO_IFSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P5_Msk instead */ 1322 #define PIO_IFSR_P6_Pos 6 /**< (PIO_IFSR) Input Filter Status Position */ 1323 #define PIO_IFSR_P6_Msk (_U_(0x1) << PIO_IFSR_P6_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1324 #define PIO_IFSR_P6 PIO_IFSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P6_Msk instead */ 1325 #define PIO_IFSR_P7_Pos 7 /**< (PIO_IFSR) Input Filter Status Position */ 1326 #define PIO_IFSR_P7_Msk (_U_(0x1) << PIO_IFSR_P7_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1327 #define PIO_IFSR_P7 PIO_IFSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P7_Msk instead */ 1328 #define PIO_IFSR_P8_Pos 8 /**< (PIO_IFSR) Input Filter Status Position */ 1329 #define PIO_IFSR_P8_Msk (_U_(0x1) << PIO_IFSR_P8_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1330 #define PIO_IFSR_P8 PIO_IFSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P8_Msk instead */ 1331 #define PIO_IFSR_P9_Pos 9 /**< (PIO_IFSR) Input Filter Status Position */ 1332 #define PIO_IFSR_P9_Msk (_U_(0x1) << PIO_IFSR_P9_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1333 #define PIO_IFSR_P9 PIO_IFSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P9_Msk instead */ 1334 #define PIO_IFSR_P10_Pos 10 /**< (PIO_IFSR) Input Filter Status Position */ 1335 #define PIO_IFSR_P10_Msk (_U_(0x1) << PIO_IFSR_P10_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1336 #define PIO_IFSR_P10 PIO_IFSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P10_Msk instead */ 1337 #define PIO_IFSR_P11_Pos 11 /**< (PIO_IFSR) Input Filter Status Position */ 1338 #define PIO_IFSR_P11_Msk (_U_(0x1) << PIO_IFSR_P11_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1339 #define PIO_IFSR_P11 PIO_IFSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P11_Msk instead */ 1340 #define PIO_IFSR_P12_Pos 12 /**< (PIO_IFSR) Input Filter Status Position */ 1341 #define PIO_IFSR_P12_Msk (_U_(0x1) << PIO_IFSR_P12_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1342 #define PIO_IFSR_P12 PIO_IFSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P12_Msk instead */ 1343 #define PIO_IFSR_P13_Pos 13 /**< (PIO_IFSR) Input Filter Status Position */ 1344 #define PIO_IFSR_P13_Msk (_U_(0x1) << PIO_IFSR_P13_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1345 #define PIO_IFSR_P13 PIO_IFSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P13_Msk instead */ 1346 #define PIO_IFSR_P14_Pos 14 /**< (PIO_IFSR) Input Filter Status Position */ 1347 #define PIO_IFSR_P14_Msk (_U_(0x1) << PIO_IFSR_P14_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1348 #define PIO_IFSR_P14 PIO_IFSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P14_Msk instead */ 1349 #define PIO_IFSR_P15_Pos 15 /**< (PIO_IFSR) Input Filter Status Position */ 1350 #define PIO_IFSR_P15_Msk (_U_(0x1) << PIO_IFSR_P15_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1351 #define PIO_IFSR_P15 PIO_IFSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P15_Msk instead */ 1352 #define PIO_IFSR_P16_Pos 16 /**< (PIO_IFSR) Input Filter Status Position */ 1353 #define PIO_IFSR_P16_Msk (_U_(0x1) << PIO_IFSR_P16_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1354 #define PIO_IFSR_P16 PIO_IFSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P16_Msk instead */ 1355 #define PIO_IFSR_P17_Pos 17 /**< (PIO_IFSR) Input Filter Status Position */ 1356 #define PIO_IFSR_P17_Msk (_U_(0x1) << PIO_IFSR_P17_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1357 #define PIO_IFSR_P17 PIO_IFSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P17_Msk instead */ 1358 #define PIO_IFSR_P18_Pos 18 /**< (PIO_IFSR) Input Filter Status Position */ 1359 #define PIO_IFSR_P18_Msk (_U_(0x1) << PIO_IFSR_P18_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1360 #define PIO_IFSR_P18 PIO_IFSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P18_Msk instead */ 1361 #define PIO_IFSR_P19_Pos 19 /**< (PIO_IFSR) Input Filter Status Position */ 1362 #define PIO_IFSR_P19_Msk (_U_(0x1) << PIO_IFSR_P19_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1363 #define PIO_IFSR_P19 PIO_IFSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P19_Msk instead */ 1364 #define PIO_IFSR_P20_Pos 20 /**< (PIO_IFSR) Input Filter Status Position */ 1365 #define PIO_IFSR_P20_Msk (_U_(0x1) << PIO_IFSR_P20_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1366 #define PIO_IFSR_P20 PIO_IFSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P20_Msk instead */ 1367 #define PIO_IFSR_P21_Pos 21 /**< (PIO_IFSR) Input Filter Status Position */ 1368 #define PIO_IFSR_P21_Msk (_U_(0x1) << PIO_IFSR_P21_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1369 #define PIO_IFSR_P21 PIO_IFSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P21_Msk instead */ 1370 #define PIO_IFSR_P22_Pos 22 /**< (PIO_IFSR) Input Filter Status Position */ 1371 #define PIO_IFSR_P22_Msk (_U_(0x1) << PIO_IFSR_P22_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1372 #define PIO_IFSR_P22 PIO_IFSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P22_Msk instead */ 1373 #define PIO_IFSR_P23_Pos 23 /**< (PIO_IFSR) Input Filter Status Position */ 1374 #define PIO_IFSR_P23_Msk (_U_(0x1) << PIO_IFSR_P23_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1375 #define PIO_IFSR_P23 PIO_IFSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P23_Msk instead */ 1376 #define PIO_IFSR_P24_Pos 24 /**< (PIO_IFSR) Input Filter Status Position */ 1377 #define PIO_IFSR_P24_Msk (_U_(0x1) << PIO_IFSR_P24_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1378 #define PIO_IFSR_P24 PIO_IFSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P24_Msk instead */ 1379 #define PIO_IFSR_P25_Pos 25 /**< (PIO_IFSR) Input Filter Status Position */ 1380 #define PIO_IFSR_P25_Msk (_U_(0x1) << PIO_IFSR_P25_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1381 #define PIO_IFSR_P25 PIO_IFSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P25_Msk instead */ 1382 #define PIO_IFSR_P26_Pos 26 /**< (PIO_IFSR) Input Filter Status Position */ 1383 #define PIO_IFSR_P26_Msk (_U_(0x1) << PIO_IFSR_P26_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1384 #define PIO_IFSR_P26 PIO_IFSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P26_Msk instead */ 1385 #define PIO_IFSR_P27_Pos 27 /**< (PIO_IFSR) Input Filter Status Position */ 1386 #define PIO_IFSR_P27_Msk (_U_(0x1) << PIO_IFSR_P27_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1387 #define PIO_IFSR_P27 PIO_IFSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P27_Msk instead */ 1388 #define PIO_IFSR_P28_Pos 28 /**< (PIO_IFSR) Input Filter Status Position */ 1389 #define PIO_IFSR_P28_Msk (_U_(0x1) << PIO_IFSR_P28_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1390 #define PIO_IFSR_P28 PIO_IFSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P28_Msk instead */ 1391 #define PIO_IFSR_P29_Pos 29 /**< (PIO_IFSR) Input Filter Status Position */ 1392 #define PIO_IFSR_P29_Msk (_U_(0x1) << PIO_IFSR_P29_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1393 #define PIO_IFSR_P29 PIO_IFSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P29_Msk instead */ 1394 #define PIO_IFSR_P30_Pos 30 /**< (PIO_IFSR) Input Filter Status Position */ 1395 #define PIO_IFSR_P30_Msk (_U_(0x1) << PIO_IFSR_P30_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1396 #define PIO_IFSR_P30 PIO_IFSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P30_Msk instead */ 1397 #define PIO_IFSR_P31_Pos 31 /**< (PIO_IFSR) Input Filter Status Position */ 1398 #define PIO_IFSR_P31_Msk (_U_(0x1) << PIO_IFSR_P31_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ 1399 #define PIO_IFSR_P31 PIO_IFSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P31_Msk instead */ 1400 #define PIO_IFSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IFSR) Register MASK (Use PIO_IFSR_Msk instead) */ 1401 #define PIO_IFSR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSR) Register Mask */ 1402 1403 #define PIO_IFSR_P_Pos 0 /**< (PIO_IFSR Position) Input Filter Status */ 1404 #define PIO_IFSR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSR_P_Pos) /**< (PIO_IFSR Mask) P */ 1405 #define PIO_IFSR_P(value) (PIO_IFSR_P_Msk & ((value) << PIO_IFSR_P_Pos)) 1406 1407 /* -------- PIO_SODR : (PIO Offset: 0x30) (/W 32) Set Output Data Register -------- */ 1408 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1409 #if COMPONENT_TYPEDEF_STYLE == 'N' 1410 typedef union { 1411 struct { 1412 uint32_t P0:1; /**< bit: 0 Set Output Data */ 1413 uint32_t P1:1; /**< bit: 1 Set Output Data */ 1414 uint32_t P2:1; /**< bit: 2 Set Output Data */ 1415 uint32_t P3:1; /**< bit: 3 Set Output Data */ 1416 uint32_t P4:1; /**< bit: 4 Set Output Data */ 1417 uint32_t P5:1; /**< bit: 5 Set Output Data */ 1418 uint32_t P6:1; /**< bit: 6 Set Output Data */ 1419 uint32_t P7:1; /**< bit: 7 Set Output Data */ 1420 uint32_t P8:1; /**< bit: 8 Set Output Data */ 1421 uint32_t P9:1; /**< bit: 9 Set Output Data */ 1422 uint32_t P10:1; /**< bit: 10 Set Output Data */ 1423 uint32_t P11:1; /**< bit: 11 Set Output Data */ 1424 uint32_t P12:1; /**< bit: 12 Set Output Data */ 1425 uint32_t P13:1; /**< bit: 13 Set Output Data */ 1426 uint32_t P14:1; /**< bit: 14 Set Output Data */ 1427 uint32_t P15:1; /**< bit: 15 Set Output Data */ 1428 uint32_t P16:1; /**< bit: 16 Set Output Data */ 1429 uint32_t P17:1; /**< bit: 17 Set Output Data */ 1430 uint32_t P18:1; /**< bit: 18 Set Output Data */ 1431 uint32_t P19:1; /**< bit: 19 Set Output Data */ 1432 uint32_t P20:1; /**< bit: 20 Set Output Data */ 1433 uint32_t P21:1; /**< bit: 21 Set Output Data */ 1434 uint32_t P22:1; /**< bit: 22 Set Output Data */ 1435 uint32_t P23:1; /**< bit: 23 Set Output Data */ 1436 uint32_t P24:1; /**< bit: 24 Set Output Data */ 1437 uint32_t P25:1; /**< bit: 25 Set Output Data */ 1438 uint32_t P26:1; /**< bit: 26 Set Output Data */ 1439 uint32_t P27:1; /**< bit: 27 Set Output Data */ 1440 uint32_t P28:1; /**< bit: 28 Set Output Data */ 1441 uint32_t P29:1; /**< bit: 29 Set Output Data */ 1442 uint32_t P30:1; /**< bit: 30 Set Output Data */ 1443 uint32_t P31:1; /**< bit: 31 Set Output Data */ 1444 } bit; /**< Structure used for bit access */ 1445 struct { 1446 uint32_t P:32; /**< bit: 0..31 Set Output Data */ 1447 } vec; /**< Structure used for vec access */ 1448 uint32_t reg; /**< Type used for register access */ 1449 } PIO_SODR_Type; 1450 #endif 1451 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1452 1453 #define PIO_SODR_OFFSET (0x30) /**< (PIO_SODR) Set Output Data Register Offset */ 1454 1455 #define PIO_SODR_P0_Pos 0 /**< (PIO_SODR) Set Output Data Position */ 1456 #define PIO_SODR_P0_Msk (_U_(0x1) << PIO_SODR_P0_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1457 #define PIO_SODR_P0 PIO_SODR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P0_Msk instead */ 1458 #define PIO_SODR_P1_Pos 1 /**< (PIO_SODR) Set Output Data Position */ 1459 #define PIO_SODR_P1_Msk (_U_(0x1) << PIO_SODR_P1_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1460 #define PIO_SODR_P1 PIO_SODR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P1_Msk instead */ 1461 #define PIO_SODR_P2_Pos 2 /**< (PIO_SODR) Set Output Data Position */ 1462 #define PIO_SODR_P2_Msk (_U_(0x1) << PIO_SODR_P2_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1463 #define PIO_SODR_P2 PIO_SODR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P2_Msk instead */ 1464 #define PIO_SODR_P3_Pos 3 /**< (PIO_SODR) Set Output Data Position */ 1465 #define PIO_SODR_P3_Msk (_U_(0x1) << PIO_SODR_P3_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1466 #define PIO_SODR_P3 PIO_SODR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P3_Msk instead */ 1467 #define PIO_SODR_P4_Pos 4 /**< (PIO_SODR) Set Output Data Position */ 1468 #define PIO_SODR_P4_Msk (_U_(0x1) << PIO_SODR_P4_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1469 #define PIO_SODR_P4 PIO_SODR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P4_Msk instead */ 1470 #define PIO_SODR_P5_Pos 5 /**< (PIO_SODR) Set Output Data Position */ 1471 #define PIO_SODR_P5_Msk (_U_(0x1) << PIO_SODR_P5_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1472 #define PIO_SODR_P5 PIO_SODR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P5_Msk instead */ 1473 #define PIO_SODR_P6_Pos 6 /**< (PIO_SODR) Set Output Data Position */ 1474 #define PIO_SODR_P6_Msk (_U_(0x1) << PIO_SODR_P6_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1475 #define PIO_SODR_P6 PIO_SODR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P6_Msk instead */ 1476 #define PIO_SODR_P7_Pos 7 /**< (PIO_SODR) Set Output Data Position */ 1477 #define PIO_SODR_P7_Msk (_U_(0x1) << PIO_SODR_P7_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1478 #define PIO_SODR_P7 PIO_SODR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P7_Msk instead */ 1479 #define PIO_SODR_P8_Pos 8 /**< (PIO_SODR) Set Output Data Position */ 1480 #define PIO_SODR_P8_Msk (_U_(0x1) << PIO_SODR_P8_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1481 #define PIO_SODR_P8 PIO_SODR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P8_Msk instead */ 1482 #define PIO_SODR_P9_Pos 9 /**< (PIO_SODR) Set Output Data Position */ 1483 #define PIO_SODR_P9_Msk (_U_(0x1) << PIO_SODR_P9_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1484 #define PIO_SODR_P9 PIO_SODR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P9_Msk instead */ 1485 #define PIO_SODR_P10_Pos 10 /**< (PIO_SODR) Set Output Data Position */ 1486 #define PIO_SODR_P10_Msk (_U_(0x1) << PIO_SODR_P10_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1487 #define PIO_SODR_P10 PIO_SODR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P10_Msk instead */ 1488 #define PIO_SODR_P11_Pos 11 /**< (PIO_SODR) Set Output Data Position */ 1489 #define PIO_SODR_P11_Msk (_U_(0x1) << PIO_SODR_P11_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1490 #define PIO_SODR_P11 PIO_SODR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P11_Msk instead */ 1491 #define PIO_SODR_P12_Pos 12 /**< (PIO_SODR) Set Output Data Position */ 1492 #define PIO_SODR_P12_Msk (_U_(0x1) << PIO_SODR_P12_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1493 #define PIO_SODR_P12 PIO_SODR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P12_Msk instead */ 1494 #define PIO_SODR_P13_Pos 13 /**< (PIO_SODR) Set Output Data Position */ 1495 #define PIO_SODR_P13_Msk (_U_(0x1) << PIO_SODR_P13_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1496 #define PIO_SODR_P13 PIO_SODR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P13_Msk instead */ 1497 #define PIO_SODR_P14_Pos 14 /**< (PIO_SODR) Set Output Data Position */ 1498 #define PIO_SODR_P14_Msk (_U_(0x1) << PIO_SODR_P14_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1499 #define PIO_SODR_P14 PIO_SODR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P14_Msk instead */ 1500 #define PIO_SODR_P15_Pos 15 /**< (PIO_SODR) Set Output Data Position */ 1501 #define PIO_SODR_P15_Msk (_U_(0x1) << PIO_SODR_P15_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1502 #define PIO_SODR_P15 PIO_SODR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P15_Msk instead */ 1503 #define PIO_SODR_P16_Pos 16 /**< (PIO_SODR) Set Output Data Position */ 1504 #define PIO_SODR_P16_Msk (_U_(0x1) << PIO_SODR_P16_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1505 #define PIO_SODR_P16 PIO_SODR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P16_Msk instead */ 1506 #define PIO_SODR_P17_Pos 17 /**< (PIO_SODR) Set Output Data Position */ 1507 #define PIO_SODR_P17_Msk (_U_(0x1) << PIO_SODR_P17_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1508 #define PIO_SODR_P17 PIO_SODR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P17_Msk instead */ 1509 #define PIO_SODR_P18_Pos 18 /**< (PIO_SODR) Set Output Data Position */ 1510 #define PIO_SODR_P18_Msk (_U_(0x1) << PIO_SODR_P18_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1511 #define PIO_SODR_P18 PIO_SODR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P18_Msk instead */ 1512 #define PIO_SODR_P19_Pos 19 /**< (PIO_SODR) Set Output Data Position */ 1513 #define PIO_SODR_P19_Msk (_U_(0x1) << PIO_SODR_P19_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1514 #define PIO_SODR_P19 PIO_SODR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P19_Msk instead */ 1515 #define PIO_SODR_P20_Pos 20 /**< (PIO_SODR) Set Output Data Position */ 1516 #define PIO_SODR_P20_Msk (_U_(0x1) << PIO_SODR_P20_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1517 #define PIO_SODR_P20 PIO_SODR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P20_Msk instead */ 1518 #define PIO_SODR_P21_Pos 21 /**< (PIO_SODR) Set Output Data Position */ 1519 #define PIO_SODR_P21_Msk (_U_(0x1) << PIO_SODR_P21_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1520 #define PIO_SODR_P21 PIO_SODR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P21_Msk instead */ 1521 #define PIO_SODR_P22_Pos 22 /**< (PIO_SODR) Set Output Data Position */ 1522 #define PIO_SODR_P22_Msk (_U_(0x1) << PIO_SODR_P22_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1523 #define PIO_SODR_P22 PIO_SODR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P22_Msk instead */ 1524 #define PIO_SODR_P23_Pos 23 /**< (PIO_SODR) Set Output Data Position */ 1525 #define PIO_SODR_P23_Msk (_U_(0x1) << PIO_SODR_P23_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1526 #define PIO_SODR_P23 PIO_SODR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P23_Msk instead */ 1527 #define PIO_SODR_P24_Pos 24 /**< (PIO_SODR) Set Output Data Position */ 1528 #define PIO_SODR_P24_Msk (_U_(0x1) << PIO_SODR_P24_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1529 #define PIO_SODR_P24 PIO_SODR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P24_Msk instead */ 1530 #define PIO_SODR_P25_Pos 25 /**< (PIO_SODR) Set Output Data Position */ 1531 #define PIO_SODR_P25_Msk (_U_(0x1) << PIO_SODR_P25_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1532 #define PIO_SODR_P25 PIO_SODR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P25_Msk instead */ 1533 #define PIO_SODR_P26_Pos 26 /**< (PIO_SODR) Set Output Data Position */ 1534 #define PIO_SODR_P26_Msk (_U_(0x1) << PIO_SODR_P26_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1535 #define PIO_SODR_P26 PIO_SODR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P26_Msk instead */ 1536 #define PIO_SODR_P27_Pos 27 /**< (PIO_SODR) Set Output Data Position */ 1537 #define PIO_SODR_P27_Msk (_U_(0x1) << PIO_SODR_P27_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1538 #define PIO_SODR_P27 PIO_SODR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P27_Msk instead */ 1539 #define PIO_SODR_P28_Pos 28 /**< (PIO_SODR) Set Output Data Position */ 1540 #define PIO_SODR_P28_Msk (_U_(0x1) << PIO_SODR_P28_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1541 #define PIO_SODR_P28 PIO_SODR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P28_Msk instead */ 1542 #define PIO_SODR_P29_Pos 29 /**< (PIO_SODR) Set Output Data Position */ 1543 #define PIO_SODR_P29_Msk (_U_(0x1) << PIO_SODR_P29_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1544 #define PIO_SODR_P29 PIO_SODR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P29_Msk instead */ 1545 #define PIO_SODR_P30_Pos 30 /**< (PIO_SODR) Set Output Data Position */ 1546 #define PIO_SODR_P30_Msk (_U_(0x1) << PIO_SODR_P30_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1547 #define PIO_SODR_P30 PIO_SODR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P30_Msk instead */ 1548 #define PIO_SODR_P31_Pos 31 /**< (PIO_SODR) Set Output Data Position */ 1549 #define PIO_SODR_P31_Msk (_U_(0x1) << PIO_SODR_P31_Pos) /**< (PIO_SODR) Set Output Data Mask */ 1550 #define PIO_SODR_P31 PIO_SODR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P31_Msk instead */ 1551 #define PIO_SODR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_SODR) Register MASK (Use PIO_SODR_Msk instead) */ 1552 #define PIO_SODR_Msk _U_(0xFFFFFFFF) /**< (PIO_SODR) Register Mask */ 1553 1554 #define PIO_SODR_P_Pos 0 /**< (PIO_SODR Position) Set Output Data */ 1555 #define PIO_SODR_P_Msk (_U_(0xFFFFFFFF) << PIO_SODR_P_Pos) /**< (PIO_SODR Mask) P */ 1556 #define PIO_SODR_P(value) (PIO_SODR_P_Msk & ((value) << PIO_SODR_P_Pos)) 1557 1558 /* -------- PIO_CODR : (PIO Offset: 0x34) (/W 32) Clear Output Data Register -------- */ 1559 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1560 #if COMPONENT_TYPEDEF_STYLE == 'N' 1561 typedef union { 1562 struct { 1563 uint32_t P0:1; /**< bit: 0 Clear Output Data */ 1564 uint32_t P1:1; /**< bit: 1 Clear Output Data */ 1565 uint32_t P2:1; /**< bit: 2 Clear Output Data */ 1566 uint32_t P3:1; /**< bit: 3 Clear Output Data */ 1567 uint32_t P4:1; /**< bit: 4 Clear Output Data */ 1568 uint32_t P5:1; /**< bit: 5 Clear Output Data */ 1569 uint32_t P6:1; /**< bit: 6 Clear Output Data */ 1570 uint32_t P7:1; /**< bit: 7 Clear Output Data */ 1571 uint32_t P8:1; /**< bit: 8 Clear Output Data */ 1572 uint32_t P9:1; /**< bit: 9 Clear Output Data */ 1573 uint32_t P10:1; /**< bit: 10 Clear Output Data */ 1574 uint32_t P11:1; /**< bit: 11 Clear Output Data */ 1575 uint32_t P12:1; /**< bit: 12 Clear Output Data */ 1576 uint32_t P13:1; /**< bit: 13 Clear Output Data */ 1577 uint32_t P14:1; /**< bit: 14 Clear Output Data */ 1578 uint32_t P15:1; /**< bit: 15 Clear Output Data */ 1579 uint32_t P16:1; /**< bit: 16 Clear Output Data */ 1580 uint32_t P17:1; /**< bit: 17 Clear Output Data */ 1581 uint32_t P18:1; /**< bit: 18 Clear Output Data */ 1582 uint32_t P19:1; /**< bit: 19 Clear Output Data */ 1583 uint32_t P20:1; /**< bit: 20 Clear Output Data */ 1584 uint32_t P21:1; /**< bit: 21 Clear Output Data */ 1585 uint32_t P22:1; /**< bit: 22 Clear Output Data */ 1586 uint32_t P23:1; /**< bit: 23 Clear Output Data */ 1587 uint32_t P24:1; /**< bit: 24 Clear Output Data */ 1588 uint32_t P25:1; /**< bit: 25 Clear Output Data */ 1589 uint32_t P26:1; /**< bit: 26 Clear Output Data */ 1590 uint32_t P27:1; /**< bit: 27 Clear Output Data */ 1591 uint32_t P28:1; /**< bit: 28 Clear Output Data */ 1592 uint32_t P29:1; /**< bit: 29 Clear Output Data */ 1593 uint32_t P30:1; /**< bit: 30 Clear Output Data */ 1594 uint32_t P31:1; /**< bit: 31 Clear Output Data */ 1595 } bit; /**< Structure used for bit access */ 1596 struct { 1597 uint32_t P:32; /**< bit: 0..31 Clear Output Data */ 1598 } vec; /**< Structure used for vec access */ 1599 uint32_t reg; /**< Type used for register access */ 1600 } PIO_CODR_Type; 1601 #endif 1602 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1603 1604 #define PIO_CODR_OFFSET (0x34) /**< (PIO_CODR) Clear Output Data Register Offset */ 1605 1606 #define PIO_CODR_P0_Pos 0 /**< (PIO_CODR) Clear Output Data Position */ 1607 #define PIO_CODR_P0_Msk (_U_(0x1) << PIO_CODR_P0_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1608 #define PIO_CODR_P0 PIO_CODR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P0_Msk instead */ 1609 #define PIO_CODR_P1_Pos 1 /**< (PIO_CODR) Clear Output Data Position */ 1610 #define PIO_CODR_P1_Msk (_U_(0x1) << PIO_CODR_P1_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1611 #define PIO_CODR_P1 PIO_CODR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P1_Msk instead */ 1612 #define PIO_CODR_P2_Pos 2 /**< (PIO_CODR) Clear Output Data Position */ 1613 #define PIO_CODR_P2_Msk (_U_(0x1) << PIO_CODR_P2_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1614 #define PIO_CODR_P2 PIO_CODR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P2_Msk instead */ 1615 #define PIO_CODR_P3_Pos 3 /**< (PIO_CODR) Clear Output Data Position */ 1616 #define PIO_CODR_P3_Msk (_U_(0x1) << PIO_CODR_P3_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1617 #define PIO_CODR_P3 PIO_CODR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P3_Msk instead */ 1618 #define PIO_CODR_P4_Pos 4 /**< (PIO_CODR) Clear Output Data Position */ 1619 #define PIO_CODR_P4_Msk (_U_(0x1) << PIO_CODR_P4_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1620 #define PIO_CODR_P4 PIO_CODR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P4_Msk instead */ 1621 #define PIO_CODR_P5_Pos 5 /**< (PIO_CODR) Clear Output Data Position */ 1622 #define PIO_CODR_P5_Msk (_U_(0x1) << PIO_CODR_P5_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1623 #define PIO_CODR_P5 PIO_CODR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P5_Msk instead */ 1624 #define PIO_CODR_P6_Pos 6 /**< (PIO_CODR) Clear Output Data Position */ 1625 #define PIO_CODR_P6_Msk (_U_(0x1) << PIO_CODR_P6_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1626 #define PIO_CODR_P6 PIO_CODR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P6_Msk instead */ 1627 #define PIO_CODR_P7_Pos 7 /**< (PIO_CODR) Clear Output Data Position */ 1628 #define PIO_CODR_P7_Msk (_U_(0x1) << PIO_CODR_P7_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1629 #define PIO_CODR_P7 PIO_CODR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P7_Msk instead */ 1630 #define PIO_CODR_P8_Pos 8 /**< (PIO_CODR) Clear Output Data Position */ 1631 #define PIO_CODR_P8_Msk (_U_(0x1) << PIO_CODR_P8_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1632 #define PIO_CODR_P8 PIO_CODR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P8_Msk instead */ 1633 #define PIO_CODR_P9_Pos 9 /**< (PIO_CODR) Clear Output Data Position */ 1634 #define PIO_CODR_P9_Msk (_U_(0x1) << PIO_CODR_P9_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1635 #define PIO_CODR_P9 PIO_CODR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P9_Msk instead */ 1636 #define PIO_CODR_P10_Pos 10 /**< (PIO_CODR) Clear Output Data Position */ 1637 #define PIO_CODR_P10_Msk (_U_(0x1) << PIO_CODR_P10_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1638 #define PIO_CODR_P10 PIO_CODR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P10_Msk instead */ 1639 #define PIO_CODR_P11_Pos 11 /**< (PIO_CODR) Clear Output Data Position */ 1640 #define PIO_CODR_P11_Msk (_U_(0x1) << PIO_CODR_P11_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1641 #define PIO_CODR_P11 PIO_CODR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P11_Msk instead */ 1642 #define PIO_CODR_P12_Pos 12 /**< (PIO_CODR) Clear Output Data Position */ 1643 #define PIO_CODR_P12_Msk (_U_(0x1) << PIO_CODR_P12_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1644 #define PIO_CODR_P12 PIO_CODR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P12_Msk instead */ 1645 #define PIO_CODR_P13_Pos 13 /**< (PIO_CODR) Clear Output Data Position */ 1646 #define PIO_CODR_P13_Msk (_U_(0x1) << PIO_CODR_P13_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1647 #define PIO_CODR_P13 PIO_CODR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P13_Msk instead */ 1648 #define PIO_CODR_P14_Pos 14 /**< (PIO_CODR) Clear Output Data Position */ 1649 #define PIO_CODR_P14_Msk (_U_(0x1) << PIO_CODR_P14_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1650 #define PIO_CODR_P14 PIO_CODR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P14_Msk instead */ 1651 #define PIO_CODR_P15_Pos 15 /**< (PIO_CODR) Clear Output Data Position */ 1652 #define PIO_CODR_P15_Msk (_U_(0x1) << PIO_CODR_P15_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1653 #define PIO_CODR_P15 PIO_CODR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P15_Msk instead */ 1654 #define PIO_CODR_P16_Pos 16 /**< (PIO_CODR) Clear Output Data Position */ 1655 #define PIO_CODR_P16_Msk (_U_(0x1) << PIO_CODR_P16_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1656 #define PIO_CODR_P16 PIO_CODR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P16_Msk instead */ 1657 #define PIO_CODR_P17_Pos 17 /**< (PIO_CODR) Clear Output Data Position */ 1658 #define PIO_CODR_P17_Msk (_U_(0x1) << PIO_CODR_P17_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1659 #define PIO_CODR_P17 PIO_CODR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P17_Msk instead */ 1660 #define PIO_CODR_P18_Pos 18 /**< (PIO_CODR) Clear Output Data Position */ 1661 #define PIO_CODR_P18_Msk (_U_(0x1) << PIO_CODR_P18_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1662 #define PIO_CODR_P18 PIO_CODR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P18_Msk instead */ 1663 #define PIO_CODR_P19_Pos 19 /**< (PIO_CODR) Clear Output Data Position */ 1664 #define PIO_CODR_P19_Msk (_U_(0x1) << PIO_CODR_P19_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1665 #define PIO_CODR_P19 PIO_CODR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P19_Msk instead */ 1666 #define PIO_CODR_P20_Pos 20 /**< (PIO_CODR) Clear Output Data Position */ 1667 #define PIO_CODR_P20_Msk (_U_(0x1) << PIO_CODR_P20_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1668 #define PIO_CODR_P20 PIO_CODR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P20_Msk instead */ 1669 #define PIO_CODR_P21_Pos 21 /**< (PIO_CODR) Clear Output Data Position */ 1670 #define PIO_CODR_P21_Msk (_U_(0x1) << PIO_CODR_P21_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1671 #define PIO_CODR_P21 PIO_CODR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P21_Msk instead */ 1672 #define PIO_CODR_P22_Pos 22 /**< (PIO_CODR) Clear Output Data Position */ 1673 #define PIO_CODR_P22_Msk (_U_(0x1) << PIO_CODR_P22_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1674 #define PIO_CODR_P22 PIO_CODR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P22_Msk instead */ 1675 #define PIO_CODR_P23_Pos 23 /**< (PIO_CODR) Clear Output Data Position */ 1676 #define PIO_CODR_P23_Msk (_U_(0x1) << PIO_CODR_P23_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1677 #define PIO_CODR_P23 PIO_CODR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P23_Msk instead */ 1678 #define PIO_CODR_P24_Pos 24 /**< (PIO_CODR) Clear Output Data Position */ 1679 #define PIO_CODR_P24_Msk (_U_(0x1) << PIO_CODR_P24_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1680 #define PIO_CODR_P24 PIO_CODR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P24_Msk instead */ 1681 #define PIO_CODR_P25_Pos 25 /**< (PIO_CODR) Clear Output Data Position */ 1682 #define PIO_CODR_P25_Msk (_U_(0x1) << PIO_CODR_P25_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1683 #define PIO_CODR_P25 PIO_CODR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P25_Msk instead */ 1684 #define PIO_CODR_P26_Pos 26 /**< (PIO_CODR) Clear Output Data Position */ 1685 #define PIO_CODR_P26_Msk (_U_(0x1) << PIO_CODR_P26_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1686 #define PIO_CODR_P26 PIO_CODR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P26_Msk instead */ 1687 #define PIO_CODR_P27_Pos 27 /**< (PIO_CODR) Clear Output Data Position */ 1688 #define PIO_CODR_P27_Msk (_U_(0x1) << PIO_CODR_P27_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1689 #define PIO_CODR_P27 PIO_CODR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P27_Msk instead */ 1690 #define PIO_CODR_P28_Pos 28 /**< (PIO_CODR) Clear Output Data Position */ 1691 #define PIO_CODR_P28_Msk (_U_(0x1) << PIO_CODR_P28_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1692 #define PIO_CODR_P28 PIO_CODR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P28_Msk instead */ 1693 #define PIO_CODR_P29_Pos 29 /**< (PIO_CODR) Clear Output Data Position */ 1694 #define PIO_CODR_P29_Msk (_U_(0x1) << PIO_CODR_P29_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1695 #define PIO_CODR_P29 PIO_CODR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P29_Msk instead */ 1696 #define PIO_CODR_P30_Pos 30 /**< (PIO_CODR) Clear Output Data Position */ 1697 #define PIO_CODR_P30_Msk (_U_(0x1) << PIO_CODR_P30_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1698 #define PIO_CODR_P30 PIO_CODR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P30_Msk instead */ 1699 #define PIO_CODR_P31_Pos 31 /**< (PIO_CODR) Clear Output Data Position */ 1700 #define PIO_CODR_P31_Msk (_U_(0x1) << PIO_CODR_P31_Pos) /**< (PIO_CODR) Clear Output Data Mask */ 1701 #define PIO_CODR_P31 PIO_CODR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P31_Msk instead */ 1702 #define PIO_CODR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_CODR) Register MASK (Use PIO_CODR_Msk instead) */ 1703 #define PIO_CODR_Msk _U_(0xFFFFFFFF) /**< (PIO_CODR) Register Mask */ 1704 1705 #define PIO_CODR_P_Pos 0 /**< (PIO_CODR Position) Clear Output Data */ 1706 #define PIO_CODR_P_Msk (_U_(0xFFFFFFFF) << PIO_CODR_P_Pos) /**< (PIO_CODR Mask) P */ 1707 #define PIO_CODR_P(value) (PIO_CODR_P_Msk & ((value) << PIO_CODR_P_Pos)) 1708 1709 /* -------- PIO_ODSR : (PIO Offset: 0x38) (R/W 32) Output Data Status Register -------- */ 1710 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1711 #if COMPONENT_TYPEDEF_STYLE == 'N' 1712 typedef union { 1713 struct { 1714 uint32_t P0:1; /**< bit: 0 Output Data Status */ 1715 uint32_t P1:1; /**< bit: 1 Output Data Status */ 1716 uint32_t P2:1; /**< bit: 2 Output Data Status */ 1717 uint32_t P3:1; /**< bit: 3 Output Data Status */ 1718 uint32_t P4:1; /**< bit: 4 Output Data Status */ 1719 uint32_t P5:1; /**< bit: 5 Output Data Status */ 1720 uint32_t P6:1; /**< bit: 6 Output Data Status */ 1721 uint32_t P7:1; /**< bit: 7 Output Data Status */ 1722 uint32_t P8:1; /**< bit: 8 Output Data Status */ 1723 uint32_t P9:1; /**< bit: 9 Output Data Status */ 1724 uint32_t P10:1; /**< bit: 10 Output Data Status */ 1725 uint32_t P11:1; /**< bit: 11 Output Data Status */ 1726 uint32_t P12:1; /**< bit: 12 Output Data Status */ 1727 uint32_t P13:1; /**< bit: 13 Output Data Status */ 1728 uint32_t P14:1; /**< bit: 14 Output Data Status */ 1729 uint32_t P15:1; /**< bit: 15 Output Data Status */ 1730 uint32_t P16:1; /**< bit: 16 Output Data Status */ 1731 uint32_t P17:1; /**< bit: 17 Output Data Status */ 1732 uint32_t P18:1; /**< bit: 18 Output Data Status */ 1733 uint32_t P19:1; /**< bit: 19 Output Data Status */ 1734 uint32_t P20:1; /**< bit: 20 Output Data Status */ 1735 uint32_t P21:1; /**< bit: 21 Output Data Status */ 1736 uint32_t P22:1; /**< bit: 22 Output Data Status */ 1737 uint32_t P23:1; /**< bit: 23 Output Data Status */ 1738 uint32_t P24:1; /**< bit: 24 Output Data Status */ 1739 uint32_t P25:1; /**< bit: 25 Output Data Status */ 1740 uint32_t P26:1; /**< bit: 26 Output Data Status */ 1741 uint32_t P27:1; /**< bit: 27 Output Data Status */ 1742 uint32_t P28:1; /**< bit: 28 Output Data Status */ 1743 uint32_t P29:1; /**< bit: 29 Output Data Status */ 1744 uint32_t P30:1; /**< bit: 30 Output Data Status */ 1745 uint32_t P31:1; /**< bit: 31 Output Data Status */ 1746 } bit; /**< Structure used for bit access */ 1747 struct { 1748 uint32_t P:32; /**< bit: 0..31 Output Data Status */ 1749 } vec; /**< Structure used for vec access */ 1750 uint32_t reg; /**< Type used for register access */ 1751 } PIO_ODSR_Type; 1752 #endif 1753 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1754 1755 #define PIO_ODSR_OFFSET (0x38) /**< (PIO_ODSR) Output Data Status Register Offset */ 1756 1757 #define PIO_ODSR_P0_Pos 0 /**< (PIO_ODSR) Output Data Status Position */ 1758 #define PIO_ODSR_P0_Msk (_U_(0x1) << PIO_ODSR_P0_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1759 #define PIO_ODSR_P0 PIO_ODSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P0_Msk instead */ 1760 #define PIO_ODSR_P1_Pos 1 /**< (PIO_ODSR) Output Data Status Position */ 1761 #define PIO_ODSR_P1_Msk (_U_(0x1) << PIO_ODSR_P1_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1762 #define PIO_ODSR_P1 PIO_ODSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P1_Msk instead */ 1763 #define PIO_ODSR_P2_Pos 2 /**< (PIO_ODSR) Output Data Status Position */ 1764 #define PIO_ODSR_P2_Msk (_U_(0x1) << PIO_ODSR_P2_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1765 #define PIO_ODSR_P2 PIO_ODSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P2_Msk instead */ 1766 #define PIO_ODSR_P3_Pos 3 /**< (PIO_ODSR) Output Data Status Position */ 1767 #define PIO_ODSR_P3_Msk (_U_(0x1) << PIO_ODSR_P3_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1768 #define PIO_ODSR_P3 PIO_ODSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P3_Msk instead */ 1769 #define PIO_ODSR_P4_Pos 4 /**< (PIO_ODSR) Output Data Status Position */ 1770 #define PIO_ODSR_P4_Msk (_U_(0x1) << PIO_ODSR_P4_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1771 #define PIO_ODSR_P4 PIO_ODSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P4_Msk instead */ 1772 #define PIO_ODSR_P5_Pos 5 /**< (PIO_ODSR) Output Data Status Position */ 1773 #define PIO_ODSR_P5_Msk (_U_(0x1) << PIO_ODSR_P5_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1774 #define PIO_ODSR_P5 PIO_ODSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P5_Msk instead */ 1775 #define PIO_ODSR_P6_Pos 6 /**< (PIO_ODSR) Output Data Status Position */ 1776 #define PIO_ODSR_P6_Msk (_U_(0x1) << PIO_ODSR_P6_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1777 #define PIO_ODSR_P6 PIO_ODSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P6_Msk instead */ 1778 #define PIO_ODSR_P7_Pos 7 /**< (PIO_ODSR) Output Data Status Position */ 1779 #define PIO_ODSR_P7_Msk (_U_(0x1) << PIO_ODSR_P7_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1780 #define PIO_ODSR_P7 PIO_ODSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P7_Msk instead */ 1781 #define PIO_ODSR_P8_Pos 8 /**< (PIO_ODSR) Output Data Status Position */ 1782 #define PIO_ODSR_P8_Msk (_U_(0x1) << PIO_ODSR_P8_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1783 #define PIO_ODSR_P8 PIO_ODSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P8_Msk instead */ 1784 #define PIO_ODSR_P9_Pos 9 /**< (PIO_ODSR) Output Data Status Position */ 1785 #define PIO_ODSR_P9_Msk (_U_(0x1) << PIO_ODSR_P9_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1786 #define PIO_ODSR_P9 PIO_ODSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P9_Msk instead */ 1787 #define PIO_ODSR_P10_Pos 10 /**< (PIO_ODSR) Output Data Status Position */ 1788 #define PIO_ODSR_P10_Msk (_U_(0x1) << PIO_ODSR_P10_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1789 #define PIO_ODSR_P10 PIO_ODSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P10_Msk instead */ 1790 #define PIO_ODSR_P11_Pos 11 /**< (PIO_ODSR) Output Data Status Position */ 1791 #define PIO_ODSR_P11_Msk (_U_(0x1) << PIO_ODSR_P11_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1792 #define PIO_ODSR_P11 PIO_ODSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P11_Msk instead */ 1793 #define PIO_ODSR_P12_Pos 12 /**< (PIO_ODSR) Output Data Status Position */ 1794 #define PIO_ODSR_P12_Msk (_U_(0x1) << PIO_ODSR_P12_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1795 #define PIO_ODSR_P12 PIO_ODSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P12_Msk instead */ 1796 #define PIO_ODSR_P13_Pos 13 /**< (PIO_ODSR) Output Data Status Position */ 1797 #define PIO_ODSR_P13_Msk (_U_(0x1) << PIO_ODSR_P13_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1798 #define PIO_ODSR_P13 PIO_ODSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P13_Msk instead */ 1799 #define PIO_ODSR_P14_Pos 14 /**< (PIO_ODSR) Output Data Status Position */ 1800 #define PIO_ODSR_P14_Msk (_U_(0x1) << PIO_ODSR_P14_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1801 #define PIO_ODSR_P14 PIO_ODSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P14_Msk instead */ 1802 #define PIO_ODSR_P15_Pos 15 /**< (PIO_ODSR) Output Data Status Position */ 1803 #define PIO_ODSR_P15_Msk (_U_(0x1) << PIO_ODSR_P15_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1804 #define PIO_ODSR_P15 PIO_ODSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P15_Msk instead */ 1805 #define PIO_ODSR_P16_Pos 16 /**< (PIO_ODSR) Output Data Status Position */ 1806 #define PIO_ODSR_P16_Msk (_U_(0x1) << PIO_ODSR_P16_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1807 #define PIO_ODSR_P16 PIO_ODSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P16_Msk instead */ 1808 #define PIO_ODSR_P17_Pos 17 /**< (PIO_ODSR) Output Data Status Position */ 1809 #define PIO_ODSR_P17_Msk (_U_(0x1) << PIO_ODSR_P17_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1810 #define PIO_ODSR_P17 PIO_ODSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P17_Msk instead */ 1811 #define PIO_ODSR_P18_Pos 18 /**< (PIO_ODSR) Output Data Status Position */ 1812 #define PIO_ODSR_P18_Msk (_U_(0x1) << PIO_ODSR_P18_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1813 #define PIO_ODSR_P18 PIO_ODSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P18_Msk instead */ 1814 #define PIO_ODSR_P19_Pos 19 /**< (PIO_ODSR) Output Data Status Position */ 1815 #define PIO_ODSR_P19_Msk (_U_(0x1) << PIO_ODSR_P19_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1816 #define PIO_ODSR_P19 PIO_ODSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P19_Msk instead */ 1817 #define PIO_ODSR_P20_Pos 20 /**< (PIO_ODSR) Output Data Status Position */ 1818 #define PIO_ODSR_P20_Msk (_U_(0x1) << PIO_ODSR_P20_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1819 #define PIO_ODSR_P20 PIO_ODSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P20_Msk instead */ 1820 #define PIO_ODSR_P21_Pos 21 /**< (PIO_ODSR) Output Data Status Position */ 1821 #define PIO_ODSR_P21_Msk (_U_(0x1) << PIO_ODSR_P21_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1822 #define PIO_ODSR_P21 PIO_ODSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P21_Msk instead */ 1823 #define PIO_ODSR_P22_Pos 22 /**< (PIO_ODSR) Output Data Status Position */ 1824 #define PIO_ODSR_P22_Msk (_U_(0x1) << PIO_ODSR_P22_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1825 #define PIO_ODSR_P22 PIO_ODSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P22_Msk instead */ 1826 #define PIO_ODSR_P23_Pos 23 /**< (PIO_ODSR) Output Data Status Position */ 1827 #define PIO_ODSR_P23_Msk (_U_(0x1) << PIO_ODSR_P23_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1828 #define PIO_ODSR_P23 PIO_ODSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P23_Msk instead */ 1829 #define PIO_ODSR_P24_Pos 24 /**< (PIO_ODSR) Output Data Status Position */ 1830 #define PIO_ODSR_P24_Msk (_U_(0x1) << PIO_ODSR_P24_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1831 #define PIO_ODSR_P24 PIO_ODSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P24_Msk instead */ 1832 #define PIO_ODSR_P25_Pos 25 /**< (PIO_ODSR) Output Data Status Position */ 1833 #define PIO_ODSR_P25_Msk (_U_(0x1) << PIO_ODSR_P25_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1834 #define PIO_ODSR_P25 PIO_ODSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P25_Msk instead */ 1835 #define PIO_ODSR_P26_Pos 26 /**< (PIO_ODSR) Output Data Status Position */ 1836 #define PIO_ODSR_P26_Msk (_U_(0x1) << PIO_ODSR_P26_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1837 #define PIO_ODSR_P26 PIO_ODSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P26_Msk instead */ 1838 #define PIO_ODSR_P27_Pos 27 /**< (PIO_ODSR) Output Data Status Position */ 1839 #define PIO_ODSR_P27_Msk (_U_(0x1) << PIO_ODSR_P27_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1840 #define PIO_ODSR_P27 PIO_ODSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P27_Msk instead */ 1841 #define PIO_ODSR_P28_Pos 28 /**< (PIO_ODSR) Output Data Status Position */ 1842 #define PIO_ODSR_P28_Msk (_U_(0x1) << PIO_ODSR_P28_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1843 #define PIO_ODSR_P28 PIO_ODSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P28_Msk instead */ 1844 #define PIO_ODSR_P29_Pos 29 /**< (PIO_ODSR) Output Data Status Position */ 1845 #define PIO_ODSR_P29_Msk (_U_(0x1) << PIO_ODSR_P29_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1846 #define PIO_ODSR_P29 PIO_ODSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P29_Msk instead */ 1847 #define PIO_ODSR_P30_Pos 30 /**< (PIO_ODSR) Output Data Status Position */ 1848 #define PIO_ODSR_P30_Msk (_U_(0x1) << PIO_ODSR_P30_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1849 #define PIO_ODSR_P30 PIO_ODSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P30_Msk instead */ 1850 #define PIO_ODSR_P31_Pos 31 /**< (PIO_ODSR) Output Data Status Position */ 1851 #define PIO_ODSR_P31_Msk (_U_(0x1) << PIO_ODSR_P31_Pos) /**< (PIO_ODSR) Output Data Status Mask */ 1852 #define PIO_ODSR_P31 PIO_ODSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P31_Msk instead */ 1853 #define PIO_ODSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_ODSR) Register MASK (Use PIO_ODSR_Msk instead) */ 1854 #define PIO_ODSR_Msk _U_(0xFFFFFFFF) /**< (PIO_ODSR) Register Mask */ 1855 1856 #define PIO_ODSR_P_Pos 0 /**< (PIO_ODSR Position) Output Data Status */ 1857 #define PIO_ODSR_P_Msk (_U_(0xFFFFFFFF) << PIO_ODSR_P_Pos) /**< (PIO_ODSR Mask) P */ 1858 #define PIO_ODSR_P(value) (PIO_ODSR_P_Msk & ((value) << PIO_ODSR_P_Pos)) 1859 1860 /* -------- PIO_PDSR : (PIO Offset: 0x3c) (R/ 32) Pin Data Status Register -------- */ 1861 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1862 #if COMPONENT_TYPEDEF_STYLE == 'N' 1863 typedef union { 1864 struct { 1865 uint32_t P0:1; /**< bit: 0 Output Data Status */ 1866 uint32_t P1:1; /**< bit: 1 Output Data Status */ 1867 uint32_t P2:1; /**< bit: 2 Output Data Status */ 1868 uint32_t P3:1; /**< bit: 3 Output Data Status */ 1869 uint32_t P4:1; /**< bit: 4 Output Data Status */ 1870 uint32_t P5:1; /**< bit: 5 Output Data Status */ 1871 uint32_t P6:1; /**< bit: 6 Output Data Status */ 1872 uint32_t P7:1; /**< bit: 7 Output Data Status */ 1873 uint32_t P8:1; /**< bit: 8 Output Data Status */ 1874 uint32_t P9:1; /**< bit: 9 Output Data Status */ 1875 uint32_t P10:1; /**< bit: 10 Output Data Status */ 1876 uint32_t P11:1; /**< bit: 11 Output Data Status */ 1877 uint32_t P12:1; /**< bit: 12 Output Data Status */ 1878 uint32_t P13:1; /**< bit: 13 Output Data Status */ 1879 uint32_t P14:1; /**< bit: 14 Output Data Status */ 1880 uint32_t P15:1; /**< bit: 15 Output Data Status */ 1881 uint32_t P16:1; /**< bit: 16 Output Data Status */ 1882 uint32_t P17:1; /**< bit: 17 Output Data Status */ 1883 uint32_t P18:1; /**< bit: 18 Output Data Status */ 1884 uint32_t P19:1; /**< bit: 19 Output Data Status */ 1885 uint32_t P20:1; /**< bit: 20 Output Data Status */ 1886 uint32_t P21:1; /**< bit: 21 Output Data Status */ 1887 uint32_t P22:1; /**< bit: 22 Output Data Status */ 1888 uint32_t P23:1; /**< bit: 23 Output Data Status */ 1889 uint32_t P24:1; /**< bit: 24 Output Data Status */ 1890 uint32_t P25:1; /**< bit: 25 Output Data Status */ 1891 uint32_t P26:1; /**< bit: 26 Output Data Status */ 1892 uint32_t P27:1; /**< bit: 27 Output Data Status */ 1893 uint32_t P28:1; /**< bit: 28 Output Data Status */ 1894 uint32_t P29:1; /**< bit: 29 Output Data Status */ 1895 uint32_t P30:1; /**< bit: 30 Output Data Status */ 1896 uint32_t P31:1; /**< bit: 31 Output Data Status */ 1897 } bit; /**< Structure used for bit access */ 1898 struct { 1899 uint32_t P:32; /**< bit: 0..31 Output Data Status */ 1900 } vec; /**< Structure used for vec access */ 1901 uint32_t reg; /**< Type used for register access */ 1902 } PIO_PDSR_Type; 1903 #endif 1904 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1905 1906 #define PIO_PDSR_OFFSET (0x3C) /**< (PIO_PDSR) Pin Data Status Register Offset */ 1907 1908 #define PIO_PDSR_P0_Pos 0 /**< (PIO_PDSR) Output Data Status Position */ 1909 #define PIO_PDSR_P0_Msk (_U_(0x1) << PIO_PDSR_P0_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1910 #define PIO_PDSR_P0 PIO_PDSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P0_Msk instead */ 1911 #define PIO_PDSR_P1_Pos 1 /**< (PIO_PDSR) Output Data Status Position */ 1912 #define PIO_PDSR_P1_Msk (_U_(0x1) << PIO_PDSR_P1_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1913 #define PIO_PDSR_P1 PIO_PDSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P1_Msk instead */ 1914 #define PIO_PDSR_P2_Pos 2 /**< (PIO_PDSR) Output Data Status Position */ 1915 #define PIO_PDSR_P2_Msk (_U_(0x1) << PIO_PDSR_P2_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1916 #define PIO_PDSR_P2 PIO_PDSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P2_Msk instead */ 1917 #define PIO_PDSR_P3_Pos 3 /**< (PIO_PDSR) Output Data Status Position */ 1918 #define PIO_PDSR_P3_Msk (_U_(0x1) << PIO_PDSR_P3_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1919 #define PIO_PDSR_P3 PIO_PDSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P3_Msk instead */ 1920 #define PIO_PDSR_P4_Pos 4 /**< (PIO_PDSR) Output Data Status Position */ 1921 #define PIO_PDSR_P4_Msk (_U_(0x1) << PIO_PDSR_P4_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1922 #define PIO_PDSR_P4 PIO_PDSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P4_Msk instead */ 1923 #define PIO_PDSR_P5_Pos 5 /**< (PIO_PDSR) Output Data Status Position */ 1924 #define PIO_PDSR_P5_Msk (_U_(0x1) << PIO_PDSR_P5_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1925 #define PIO_PDSR_P5 PIO_PDSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P5_Msk instead */ 1926 #define PIO_PDSR_P6_Pos 6 /**< (PIO_PDSR) Output Data Status Position */ 1927 #define PIO_PDSR_P6_Msk (_U_(0x1) << PIO_PDSR_P6_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1928 #define PIO_PDSR_P6 PIO_PDSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P6_Msk instead */ 1929 #define PIO_PDSR_P7_Pos 7 /**< (PIO_PDSR) Output Data Status Position */ 1930 #define PIO_PDSR_P7_Msk (_U_(0x1) << PIO_PDSR_P7_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1931 #define PIO_PDSR_P7 PIO_PDSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P7_Msk instead */ 1932 #define PIO_PDSR_P8_Pos 8 /**< (PIO_PDSR) Output Data Status Position */ 1933 #define PIO_PDSR_P8_Msk (_U_(0x1) << PIO_PDSR_P8_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1934 #define PIO_PDSR_P8 PIO_PDSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P8_Msk instead */ 1935 #define PIO_PDSR_P9_Pos 9 /**< (PIO_PDSR) Output Data Status Position */ 1936 #define PIO_PDSR_P9_Msk (_U_(0x1) << PIO_PDSR_P9_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1937 #define PIO_PDSR_P9 PIO_PDSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P9_Msk instead */ 1938 #define PIO_PDSR_P10_Pos 10 /**< (PIO_PDSR) Output Data Status Position */ 1939 #define PIO_PDSR_P10_Msk (_U_(0x1) << PIO_PDSR_P10_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1940 #define PIO_PDSR_P10 PIO_PDSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P10_Msk instead */ 1941 #define PIO_PDSR_P11_Pos 11 /**< (PIO_PDSR) Output Data Status Position */ 1942 #define PIO_PDSR_P11_Msk (_U_(0x1) << PIO_PDSR_P11_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1943 #define PIO_PDSR_P11 PIO_PDSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P11_Msk instead */ 1944 #define PIO_PDSR_P12_Pos 12 /**< (PIO_PDSR) Output Data Status Position */ 1945 #define PIO_PDSR_P12_Msk (_U_(0x1) << PIO_PDSR_P12_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1946 #define PIO_PDSR_P12 PIO_PDSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P12_Msk instead */ 1947 #define PIO_PDSR_P13_Pos 13 /**< (PIO_PDSR) Output Data Status Position */ 1948 #define PIO_PDSR_P13_Msk (_U_(0x1) << PIO_PDSR_P13_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1949 #define PIO_PDSR_P13 PIO_PDSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P13_Msk instead */ 1950 #define PIO_PDSR_P14_Pos 14 /**< (PIO_PDSR) Output Data Status Position */ 1951 #define PIO_PDSR_P14_Msk (_U_(0x1) << PIO_PDSR_P14_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1952 #define PIO_PDSR_P14 PIO_PDSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P14_Msk instead */ 1953 #define PIO_PDSR_P15_Pos 15 /**< (PIO_PDSR) Output Data Status Position */ 1954 #define PIO_PDSR_P15_Msk (_U_(0x1) << PIO_PDSR_P15_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1955 #define PIO_PDSR_P15 PIO_PDSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P15_Msk instead */ 1956 #define PIO_PDSR_P16_Pos 16 /**< (PIO_PDSR) Output Data Status Position */ 1957 #define PIO_PDSR_P16_Msk (_U_(0x1) << PIO_PDSR_P16_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1958 #define PIO_PDSR_P16 PIO_PDSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P16_Msk instead */ 1959 #define PIO_PDSR_P17_Pos 17 /**< (PIO_PDSR) Output Data Status Position */ 1960 #define PIO_PDSR_P17_Msk (_U_(0x1) << PIO_PDSR_P17_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1961 #define PIO_PDSR_P17 PIO_PDSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P17_Msk instead */ 1962 #define PIO_PDSR_P18_Pos 18 /**< (PIO_PDSR) Output Data Status Position */ 1963 #define PIO_PDSR_P18_Msk (_U_(0x1) << PIO_PDSR_P18_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1964 #define PIO_PDSR_P18 PIO_PDSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P18_Msk instead */ 1965 #define PIO_PDSR_P19_Pos 19 /**< (PIO_PDSR) Output Data Status Position */ 1966 #define PIO_PDSR_P19_Msk (_U_(0x1) << PIO_PDSR_P19_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1967 #define PIO_PDSR_P19 PIO_PDSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P19_Msk instead */ 1968 #define PIO_PDSR_P20_Pos 20 /**< (PIO_PDSR) Output Data Status Position */ 1969 #define PIO_PDSR_P20_Msk (_U_(0x1) << PIO_PDSR_P20_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1970 #define PIO_PDSR_P20 PIO_PDSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P20_Msk instead */ 1971 #define PIO_PDSR_P21_Pos 21 /**< (PIO_PDSR) Output Data Status Position */ 1972 #define PIO_PDSR_P21_Msk (_U_(0x1) << PIO_PDSR_P21_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1973 #define PIO_PDSR_P21 PIO_PDSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P21_Msk instead */ 1974 #define PIO_PDSR_P22_Pos 22 /**< (PIO_PDSR) Output Data Status Position */ 1975 #define PIO_PDSR_P22_Msk (_U_(0x1) << PIO_PDSR_P22_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1976 #define PIO_PDSR_P22 PIO_PDSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P22_Msk instead */ 1977 #define PIO_PDSR_P23_Pos 23 /**< (PIO_PDSR) Output Data Status Position */ 1978 #define PIO_PDSR_P23_Msk (_U_(0x1) << PIO_PDSR_P23_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1979 #define PIO_PDSR_P23 PIO_PDSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P23_Msk instead */ 1980 #define PIO_PDSR_P24_Pos 24 /**< (PIO_PDSR) Output Data Status Position */ 1981 #define PIO_PDSR_P24_Msk (_U_(0x1) << PIO_PDSR_P24_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1982 #define PIO_PDSR_P24 PIO_PDSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P24_Msk instead */ 1983 #define PIO_PDSR_P25_Pos 25 /**< (PIO_PDSR) Output Data Status Position */ 1984 #define PIO_PDSR_P25_Msk (_U_(0x1) << PIO_PDSR_P25_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1985 #define PIO_PDSR_P25 PIO_PDSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P25_Msk instead */ 1986 #define PIO_PDSR_P26_Pos 26 /**< (PIO_PDSR) Output Data Status Position */ 1987 #define PIO_PDSR_P26_Msk (_U_(0x1) << PIO_PDSR_P26_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1988 #define PIO_PDSR_P26 PIO_PDSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P26_Msk instead */ 1989 #define PIO_PDSR_P27_Pos 27 /**< (PIO_PDSR) Output Data Status Position */ 1990 #define PIO_PDSR_P27_Msk (_U_(0x1) << PIO_PDSR_P27_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1991 #define PIO_PDSR_P27 PIO_PDSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P27_Msk instead */ 1992 #define PIO_PDSR_P28_Pos 28 /**< (PIO_PDSR) Output Data Status Position */ 1993 #define PIO_PDSR_P28_Msk (_U_(0x1) << PIO_PDSR_P28_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1994 #define PIO_PDSR_P28 PIO_PDSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P28_Msk instead */ 1995 #define PIO_PDSR_P29_Pos 29 /**< (PIO_PDSR) Output Data Status Position */ 1996 #define PIO_PDSR_P29_Msk (_U_(0x1) << PIO_PDSR_P29_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 1997 #define PIO_PDSR_P29 PIO_PDSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P29_Msk instead */ 1998 #define PIO_PDSR_P30_Pos 30 /**< (PIO_PDSR) Output Data Status Position */ 1999 #define PIO_PDSR_P30_Msk (_U_(0x1) << PIO_PDSR_P30_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 2000 #define PIO_PDSR_P30 PIO_PDSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P30_Msk instead */ 2001 #define PIO_PDSR_P31_Pos 31 /**< (PIO_PDSR) Output Data Status Position */ 2002 #define PIO_PDSR_P31_Msk (_U_(0x1) << PIO_PDSR_P31_Pos) /**< (PIO_PDSR) Output Data Status Mask */ 2003 #define PIO_PDSR_P31 PIO_PDSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P31_Msk instead */ 2004 #define PIO_PDSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PDSR) Register MASK (Use PIO_PDSR_Msk instead) */ 2005 #define PIO_PDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PDSR) Register Mask */ 2006 2007 #define PIO_PDSR_P_Pos 0 /**< (PIO_PDSR Position) Output Data Status */ 2008 #define PIO_PDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PDSR_P_Pos) /**< (PIO_PDSR Mask) P */ 2009 #define PIO_PDSR_P(value) (PIO_PDSR_P_Msk & ((value) << PIO_PDSR_P_Pos)) 2010 2011 /* -------- PIO_IER : (PIO Offset: 0x40) (/W 32) Interrupt Enable Register -------- */ 2012 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2013 #if COMPONENT_TYPEDEF_STYLE == 'N' 2014 typedef union { 2015 struct { 2016 uint32_t P0:1; /**< bit: 0 Input Change Interrupt Enable */ 2017 uint32_t P1:1; /**< bit: 1 Input Change Interrupt Enable */ 2018 uint32_t P2:1; /**< bit: 2 Input Change Interrupt Enable */ 2019 uint32_t P3:1; /**< bit: 3 Input Change Interrupt Enable */ 2020 uint32_t P4:1; /**< bit: 4 Input Change Interrupt Enable */ 2021 uint32_t P5:1; /**< bit: 5 Input Change Interrupt Enable */ 2022 uint32_t P6:1; /**< bit: 6 Input Change Interrupt Enable */ 2023 uint32_t P7:1; /**< bit: 7 Input Change Interrupt Enable */ 2024 uint32_t P8:1; /**< bit: 8 Input Change Interrupt Enable */ 2025 uint32_t P9:1; /**< bit: 9 Input Change Interrupt Enable */ 2026 uint32_t P10:1; /**< bit: 10 Input Change Interrupt Enable */ 2027 uint32_t P11:1; /**< bit: 11 Input Change Interrupt Enable */ 2028 uint32_t P12:1; /**< bit: 12 Input Change Interrupt Enable */ 2029 uint32_t P13:1; /**< bit: 13 Input Change Interrupt Enable */ 2030 uint32_t P14:1; /**< bit: 14 Input Change Interrupt Enable */ 2031 uint32_t P15:1; /**< bit: 15 Input Change Interrupt Enable */ 2032 uint32_t P16:1; /**< bit: 16 Input Change Interrupt Enable */ 2033 uint32_t P17:1; /**< bit: 17 Input Change Interrupt Enable */ 2034 uint32_t P18:1; /**< bit: 18 Input Change Interrupt Enable */ 2035 uint32_t P19:1; /**< bit: 19 Input Change Interrupt Enable */ 2036 uint32_t P20:1; /**< bit: 20 Input Change Interrupt Enable */ 2037 uint32_t P21:1; /**< bit: 21 Input Change Interrupt Enable */ 2038 uint32_t P22:1; /**< bit: 22 Input Change Interrupt Enable */ 2039 uint32_t P23:1; /**< bit: 23 Input Change Interrupt Enable */ 2040 uint32_t P24:1; /**< bit: 24 Input Change Interrupt Enable */ 2041 uint32_t P25:1; /**< bit: 25 Input Change Interrupt Enable */ 2042 uint32_t P26:1; /**< bit: 26 Input Change Interrupt Enable */ 2043 uint32_t P27:1; /**< bit: 27 Input Change Interrupt Enable */ 2044 uint32_t P28:1; /**< bit: 28 Input Change Interrupt Enable */ 2045 uint32_t P29:1; /**< bit: 29 Input Change Interrupt Enable */ 2046 uint32_t P30:1; /**< bit: 30 Input Change Interrupt Enable */ 2047 uint32_t P31:1; /**< bit: 31 Input Change Interrupt Enable */ 2048 } bit; /**< Structure used for bit access */ 2049 struct { 2050 uint32_t P:32; /**< bit: 0..31 Input Change Interrupt Enable */ 2051 } vec; /**< Structure used for vec access */ 2052 uint32_t reg; /**< Type used for register access */ 2053 } PIO_IER_Type; 2054 #endif 2055 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2056 2057 #define PIO_IER_OFFSET (0x40) /**< (PIO_IER) Interrupt Enable Register Offset */ 2058 2059 #define PIO_IER_P0_Pos 0 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2060 #define PIO_IER_P0_Msk (_U_(0x1) << PIO_IER_P0_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2061 #define PIO_IER_P0 PIO_IER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P0_Msk instead */ 2062 #define PIO_IER_P1_Pos 1 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2063 #define PIO_IER_P1_Msk (_U_(0x1) << PIO_IER_P1_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2064 #define PIO_IER_P1 PIO_IER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P1_Msk instead */ 2065 #define PIO_IER_P2_Pos 2 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2066 #define PIO_IER_P2_Msk (_U_(0x1) << PIO_IER_P2_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2067 #define PIO_IER_P2 PIO_IER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P2_Msk instead */ 2068 #define PIO_IER_P3_Pos 3 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2069 #define PIO_IER_P3_Msk (_U_(0x1) << PIO_IER_P3_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2070 #define PIO_IER_P3 PIO_IER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P3_Msk instead */ 2071 #define PIO_IER_P4_Pos 4 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2072 #define PIO_IER_P4_Msk (_U_(0x1) << PIO_IER_P4_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2073 #define PIO_IER_P4 PIO_IER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P4_Msk instead */ 2074 #define PIO_IER_P5_Pos 5 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2075 #define PIO_IER_P5_Msk (_U_(0x1) << PIO_IER_P5_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2076 #define PIO_IER_P5 PIO_IER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P5_Msk instead */ 2077 #define PIO_IER_P6_Pos 6 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2078 #define PIO_IER_P6_Msk (_U_(0x1) << PIO_IER_P6_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2079 #define PIO_IER_P6 PIO_IER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P6_Msk instead */ 2080 #define PIO_IER_P7_Pos 7 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2081 #define PIO_IER_P7_Msk (_U_(0x1) << PIO_IER_P7_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2082 #define PIO_IER_P7 PIO_IER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P7_Msk instead */ 2083 #define PIO_IER_P8_Pos 8 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2084 #define PIO_IER_P8_Msk (_U_(0x1) << PIO_IER_P8_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2085 #define PIO_IER_P8 PIO_IER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P8_Msk instead */ 2086 #define PIO_IER_P9_Pos 9 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2087 #define PIO_IER_P9_Msk (_U_(0x1) << PIO_IER_P9_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2088 #define PIO_IER_P9 PIO_IER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P9_Msk instead */ 2089 #define PIO_IER_P10_Pos 10 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2090 #define PIO_IER_P10_Msk (_U_(0x1) << PIO_IER_P10_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2091 #define PIO_IER_P10 PIO_IER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P10_Msk instead */ 2092 #define PIO_IER_P11_Pos 11 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2093 #define PIO_IER_P11_Msk (_U_(0x1) << PIO_IER_P11_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2094 #define PIO_IER_P11 PIO_IER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P11_Msk instead */ 2095 #define PIO_IER_P12_Pos 12 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2096 #define PIO_IER_P12_Msk (_U_(0x1) << PIO_IER_P12_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2097 #define PIO_IER_P12 PIO_IER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P12_Msk instead */ 2098 #define PIO_IER_P13_Pos 13 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2099 #define PIO_IER_P13_Msk (_U_(0x1) << PIO_IER_P13_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2100 #define PIO_IER_P13 PIO_IER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P13_Msk instead */ 2101 #define PIO_IER_P14_Pos 14 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2102 #define PIO_IER_P14_Msk (_U_(0x1) << PIO_IER_P14_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2103 #define PIO_IER_P14 PIO_IER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P14_Msk instead */ 2104 #define PIO_IER_P15_Pos 15 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2105 #define PIO_IER_P15_Msk (_U_(0x1) << PIO_IER_P15_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2106 #define PIO_IER_P15 PIO_IER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P15_Msk instead */ 2107 #define PIO_IER_P16_Pos 16 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2108 #define PIO_IER_P16_Msk (_U_(0x1) << PIO_IER_P16_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2109 #define PIO_IER_P16 PIO_IER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P16_Msk instead */ 2110 #define PIO_IER_P17_Pos 17 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2111 #define PIO_IER_P17_Msk (_U_(0x1) << PIO_IER_P17_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2112 #define PIO_IER_P17 PIO_IER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P17_Msk instead */ 2113 #define PIO_IER_P18_Pos 18 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2114 #define PIO_IER_P18_Msk (_U_(0x1) << PIO_IER_P18_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2115 #define PIO_IER_P18 PIO_IER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P18_Msk instead */ 2116 #define PIO_IER_P19_Pos 19 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2117 #define PIO_IER_P19_Msk (_U_(0x1) << PIO_IER_P19_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2118 #define PIO_IER_P19 PIO_IER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P19_Msk instead */ 2119 #define PIO_IER_P20_Pos 20 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2120 #define PIO_IER_P20_Msk (_U_(0x1) << PIO_IER_P20_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2121 #define PIO_IER_P20 PIO_IER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P20_Msk instead */ 2122 #define PIO_IER_P21_Pos 21 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2123 #define PIO_IER_P21_Msk (_U_(0x1) << PIO_IER_P21_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2124 #define PIO_IER_P21 PIO_IER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P21_Msk instead */ 2125 #define PIO_IER_P22_Pos 22 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2126 #define PIO_IER_P22_Msk (_U_(0x1) << PIO_IER_P22_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2127 #define PIO_IER_P22 PIO_IER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P22_Msk instead */ 2128 #define PIO_IER_P23_Pos 23 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2129 #define PIO_IER_P23_Msk (_U_(0x1) << PIO_IER_P23_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2130 #define PIO_IER_P23 PIO_IER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P23_Msk instead */ 2131 #define PIO_IER_P24_Pos 24 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2132 #define PIO_IER_P24_Msk (_U_(0x1) << PIO_IER_P24_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2133 #define PIO_IER_P24 PIO_IER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P24_Msk instead */ 2134 #define PIO_IER_P25_Pos 25 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2135 #define PIO_IER_P25_Msk (_U_(0x1) << PIO_IER_P25_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2136 #define PIO_IER_P25 PIO_IER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P25_Msk instead */ 2137 #define PIO_IER_P26_Pos 26 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2138 #define PIO_IER_P26_Msk (_U_(0x1) << PIO_IER_P26_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2139 #define PIO_IER_P26 PIO_IER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P26_Msk instead */ 2140 #define PIO_IER_P27_Pos 27 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2141 #define PIO_IER_P27_Msk (_U_(0x1) << PIO_IER_P27_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2142 #define PIO_IER_P27 PIO_IER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P27_Msk instead */ 2143 #define PIO_IER_P28_Pos 28 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2144 #define PIO_IER_P28_Msk (_U_(0x1) << PIO_IER_P28_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2145 #define PIO_IER_P28 PIO_IER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P28_Msk instead */ 2146 #define PIO_IER_P29_Pos 29 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2147 #define PIO_IER_P29_Msk (_U_(0x1) << PIO_IER_P29_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2148 #define PIO_IER_P29 PIO_IER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P29_Msk instead */ 2149 #define PIO_IER_P30_Pos 30 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2150 #define PIO_IER_P30_Msk (_U_(0x1) << PIO_IER_P30_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2151 #define PIO_IER_P30 PIO_IER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P30_Msk instead */ 2152 #define PIO_IER_P31_Pos 31 /**< (PIO_IER) Input Change Interrupt Enable Position */ 2153 #define PIO_IER_P31_Msk (_U_(0x1) << PIO_IER_P31_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ 2154 #define PIO_IER_P31 PIO_IER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P31_Msk instead */ 2155 #define PIO_IER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IER) Register MASK (Use PIO_IER_Msk instead) */ 2156 #define PIO_IER_Msk _U_(0xFFFFFFFF) /**< (PIO_IER) Register Mask */ 2157 2158 #define PIO_IER_P_Pos 0 /**< (PIO_IER Position) Input Change Interrupt Enable */ 2159 #define PIO_IER_P_Msk (_U_(0xFFFFFFFF) << PIO_IER_P_Pos) /**< (PIO_IER Mask) P */ 2160 #define PIO_IER_P(value) (PIO_IER_P_Msk & ((value) << PIO_IER_P_Pos)) 2161 2162 /* -------- PIO_IDR : (PIO Offset: 0x44) (/W 32) Interrupt Disable Register -------- */ 2163 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2164 #if COMPONENT_TYPEDEF_STYLE == 'N' 2165 typedef union { 2166 struct { 2167 uint32_t P0:1; /**< bit: 0 Input Change Interrupt Disable */ 2168 uint32_t P1:1; /**< bit: 1 Input Change Interrupt Disable */ 2169 uint32_t P2:1; /**< bit: 2 Input Change Interrupt Disable */ 2170 uint32_t P3:1; /**< bit: 3 Input Change Interrupt Disable */ 2171 uint32_t P4:1; /**< bit: 4 Input Change Interrupt Disable */ 2172 uint32_t P5:1; /**< bit: 5 Input Change Interrupt Disable */ 2173 uint32_t P6:1; /**< bit: 6 Input Change Interrupt Disable */ 2174 uint32_t P7:1; /**< bit: 7 Input Change Interrupt Disable */ 2175 uint32_t P8:1; /**< bit: 8 Input Change Interrupt Disable */ 2176 uint32_t P9:1; /**< bit: 9 Input Change Interrupt Disable */ 2177 uint32_t P10:1; /**< bit: 10 Input Change Interrupt Disable */ 2178 uint32_t P11:1; /**< bit: 11 Input Change Interrupt Disable */ 2179 uint32_t P12:1; /**< bit: 12 Input Change Interrupt Disable */ 2180 uint32_t P13:1; /**< bit: 13 Input Change Interrupt Disable */ 2181 uint32_t P14:1; /**< bit: 14 Input Change Interrupt Disable */ 2182 uint32_t P15:1; /**< bit: 15 Input Change Interrupt Disable */ 2183 uint32_t P16:1; /**< bit: 16 Input Change Interrupt Disable */ 2184 uint32_t P17:1; /**< bit: 17 Input Change Interrupt Disable */ 2185 uint32_t P18:1; /**< bit: 18 Input Change Interrupt Disable */ 2186 uint32_t P19:1; /**< bit: 19 Input Change Interrupt Disable */ 2187 uint32_t P20:1; /**< bit: 20 Input Change Interrupt Disable */ 2188 uint32_t P21:1; /**< bit: 21 Input Change Interrupt Disable */ 2189 uint32_t P22:1; /**< bit: 22 Input Change Interrupt Disable */ 2190 uint32_t P23:1; /**< bit: 23 Input Change Interrupt Disable */ 2191 uint32_t P24:1; /**< bit: 24 Input Change Interrupt Disable */ 2192 uint32_t P25:1; /**< bit: 25 Input Change Interrupt Disable */ 2193 uint32_t P26:1; /**< bit: 26 Input Change Interrupt Disable */ 2194 uint32_t P27:1; /**< bit: 27 Input Change Interrupt Disable */ 2195 uint32_t P28:1; /**< bit: 28 Input Change Interrupt Disable */ 2196 uint32_t P29:1; /**< bit: 29 Input Change Interrupt Disable */ 2197 uint32_t P30:1; /**< bit: 30 Input Change Interrupt Disable */ 2198 uint32_t P31:1; /**< bit: 31 Input Change Interrupt Disable */ 2199 } bit; /**< Structure used for bit access */ 2200 struct { 2201 uint32_t P:32; /**< bit: 0..31 Input Change Interrupt Disable */ 2202 } vec; /**< Structure used for vec access */ 2203 uint32_t reg; /**< Type used for register access */ 2204 } PIO_IDR_Type; 2205 #endif 2206 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2207 2208 #define PIO_IDR_OFFSET (0x44) /**< (PIO_IDR) Interrupt Disable Register Offset */ 2209 2210 #define PIO_IDR_P0_Pos 0 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2211 #define PIO_IDR_P0_Msk (_U_(0x1) << PIO_IDR_P0_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2212 #define PIO_IDR_P0 PIO_IDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P0_Msk instead */ 2213 #define PIO_IDR_P1_Pos 1 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2214 #define PIO_IDR_P1_Msk (_U_(0x1) << PIO_IDR_P1_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2215 #define PIO_IDR_P1 PIO_IDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P1_Msk instead */ 2216 #define PIO_IDR_P2_Pos 2 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2217 #define PIO_IDR_P2_Msk (_U_(0x1) << PIO_IDR_P2_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2218 #define PIO_IDR_P2 PIO_IDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P2_Msk instead */ 2219 #define PIO_IDR_P3_Pos 3 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2220 #define PIO_IDR_P3_Msk (_U_(0x1) << PIO_IDR_P3_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2221 #define PIO_IDR_P3 PIO_IDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P3_Msk instead */ 2222 #define PIO_IDR_P4_Pos 4 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2223 #define PIO_IDR_P4_Msk (_U_(0x1) << PIO_IDR_P4_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2224 #define PIO_IDR_P4 PIO_IDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P4_Msk instead */ 2225 #define PIO_IDR_P5_Pos 5 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2226 #define PIO_IDR_P5_Msk (_U_(0x1) << PIO_IDR_P5_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2227 #define PIO_IDR_P5 PIO_IDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P5_Msk instead */ 2228 #define PIO_IDR_P6_Pos 6 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2229 #define PIO_IDR_P6_Msk (_U_(0x1) << PIO_IDR_P6_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2230 #define PIO_IDR_P6 PIO_IDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P6_Msk instead */ 2231 #define PIO_IDR_P7_Pos 7 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2232 #define PIO_IDR_P7_Msk (_U_(0x1) << PIO_IDR_P7_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2233 #define PIO_IDR_P7 PIO_IDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P7_Msk instead */ 2234 #define PIO_IDR_P8_Pos 8 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2235 #define PIO_IDR_P8_Msk (_U_(0x1) << PIO_IDR_P8_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2236 #define PIO_IDR_P8 PIO_IDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P8_Msk instead */ 2237 #define PIO_IDR_P9_Pos 9 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2238 #define PIO_IDR_P9_Msk (_U_(0x1) << PIO_IDR_P9_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2239 #define PIO_IDR_P9 PIO_IDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P9_Msk instead */ 2240 #define PIO_IDR_P10_Pos 10 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2241 #define PIO_IDR_P10_Msk (_U_(0x1) << PIO_IDR_P10_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2242 #define PIO_IDR_P10 PIO_IDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P10_Msk instead */ 2243 #define PIO_IDR_P11_Pos 11 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2244 #define PIO_IDR_P11_Msk (_U_(0x1) << PIO_IDR_P11_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2245 #define PIO_IDR_P11 PIO_IDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P11_Msk instead */ 2246 #define PIO_IDR_P12_Pos 12 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2247 #define PIO_IDR_P12_Msk (_U_(0x1) << PIO_IDR_P12_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2248 #define PIO_IDR_P12 PIO_IDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P12_Msk instead */ 2249 #define PIO_IDR_P13_Pos 13 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2250 #define PIO_IDR_P13_Msk (_U_(0x1) << PIO_IDR_P13_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2251 #define PIO_IDR_P13 PIO_IDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P13_Msk instead */ 2252 #define PIO_IDR_P14_Pos 14 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2253 #define PIO_IDR_P14_Msk (_U_(0x1) << PIO_IDR_P14_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2254 #define PIO_IDR_P14 PIO_IDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P14_Msk instead */ 2255 #define PIO_IDR_P15_Pos 15 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2256 #define PIO_IDR_P15_Msk (_U_(0x1) << PIO_IDR_P15_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2257 #define PIO_IDR_P15 PIO_IDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P15_Msk instead */ 2258 #define PIO_IDR_P16_Pos 16 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2259 #define PIO_IDR_P16_Msk (_U_(0x1) << PIO_IDR_P16_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2260 #define PIO_IDR_P16 PIO_IDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P16_Msk instead */ 2261 #define PIO_IDR_P17_Pos 17 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2262 #define PIO_IDR_P17_Msk (_U_(0x1) << PIO_IDR_P17_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2263 #define PIO_IDR_P17 PIO_IDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P17_Msk instead */ 2264 #define PIO_IDR_P18_Pos 18 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2265 #define PIO_IDR_P18_Msk (_U_(0x1) << PIO_IDR_P18_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2266 #define PIO_IDR_P18 PIO_IDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P18_Msk instead */ 2267 #define PIO_IDR_P19_Pos 19 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2268 #define PIO_IDR_P19_Msk (_U_(0x1) << PIO_IDR_P19_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2269 #define PIO_IDR_P19 PIO_IDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P19_Msk instead */ 2270 #define PIO_IDR_P20_Pos 20 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2271 #define PIO_IDR_P20_Msk (_U_(0x1) << PIO_IDR_P20_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2272 #define PIO_IDR_P20 PIO_IDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P20_Msk instead */ 2273 #define PIO_IDR_P21_Pos 21 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2274 #define PIO_IDR_P21_Msk (_U_(0x1) << PIO_IDR_P21_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2275 #define PIO_IDR_P21 PIO_IDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P21_Msk instead */ 2276 #define PIO_IDR_P22_Pos 22 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2277 #define PIO_IDR_P22_Msk (_U_(0x1) << PIO_IDR_P22_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2278 #define PIO_IDR_P22 PIO_IDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P22_Msk instead */ 2279 #define PIO_IDR_P23_Pos 23 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2280 #define PIO_IDR_P23_Msk (_U_(0x1) << PIO_IDR_P23_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2281 #define PIO_IDR_P23 PIO_IDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P23_Msk instead */ 2282 #define PIO_IDR_P24_Pos 24 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2283 #define PIO_IDR_P24_Msk (_U_(0x1) << PIO_IDR_P24_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2284 #define PIO_IDR_P24 PIO_IDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P24_Msk instead */ 2285 #define PIO_IDR_P25_Pos 25 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2286 #define PIO_IDR_P25_Msk (_U_(0x1) << PIO_IDR_P25_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2287 #define PIO_IDR_P25 PIO_IDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P25_Msk instead */ 2288 #define PIO_IDR_P26_Pos 26 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2289 #define PIO_IDR_P26_Msk (_U_(0x1) << PIO_IDR_P26_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2290 #define PIO_IDR_P26 PIO_IDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P26_Msk instead */ 2291 #define PIO_IDR_P27_Pos 27 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2292 #define PIO_IDR_P27_Msk (_U_(0x1) << PIO_IDR_P27_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2293 #define PIO_IDR_P27 PIO_IDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P27_Msk instead */ 2294 #define PIO_IDR_P28_Pos 28 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2295 #define PIO_IDR_P28_Msk (_U_(0x1) << PIO_IDR_P28_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2296 #define PIO_IDR_P28 PIO_IDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P28_Msk instead */ 2297 #define PIO_IDR_P29_Pos 29 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2298 #define PIO_IDR_P29_Msk (_U_(0x1) << PIO_IDR_P29_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2299 #define PIO_IDR_P29 PIO_IDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P29_Msk instead */ 2300 #define PIO_IDR_P30_Pos 30 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2301 #define PIO_IDR_P30_Msk (_U_(0x1) << PIO_IDR_P30_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2302 #define PIO_IDR_P30 PIO_IDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P30_Msk instead */ 2303 #define PIO_IDR_P31_Pos 31 /**< (PIO_IDR) Input Change Interrupt Disable Position */ 2304 #define PIO_IDR_P31_Msk (_U_(0x1) << PIO_IDR_P31_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ 2305 #define PIO_IDR_P31 PIO_IDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P31_Msk instead */ 2306 #define PIO_IDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IDR) Register MASK (Use PIO_IDR_Msk instead) */ 2307 #define PIO_IDR_Msk _U_(0xFFFFFFFF) /**< (PIO_IDR) Register Mask */ 2308 2309 #define PIO_IDR_P_Pos 0 /**< (PIO_IDR Position) Input Change Interrupt Disable */ 2310 #define PIO_IDR_P_Msk (_U_(0xFFFFFFFF) << PIO_IDR_P_Pos) /**< (PIO_IDR Mask) P */ 2311 #define PIO_IDR_P(value) (PIO_IDR_P_Msk & ((value) << PIO_IDR_P_Pos)) 2312 2313 /* -------- PIO_IMR : (PIO Offset: 0x48) (R/ 32) Interrupt Mask Register -------- */ 2314 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2315 #if COMPONENT_TYPEDEF_STYLE == 'N' 2316 typedef union { 2317 struct { 2318 uint32_t P0:1; /**< bit: 0 Input Change Interrupt Mask */ 2319 uint32_t P1:1; /**< bit: 1 Input Change Interrupt Mask */ 2320 uint32_t P2:1; /**< bit: 2 Input Change Interrupt Mask */ 2321 uint32_t P3:1; /**< bit: 3 Input Change Interrupt Mask */ 2322 uint32_t P4:1; /**< bit: 4 Input Change Interrupt Mask */ 2323 uint32_t P5:1; /**< bit: 5 Input Change Interrupt Mask */ 2324 uint32_t P6:1; /**< bit: 6 Input Change Interrupt Mask */ 2325 uint32_t P7:1; /**< bit: 7 Input Change Interrupt Mask */ 2326 uint32_t P8:1; /**< bit: 8 Input Change Interrupt Mask */ 2327 uint32_t P9:1; /**< bit: 9 Input Change Interrupt Mask */ 2328 uint32_t P10:1; /**< bit: 10 Input Change Interrupt Mask */ 2329 uint32_t P11:1; /**< bit: 11 Input Change Interrupt Mask */ 2330 uint32_t P12:1; /**< bit: 12 Input Change Interrupt Mask */ 2331 uint32_t P13:1; /**< bit: 13 Input Change Interrupt Mask */ 2332 uint32_t P14:1; /**< bit: 14 Input Change Interrupt Mask */ 2333 uint32_t P15:1; /**< bit: 15 Input Change Interrupt Mask */ 2334 uint32_t P16:1; /**< bit: 16 Input Change Interrupt Mask */ 2335 uint32_t P17:1; /**< bit: 17 Input Change Interrupt Mask */ 2336 uint32_t P18:1; /**< bit: 18 Input Change Interrupt Mask */ 2337 uint32_t P19:1; /**< bit: 19 Input Change Interrupt Mask */ 2338 uint32_t P20:1; /**< bit: 20 Input Change Interrupt Mask */ 2339 uint32_t P21:1; /**< bit: 21 Input Change Interrupt Mask */ 2340 uint32_t P22:1; /**< bit: 22 Input Change Interrupt Mask */ 2341 uint32_t P23:1; /**< bit: 23 Input Change Interrupt Mask */ 2342 uint32_t P24:1; /**< bit: 24 Input Change Interrupt Mask */ 2343 uint32_t P25:1; /**< bit: 25 Input Change Interrupt Mask */ 2344 uint32_t P26:1; /**< bit: 26 Input Change Interrupt Mask */ 2345 uint32_t P27:1; /**< bit: 27 Input Change Interrupt Mask */ 2346 uint32_t P28:1; /**< bit: 28 Input Change Interrupt Mask */ 2347 uint32_t P29:1; /**< bit: 29 Input Change Interrupt Mask */ 2348 uint32_t P30:1; /**< bit: 30 Input Change Interrupt Mask */ 2349 uint32_t P31:1; /**< bit: 31 Input Change Interrupt Mask */ 2350 } bit; /**< Structure used for bit access */ 2351 struct { 2352 uint32_t P:32; /**< bit: 0..31 Input Change Interrupt Mask */ 2353 } vec; /**< Structure used for vec access */ 2354 uint32_t reg; /**< Type used for register access */ 2355 } PIO_IMR_Type; 2356 #endif 2357 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2358 2359 #define PIO_IMR_OFFSET (0x48) /**< (PIO_IMR) Interrupt Mask Register Offset */ 2360 2361 #define PIO_IMR_P0_Pos 0 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2362 #define PIO_IMR_P0_Msk (_U_(0x1) << PIO_IMR_P0_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2363 #define PIO_IMR_P0 PIO_IMR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P0_Msk instead */ 2364 #define PIO_IMR_P1_Pos 1 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2365 #define PIO_IMR_P1_Msk (_U_(0x1) << PIO_IMR_P1_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2366 #define PIO_IMR_P1 PIO_IMR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P1_Msk instead */ 2367 #define PIO_IMR_P2_Pos 2 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2368 #define PIO_IMR_P2_Msk (_U_(0x1) << PIO_IMR_P2_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2369 #define PIO_IMR_P2 PIO_IMR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P2_Msk instead */ 2370 #define PIO_IMR_P3_Pos 3 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2371 #define PIO_IMR_P3_Msk (_U_(0x1) << PIO_IMR_P3_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2372 #define PIO_IMR_P3 PIO_IMR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P3_Msk instead */ 2373 #define PIO_IMR_P4_Pos 4 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2374 #define PIO_IMR_P4_Msk (_U_(0x1) << PIO_IMR_P4_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2375 #define PIO_IMR_P4 PIO_IMR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P4_Msk instead */ 2376 #define PIO_IMR_P5_Pos 5 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2377 #define PIO_IMR_P5_Msk (_U_(0x1) << PIO_IMR_P5_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2378 #define PIO_IMR_P5 PIO_IMR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P5_Msk instead */ 2379 #define PIO_IMR_P6_Pos 6 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2380 #define PIO_IMR_P6_Msk (_U_(0x1) << PIO_IMR_P6_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2381 #define PIO_IMR_P6 PIO_IMR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P6_Msk instead */ 2382 #define PIO_IMR_P7_Pos 7 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2383 #define PIO_IMR_P7_Msk (_U_(0x1) << PIO_IMR_P7_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2384 #define PIO_IMR_P7 PIO_IMR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P7_Msk instead */ 2385 #define PIO_IMR_P8_Pos 8 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2386 #define PIO_IMR_P8_Msk (_U_(0x1) << PIO_IMR_P8_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2387 #define PIO_IMR_P8 PIO_IMR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P8_Msk instead */ 2388 #define PIO_IMR_P9_Pos 9 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2389 #define PIO_IMR_P9_Msk (_U_(0x1) << PIO_IMR_P9_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2390 #define PIO_IMR_P9 PIO_IMR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P9_Msk instead */ 2391 #define PIO_IMR_P10_Pos 10 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2392 #define PIO_IMR_P10_Msk (_U_(0x1) << PIO_IMR_P10_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2393 #define PIO_IMR_P10 PIO_IMR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P10_Msk instead */ 2394 #define PIO_IMR_P11_Pos 11 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2395 #define PIO_IMR_P11_Msk (_U_(0x1) << PIO_IMR_P11_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2396 #define PIO_IMR_P11 PIO_IMR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P11_Msk instead */ 2397 #define PIO_IMR_P12_Pos 12 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2398 #define PIO_IMR_P12_Msk (_U_(0x1) << PIO_IMR_P12_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2399 #define PIO_IMR_P12 PIO_IMR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P12_Msk instead */ 2400 #define PIO_IMR_P13_Pos 13 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2401 #define PIO_IMR_P13_Msk (_U_(0x1) << PIO_IMR_P13_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2402 #define PIO_IMR_P13 PIO_IMR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P13_Msk instead */ 2403 #define PIO_IMR_P14_Pos 14 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2404 #define PIO_IMR_P14_Msk (_U_(0x1) << PIO_IMR_P14_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2405 #define PIO_IMR_P14 PIO_IMR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P14_Msk instead */ 2406 #define PIO_IMR_P15_Pos 15 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2407 #define PIO_IMR_P15_Msk (_U_(0x1) << PIO_IMR_P15_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2408 #define PIO_IMR_P15 PIO_IMR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P15_Msk instead */ 2409 #define PIO_IMR_P16_Pos 16 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2410 #define PIO_IMR_P16_Msk (_U_(0x1) << PIO_IMR_P16_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2411 #define PIO_IMR_P16 PIO_IMR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P16_Msk instead */ 2412 #define PIO_IMR_P17_Pos 17 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2413 #define PIO_IMR_P17_Msk (_U_(0x1) << PIO_IMR_P17_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2414 #define PIO_IMR_P17 PIO_IMR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P17_Msk instead */ 2415 #define PIO_IMR_P18_Pos 18 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2416 #define PIO_IMR_P18_Msk (_U_(0x1) << PIO_IMR_P18_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2417 #define PIO_IMR_P18 PIO_IMR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P18_Msk instead */ 2418 #define PIO_IMR_P19_Pos 19 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2419 #define PIO_IMR_P19_Msk (_U_(0x1) << PIO_IMR_P19_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2420 #define PIO_IMR_P19 PIO_IMR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P19_Msk instead */ 2421 #define PIO_IMR_P20_Pos 20 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2422 #define PIO_IMR_P20_Msk (_U_(0x1) << PIO_IMR_P20_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2423 #define PIO_IMR_P20 PIO_IMR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P20_Msk instead */ 2424 #define PIO_IMR_P21_Pos 21 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2425 #define PIO_IMR_P21_Msk (_U_(0x1) << PIO_IMR_P21_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2426 #define PIO_IMR_P21 PIO_IMR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P21_Msk instead */ 2427 #define PIO_IMR_P22_Pos 22 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2428 #define PIO_IMR_P22_Msk (_U_(0x1) << PIO_IMR_P22_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2429 #define PIO_IMR_P22 PIO_IMR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P22_Msk instead */ 2430 #define PIO_IMR_P23_Pos 23 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2431 #define PIO_IMR_P23_Msk (_U_(0x1) << PIO_IMR_P23_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2432 #define PIO_IMR_P23 PIO_IMR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P23_Msk instead */ 2433 #define PIO_IMR_P24_Pos 24 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2434 #define PIO_IMR_P24_Msk (_U_(0x1) << PIO_IMR_P24_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2435 #define PIO_IMR_P24 PIO_IMR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P24_Msk instead */ 2436 #define PIO_IMR_P25_Pos 25 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2437 #define PIO_IMR_P25_Msk (_U_(0x1) << PIO_IMR_P25_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2438 #define PIO_IMR_P25 PIO_IMR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P25_Msk instead */ 2439 #define PIO_IMR_P26_Pos 26 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2440 #define PIO_IMR_P26_Msk (_U_(0x1) << PIO_IMR_P26_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2441 #define PIO_IMR_P26 PIO_IMR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P26_Msk instead */ 2442 #define PIO_IMR_P27_Pos 27 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2443 #define PIO_IMR_P27_Msk (_U_(0x1) << PIO_IMR_P27_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2444 #define PIO_IMR_P27 PIO_IMR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P27_Msk instead */ 2445 #define PIO_IMR_P28_Pos 28 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2446 #define PIO_IMR_P28_Msk (_U_(0x1) << PIO_IMR_P28_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2447 #define PIO_IMR_P28 PIO_IMR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P28_Msk instead */ 2448 #define PIO_IMR_P29_Pos 29 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2449 #define PIO_IMR_P29_Msk (_U_(0x1) << PIO_IMR_P29_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2450 #define PIO_IMR_P29 PIO_IMR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P29_Msk instead */ 2451 #define PIO_IMR_P30_Pos 30 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2452 #define PIO_IMR_P30_Msk (_U_(0x1) << PIO_IMR_P30_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2453 #define PIO_IMR_P30 PIO_IMR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P30_Msk instead */ 2454 #define PIO_IMR_P31_Pos 31 /**< (PIO_IMR) Input Change Interrupt Mask Position */ 2455 #define PIO_IMR_P31_Msk (_U_(0x1) << PIO_IMR_P31_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ 2456 #define PIO_IMR_P31 PIO_IMR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P31_Msk instead */ 2457 #define PIO_IMR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IMR) Register MASK (Use PIO_IMR_Msk instead) */ 2458 #define PIO_IMR_Msk _U_(0xFFFFFFFF) /**< (PIO_IMR) Register Mask */ 2459 2460 #define PIO_IMR_P_Pos 0 /**< (PIO_IMR Position) Input Change Interrupt Mask */ 2461 #define PIO_IMR_P_Msk (_U_(0xFFFFFFFF) << PIO_IMR_P_Pos) /**< (PIO_IMR Mask) P */ 2462 #define PIO_IMR_P(value) (PIO_IMR_P_Msk & ((value) << PIO_IMR_P_Pos)) 2463 2464 /* -------- PIO_ISR : (PIO Offset: 0x4c) (R/ 32) Interrupt Status Register -------- */ 2465 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2466 #if COMPONENT_TYPEDEF_STYLE == 'N' 2467 typedef union { 2468 struct { 2469 uint32_t P0:1; /**< bit: 0 Input Change Interrupt Status */ 2470 uint32_t P1:1; /**< bit: 1 Input Change Interrupt Status */ 2471 uint32_t P2:1; /**< bit: 2 Input Change Interrupt Status */ 2472 uint32_t P3:1; /**< bit: 3 Input Change Interrupt Status */ 2473 uint32_t P4:1; /**< bit: 4 Input Change Interrupt Status */ 2474 uint32_t P5:1; /**< bit: 5 Input Change Interrupt Status */ 2475 uint32_t P6:1; /**< bit: 6 Input Change Interrupt Status */ 2476 uint32_t P7:1; /**< bit: 7 Input Change Interrupt Status */ 2477 uint32_t P8:1; /**< bit: 8 Input Change Interrupt Status */ 2478 uint32_t P9:1; /**< bit: 9 Input Change Interrupt Status */ 2479 uint32_t P10:1; /**< bit: 10 Input Change Interrupt Status */ 2480 uint32_t P11:1; /**< bit: 11 Input Change Interrupt Status */ 2481 uint32_t P12:1; /**< bit: 12 Input Change Interrupt Status */ 2482 uint32_t P13:1; /**< bit: 13 Input Change Interrupt Status */ 2483 uint32_t P14:1; /**< bit: 14 Input Change Interrupt Status */ 2484 uint32_t P15:1; /**< bit: 15 Input Change Interrupt Status */ 2485 uint32_t P16:1; /**< bit: 16 Input Change Interrupt Status */ 2486 uint32_t P17:1; /**< bit: 17 Input Change Interrupt Status */ 2487 uint32_t P18:1; /**< bit: 18 Input Change Interrupt Status */ 2488 uint32_t P19:1; /**< bit: 19 Input Change Interrupt Status */ 2489 uint32_t P20:1; /**< bit: 20 Input Change Interrupt Status */ 2490 uint32_t P21:1; /**< bit: 21 Input Change Interrupt Status */ 2491 uint32_t P22:1; /**< bit: 22 Input Change Interrupt Status */ 2492 uint32_t P23:1; /**< bit: 23 Input Change Interrupt Status */ 2493 uint32_t P24:1; /**< bit: 24 Input Change Interrupt Status */ 2494 uint32_t P25:1; /**< bit: 25 Input Change Interrupt Status */ 2495 uint32_t P26:1; /**< bit: 26 Input Change Interrupt Status */ 2496 uint32_t P27:1; /**< bit: 27 Input Change Interrupt Status */ 2497 uint32_t P28:1; /**< bit: 28 Input Change Interrupt Status */ 2498 uint32_t P29:1; /**< bit: 29 Input Change Interrupt Status */ 2499 uint32_t P30:1; /**< bit: 30 Input Change Interrupt Status */ 2500 uint32_t P31:1; /**< bit: 31 Input Change Interrupt Status */ 2501 } bit; /**< Structure used for bit access */ 2502 struct { 2503 uint32_t P:32; /**< bit: 0..31 Input Change Interrupt Status */ 2504 } vec; /**< Structure used for vec access */ 2505 uint32_t reg; /**< Type used for register access */ 2506 } PIO_ISR_Type; 2507 #endif 2508 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2509 2510 #define PIO_ISR_OFFSET (0x4C) /**< (PIO_ISR) Interrupt Status Register Offset */ 2511 2512 #define PIO_ISR_P0_Pos 0 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2513 #define PIO_ISR_P0_Msk (_U_(0x1) << PIO_ISR_P0_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2514 #define PIO_ISR_P0 PIO_ISR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P0_Msk instead */ 2515 #define PIO_ISR_P1_Pos 1 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2516 #define PIO_ISR_P1_Msk (_U_(0x1) << PIO_ISR_P1_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2517 #define PIO_ISR_P1 PIO_ISR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P1_Msk instead */ 2518 #define PIO_ISR_P2_Pos 2 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2519 #define PIO_ISR_P2_Msk (_U_(0x1) << PIO_ISR_P2_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2520 #define PIO_ISR_P2 PIO_ISR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P2_Msk instead */ 2521 #define PIO_ISR_P3_Pos 3 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2522 #define PIO_ISR_P3_Msk (_U_(0x1) << PIO_ISR_P3_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2523 #define PIO_ISR_P3 PIO_ISR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P3_Msk instead */ 2524 #define PIO_ISR_P4_Pos 4 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2525 #define PIO_ISR_P4_Msk (_U_(0x1) << PIO_ISR_P4_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2526 #define PIO_ISR_P4 PIO_ISR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P4_Msk instead */ 2527 #define PIO_ISR_P5_Pos 5 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2528 #define PIO_ISR_P5_Msk (_U_(0x1) << PIO_ISR_P5_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2529 #define PIO_ISR_P5 PIO_ISR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P5_Msk instead */ 2530 #define PIO_ISR_P6_Pos 6 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2531 #define PIO_ISR_P6_Msk (_U_(0x1) << PIO_ISR_P6_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2532 #define PIO_ISR_P6 PIO_ISR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P6_Msk instead */ 2533 #define PIO_ISR_P7_Pos 7 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2534 #define PIO_ISR_P7_Msk (_U_(0x1) << PIO_ISR_P7_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2535 #define PIO_ISR_P7 PIO_ISR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P7_Msk instead */ 2536 #define PIO_ISR_P8_Pos 8 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2537 #define PIO_ISR_P8_Msk (_U_(0x1) << PIO_ISR_P8_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2538 #define PIO_ISR_P8 PIO_ISR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P8_Msk instead */ 2539 #define PIO_ISR_P9_Pos 9 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2540 #define PIO_ISR_P9_Msk (_U_(0x1) << PIO_ISR_P9_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2541 #define PIO_ISR_P9 PIO_ISR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P9_Msk instead */ 2542 #define PIO_ISR_P10_Pos 10 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2543 #define PIO_ISR_P10_Msk (_U_(0x1) << PIO_ISR_P10_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2544 #define PIO_ISR_P10 PIO_ISR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P10_Msk instead */ 2545 #define PIO_ISR_P11_Pos 11 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2546 #define PIO_ISR_P11_Msk (_U_(0x1) << PIO_ISR_P11_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2547 #define PIO_ISR_P11 PIO_ISR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P11_Msk instead */ 2548 #define PIO_ISR_P12_Pos 12 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2549 #define PIO_ISR_P12_Msk (_U_(0x1) << PIO_ISR_P12_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2550 #define PIO_ISR_P12 PIO_ISR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P12_Msk instead */ 2551 #define PIO_ISR_P13_Pos 13 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2552 #define PIO_ISR_P13_Msk (_U_(0x1) << PIO_ISR_P13_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2553 #define PIO_ISR_P13 PIO_ISR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P13_Msk instead */ 2554 #define PIO_ISR_P14_Pos 14 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2555 #define PIO_ISR_P14_Msk (_U_(0x1) << PIO_ISR_P14_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2556 #define PIO_ISR_P14 PIO_ISR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P14_Msk instead */ 2557 #define PIO_ISR_P15_Pos 15 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2558 #define PIO_ISR_P15_Msk (_U_(0x1) << PIO_ISR_P15_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2559 #define PIO_ISR_P15 PIO_ISR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P15_Msk instead */ 2560 #define PIO_ISR_P16_Pos 16 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2561 #define PIO_ISR_P16_Msk (_U_(0x1) << PIO_ISR_P16_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2562 #define PIO_ISR_P16 PIO_ISR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P16_Msk instead */ 2563 #define PIO_ISR_P17_Pos 17 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2564 #define PIO_ISR_P17_Msk (_U_(0x1) << PIO_ISR_P17_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2565 #define PIO_ISR_P17 PIO_ISR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P17_Msk instead */ 2566 #define PIO_ISR_P18_Pos 18 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2567 #define PIO_ISR_P18_Msk (_U_(0x1) << PIO_ISR_P18_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2568 #define PIO_ISR_P18 PIO_ISR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P18_Msk instead */ 2569 #define PIO_ISR_P19_Pos 19 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2570 #define PIO_ISR_P19_Msk (_U_(0x1) << PIO_ISR_P19_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2571 #define PIO_ISR_P19 PIO_ISR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P19_Msk instead */ 2572 #define PIO_ISR_P20_Pos 20 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2573 #define PIO_ISR_P20_Msk (_U_(0x1) << PIO_ISR_P20_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2574 #define PIO_ISR_P20 PIO_ISR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P20_Msk instead */ 2575 #define PIO_ISR_P21_Pos 21 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2576 #define PIO_ISR_P21_Msk (_U_(0x1) << PIO_ISR_P21_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2577 #define PIO_ISR_P21 PIO_ISR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P21_Msk instead */ 2578 #define PIO_ISR_P22_Pos 22 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2579 #define PIO_ISR_P22_Msk (_U_(0x1) << PIO_ISR_P22_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2580 #define PIO_ISR_P22 PIO_ISR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P22_Msk instead */ 2581 #define PIO_ISR_P23_Pos 23 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2582 #define PIO_ISR_P23_Msk (_U_(0x1) << PIO_ISR_P23_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2583 #define PIO_ISR_P23 PIO_ISR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P23_Msk instead */ 2584 #define PIO_ISR_P24_Pos 24 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2585 #define PIO_ISR_P24_Msk (_U_(0x1) << PIO_ISR_P24_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2586 #define PIO_ISR_P24 PIO_ISR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P24_Msk instead */ 2587 #define PIO_ISR_P25_Pos 25 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2588 #define PIO_ISR_P25_Msk (_U_(0x1) << PIO_ISR_P25_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2589 #define PIO_ISR_P25 PIO_ISR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P25_Msk instead */ 2590 #define PIO_ISR_P26_Pos 26 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2591 #define PIO_ISR_P26_Msk (_U_(0x1) << PIO_ISR_P26_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2592 #define PIO_ISR_P26 PIO_ISR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P26_Msk instead */ 2593 #define PIO_ISR_P27_Pos 27 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2594 #define PIO_ISR_P27_Msk (_U_(0x1) << PIO_ISR_P27_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2595 #define PIO_ISR_P27 PIO_ISR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P27_Msk instead */ 2596 #define PIO_ISR_P28_Pos 28 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2597 #define PIO_ISR_P28_Msk (_U_(0x1) << PIO_ISR_P28_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2598 #define PIO_ISR_P28 PIO_ISR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P28_Msk instead */ 2599 #define PIO_ISR_P29_Pos 29 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2600 #define PIO_ISR_P29_Msk (_U_(0x1) << PIO_ISR_P29_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2601 #define PIO_ISR_P29 PIO_ISR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P29_Msk instead */ 2602 #define PIO_ISR_P30_Pos 30 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2603 #define PIO_ISR_P30_Msk (_U_(0x1) << PIO_ISR_P30_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2604 #define PIO_ISR_P30 PIO_ISR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P30_Msk instead */ 2605 #define PIO_ISR_P31_Pos 31 /**< (PIO_ISR) Input Change Interrupt Status Position */ 2606 #define PIO_ISR_P31_Msk (_U_(0x1) << PIO_ISR_P31_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ 2607 #define PIO_ISR_P31 PIO_ISR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P31_Msk instead */ 2608 #define PIO_ISR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_ISR) Register MASK (Use PIO_ISR_Msk instead) */ 2609 #define PIO_ISR_Msk _U_(0xFFFFFFFF) /**< (PIO_ISR) Register Mask */ 2610 2611 #define PIO_ISR_P_Pos 0 /**< (PIO_ISR Position) Input Change Interrupt Status */ 2612 #define PIO_ISR_P_Msk (_U_(0xFFFFFFFF) << PIO_ISR_P_Pos) /**< (PIO_ISR Mask) P */ 2613 #define PIO_ISR_P(value) (PIO_ISR_P_Msk & ((value) << PIO_ISR_P_Pos)) 2614 2615 /* -------- PIO_MDER : (PIO Offset: 0x50) (/W 32) Multi-driver Enable Register -------- */ 2616 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2617 #if COMPONENT_TYPEDEF_STYLE == 'N' 2618 typedef union { 2619 struct { 2620 uint32_t P0:1; /**< bit: 0 Multi-drive Enable */ 2621 uint32_t P1:1; /**< bit: 1 Multi-drive Enable */ 2622 uint32_t P2:1; /**< bit: 2 Multi-drive Enable */ 2623 uint32_t P3:1; /**< bit: 3 Multi-drive Enable */ 2624 uint32_t P4:1; /**< bit: 4 Multi-drive Enable */ 2625 uint32_t P5:1; /**< bit: 5 Multi-drive Enable */ 2626 uint32_t P6:1; /**< bit: 6 Multi-drive Enable */ 2627 uint32_t P7:1; /**< bit: 7 Multi-drive Enable */ 2628 uint32_t P8:1; /**< bit: 8 Multi-drive Enable */ 2629 uint32_t P9:1; /**< bit: 9 Multi-drive Enable */ 2630 uint32_t P10:1; /**< bit: 10 Multi-drive Enable */ 2631 uint32_t P11:1; /**< bit: 11 Multi-drive Enable */ 2632 uint32_t P12:1; /**< bit: 12 Multi-drive Enable */ 2633 uint32_t P13:1; /**< bit: 13 Multi-drive Enable */ 2634 uint32_t P14:1; /**< bit: 14 Multi-drive Enable */ 2635 uint32_t P15:1; /**< bit: 15 Multi-drive Enable */ 2636 uint32_t P16:1; /**< bit: 16 Multi-drive Enable */ 2637 uint32_t P17:1; /**< bit: 17 Multi-drive Enable */ 2638 uint32_t P18:1; /**< bit: 18 Multi-drive Enable */ 2639 uint32_t P19:1; /**< bit: 19 Multi-drive Enable */ 2640 uint32_t P20:1; /**< bit: 20 Multi-drive Enable */ 2641 uint32_t P21:1; /**< bit: 21 Multi-drive Enable */ 2642 uint32_t P22:1; /**< bit: 22 Multi-drive Enable */ 2643 uint32_t P23:1; /**< bit: 23 Multi-drive Enable */ 2644 uint32_t P24:1; /**< bit: 24 Multi-drive Enable */ 2645 uint32_t P25:1; /**< bit: 25 Multi-drive Enable */ 2646 uint32_t P26:1; /**< bit: 26 Multi-drive Enable */ 2647 uint32_t P27:1; /**< bit: 27 Multi-drive Enable */ 2648 uint32_t P28:1; /**< bit: 28 Multi-drive Enable */ 2649 uint32_t P29:1; /**< bit: 29 Multi-drive Enable */ 2650 uint32_t P30:1; /**< bit: 30 Multi-drive Enable */ 2651 uint32_t P31:1; /**< bit: 31 Multi-drive Enable */ 2652 } bit; /**< Structure used for bit access */ 2653 struct { 2654 uint32_t P:32; /**< bit: 0..31 Multi-drive Enable */ 2655 } vec; /**< Structure used for vec access */ 2656 uint32_t reg; /**< Type used for register access */ 2657 } PIO_MDER_Type; 2658 #endif 2659 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2660 2661 #define PIO_MDER_OFFSET (0x50) /**< (PIO_MDER) Multi-driver Enable Register Offset */ 2662 2663 #define PIO_MDER_P0_Pos 0 /**< (PIO_MDER) Multi-drive Enable Position */ 2664 #define PIO_MDER_P0_Msk (_U_(0x1) << PIO_MDER_P0_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2665 #define PIO_MDER_P0 PIO_MDER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P0_Msk instead */ 2666 #define PIO_MDER_P1_Pos 1 /**< (PIO_MDER) Multi-drive Enable Position */ 2667 #define PIO_MDER_P1_Msk (_U_(0x1) << PIO_MDER_P1_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2668 #define PIO_MDER_P1 PIO_MDER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P1_Msk instead */ 2669 #define PIO_MDER_P2_Pos 2 /**< (PIO_MDER) Multi-drive Enable Position */ 2670 #define PIO_MDER_P2_Msk (_U_(0x1) << PIO_MDER_P2_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2671 #define PIO_MDER_P2 PIO_MDER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P2_Msk instead */ 2672 #define PIO_MDER_P3_Pos 3 /**< (PIO_MDER) Multi-drive Enable Position */ 2673 #define PIO_MDER_P3_Msk (_U_(0x1) << PIO_MDER_P3_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2674 #define PIO_MDER_P3 PIO_MDER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P3_Msk instead */ 2675 #define PIO_MDER_P4_Pos 4 /**< (PIO_MDER) Multi-drive Enable Position */ 2676 #define PIO_MDER_P4_Msk (_U_(0x1) << PIO_MDER_P4_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2677 #define PIO_MDER_P4 PIO_MDER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P4_Msk instead */ 2678 #define PIO_MDER_P5_Pos 5 /**< (PIO_MDER) Multi-drive Enable Position */ 2679 #define PIO_MDER_P5_Msk (_U_(0x1) << PIO_MDER_P5_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2680 #define PIO_MDER_P5 PIO_MDER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P5_Msk instead */ 2681 #define PIO_MDER_P6_Pos 6 /**< (PIO_MDER) Multi-drive Enable Position */ 2682 #define PIO_MDER_P6_Msk (_U_(0x1) << PIO_MDER_P6_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2683 #define PIO_MDER_P6 PIO_MDER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P6_Msk instead */ 2684 #define PIO_MDER_P7_Pos 7 /**< (PIO_MDER) Multi-drive Enable Position */ 2685 #define PIO_MDER_P7_Msk (_U_(0x1) << PIO_MDER_P7_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2686 #define PIO_MDER_P7 PIO_MDER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P7_Msk instead */ 2687 #define PIO_MDER_P8_Pos 8 /**< (PIO_MDER) Multi-drive Enable Position */ 2688 #define PIO_MDER_P8_Msk (_U_(0x1) << PIO_MDER_P8_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2689 #define PIO_MDER_P8 PIO_MDER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P8_Msk instead */ 2690 #define PIO_MDER_P9_Pos 9 /**< (PIO_MDER) Multi-drive Enable Position */ 2691 #define PIO_MDER_P9_Msk (_U_(0x1) << PIO_MDER_P9_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2692 #define PIO_MDER_P9 PIO_MDER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P9_Msk instead */ 2693 #define PIO_MDER_P10_Pos 10 /**< (PIO_MDER) Multi-drive Enable Position */ 2694 #define PIO_MDER_P10_Msk (_U_(0x1) << PIO_MDER_P10_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2695 #define PIO_MDER_P10 PIO_MDER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P10_Msk instead */ 2696 #define PIO_MDER_P11_Pos 11 /**< (PIO_MDER) Multi-drive Enable Position */ 2697 #define PIO_MDER_P11_Msk (_U_(0x1) << PIO_MDER_P11_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2698 #define PIO_MDER_P11 PIO_MDER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P11_Msk instead */ 2699 #define PIO_MDER_P12_Pos 12 /**< (PIO_MDER) Multi-drive Enable Position */ 2700 #define PIO_MDER_P12_Msk (_U_(0x1) << PIO_MDER_P12_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2701 #define PIO_MDER_P12 PIO_MDER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P12_Msk instead */ 2702 #define PIO_MDER_P13_Pos 13 /**< (PIO_MDER) Multi-drive Enable Position */ 2703 #define PIO_MDER_P13_Msk (_U_(0x1) << PIO_MDER_P13_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2704 #define PIO_MDER_P13 PIO_MDER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P13_Msk instead */ 2705 #define PIO_MDER_P14_Pos 14 /**< (PIO_MDER) Multi-drive Enable Position */ 2706 #define PIO_MDER_P14_Msk (_U_(0x1) << PIO_MDER_P14_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2707 #define PIO_MDER_P14 PIO_MDER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P14_Msk instead */ 2708 #define PIO_MDER_P15_Pos 15 /**< (PIO_MDER) Multi-drive Enable Position */ 2709 #define PIO_MDER_P15_Msk (_U_(0x1) << PIO_MDER_P15_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2710 #define PIO_MDER_P15 PIO_MDER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P15_Msk instead */ 2711 #define PIO_MDER_P16_Pos 16 /**< (PIO_MDER) Multi-drive Enable Position */ 2712 #define PIO_MDER_P16_Msk (_U_(0x1) << PIO_MDER_P16_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2713 #define PIO_MDER_P16 PIO_MDER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P16_Msk instead */ 2714 #define PIO_MDER_P17_Pos 17 /**< (PIO_MDER) Multi-drive Enable Position */ 2715 #define PIO_MDER_P17_Msk (_U_(0x1) << PIO_MDER_P17_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2716 #define PIO_MDER_P17 PIO_MDER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P17_Msk instead */ 2717 #define PIO_MDER_P18_Pos 18 /**< (PIO_MDER) Multi-drive Enable Position */ 2718 #define PIO_MDER_P18_Msk (_U_(0x1) << PIO_MDER_P18_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2719 #define PIO_MDER_P18 PIO_MDER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P18_Msk instead */ 2720 #define PIO_MDER_P19_Pos 19 /**< (PIO_MDER) Multi-drive Enable Position */ 2721 #define PIO_MDER_P19_Msk (_U_(0x1) << PIO_MDER_P19_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2722 #define PIO_MDER_P19 PIO_MDER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P19_Msk instead */ 2723 #define PIO_MDER_P20_Pos 20 /**< (PIO_MDER) Multi-drive Enable Position */ 2724 #define PIO_MDER_P20_Msk (_U_(0x1) << PIO_MDER_P20_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2725 #define PIO_MDER_P20 PIO_MDER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P20_Msk instead */ 2726 #define PIO_MDER_P21_Pos 21 /**< (PIO_MDER) Multi-drive Enable Position */ 2727 #define PIO_MDER_P21_Msk (_U_(0x1) << PIO_MDER_P21_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2728 #define PIO_MDER_P21 PIO_MDER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P21_Msk instead */ 2729 #define PIO_MDER_P22_Pos 22 /**< (PIO_MDER) Multi-drive Enable Position */ 2730 #define PIO_MDER_P22_Msk (_U_(0x1) << PIO_MDER_P22_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2731 #define PIO_MDER_P22 PIO_MDER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P22_Msk instead */ 2732 #define PIO_MDER_P23_Pos 23 /**< (PIO_MDER) Multi-drive Enable Position */ 2733 #define PIO_MDER_P23_Msk (_U_(0x1) << PIO_MDER_P23_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2734 #define PIO_MDER_P23 PIO_MDER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P23_Msk instead */ 2735 #define PIO_MDER_P24_Pos 24 /**< (PIO_MDER) Multi-drive Enable Position */ 2736 #define PIO_MDER_P24_Msk (_U_(0x1) << PIO_MDER_P24_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2737 #define PIO_MDER_P24 PIO_MDER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P24_Msk instead */ 2738 #define PIO_MDER_P25_Pos 25 /**< (PIO_MDER) Multi-drive Enable Position */ 2739 #define PIO_MDER_P25_Msk (_U_(0x1) << PIO_MDER_P25_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2740 #define PIO_MDER_P25 PIO_MDER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P25_Msk instead */ 2741 #define PIO_MDER_P26_Pos 26 /**< (PIO_MDER) Multi-drive Enable Position */ 2742 #define PIO_MDER_P26_Msk (_U_(0x1) << PIO_MDER_P26_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2743 #define PIO_MDER_P26 PIO_MDER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P26_Msk instead */ 2744 #define PIO_MDER_P27_Pos 27 /**< (PIO_MDER) Multi-drive Enable Position */ 2745 #define PIO_MDER_P27_Msk (_U_(0x1) << PIO_MDER_P27_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2746 #define PIO_MDER_P27 PIO_MDER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P27_Msk instead */ 2747 #define PIO_MDER_P28_Pos 28 /**< (PIO_MDER) Multi-drive Enable Position */ 2748 #define PIO_MDER_P28_Msk (_U_(0x1) << PIO_MDER_P28_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2749 #define PIO_MDER_P28 PIO_MDER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P28_Msk instead */ 2750 #define PIO_MDER_P29_Pos 29 /**< (PIO_MDER) Multi-drive Enable Position */ 2751 #define PIO_MDER_P29_Msk (_U_(0x1) << PIO_MDER_P29_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2752 #define PIO_MDER_P29 PIO_MDER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P29_Msk instead */ 2753 #define PIO_MDER_P30_Pos 30 /**< (PIO_MDER) Multi-drive Enable Position */ 2754 #define PIO_MDER_P30_Msk (_U_(0x1) << PIO_MDER_P30_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2755 #define PIO_MDER_P30 PIO_MDER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P30_Msk instead */ 2756 #define PIO_MDER_P31_Pos 31 /**< (PIO_MDER) Multi-drive Enable Position */ 2757 #define PIO_MDER_P31_Msk (_U_(0x1) << PIO_MDER_P31_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ 2758 #define PIO_MDER_P31 PIO_MDER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P31_Msk instead */ 2759 #define PIO_MDER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_MDER) Register MASK (Use PIO_MDER_Msk instead) */ 2760 #define PIO_MDER_Msk _U_(0xFFFFFFFF) /**< (PIO_MDER) Register Mask */ 2761 2762 #define PIO_MDER_P_Pos 0 /**< (PIO_MDER Position) Multi-drive Enable */ 2763 #define PIO_MDER_P_Msk (_U_(0xFFFFFFFF) << PIO_MDER_P_Pos) /**< (PIO_MDER Mask) P */ 2764 #define PIO_MDER_P(value) (PIO_MDER_P_Msk & ((value) << PIO_MDER_P_Pos)) 2765 2766 /* -------- PIO_MDDR : (PIO Offset: 0x54) (/W 32) Multi-driver Disable Register -------- */ 2767 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2768 #if COMPONENT_TYPEDEF_STYLE == 'N' 2769 typedef union { 2770 struct { 2771 uint32_t P0:1; /**< bit: 0 Multi-drive Disable */ 2772 uint32_t P1:1; /**< bit: 1 Multi-drive Disable */ 2773 uint32_t P2:1; /**< bit: 2 Multi-drive Disable */ 2774 uint32_t P3:1; /**< bit: 3 Multi-drive Disable */ 2775 uint32_t P4:1; /**< bit: 4 Multi-drive Disable */ 2776 uint32_t P5:1; /**< bit: 5 Multi-drive Disable */ 2777 uint32_t P6:1; /**< bit: 6 Multi-drive Disable */ 2778 uint32_t P7:1; /**< bit: 7 Multi-drive Disable */ 2779 uint32_t P8:1; /**< bit: 8 Multi-drive Disable */ 2780 uint32_t P9:1; /**< bit: 9 Multi-drive Disable */ 2781 uint32_t P10:1; /**< bit: 10 Multi-drive Disable */ 2782 uint32_t P11:1; /**< bit: 11 Multi-drive Disable */ 2783 uint32_t P12:1; /**< bit: 12 Multi-drive Disable */ 2784 uint32_t P13:1; /**< bit: 13 Multi-drive Disable */ 2785 uint32_t P14:1; /**< bit: 14 Multi-drive Disable */ 2786 uint32_t P15:1; /**< bit: 15 Multi-drive Disable */ 2787 uint32_t P16:1; /**< bit: 16 Multi-drive Disable */ 2788 uint32_t P17:1; /**< bit: 17 Multi-drive Disable */ 2789 uint32_t P18:1; /**< bit: 18 Multi-drive Disable */ 2790 uint32_t P19:1; /**< bit: 19 Multi-drive Disable */ 2791 uint32_t P20:1; /**< bit: 20 Multi-drive Disable */ 2792 uint32_t P21:1; /**< bit: 21 Multi-drive Disable */ 2793 uint32_t P22:1; /**< bit: 22 Multi-drive Disable */ 2794 uint32_t P23:1; /**< bit: 23 Multi-drive Disable */ 2795 uint32_t P24:1; /**< bit: 24 Multi-drive Disable */ 2796 uint32_t P25:1; /**< bit: 25 Multi-drive Disable */ 2797 uint32_t P26:1; /**< bit: 26 Multi-drive Disable */ 2798 uint32_t P27:1; /**< bit: 27 Multi-drive Disable */ 2799 uint32_t P28:1; /**< bit: 28 Multi-drive Disable */ 2800 uint32_t P29:1; /**< bit: 29 Multi-drive Disable */ 2801 uint32_t P30:1; /**< bit: 30 Multi-drive Disable */ 2802 uint32_t P31:1; /**< bit: 31 Multi-drive Disable */ 2803 } bit; /**< Structure used for bit access */ 2804 struct { 2805 uint32_t P:32; /**< bit: 0..31 Multi-drive Disable */ 2806 } vec; /**< Structure used for vec access */ 2807 uint32_t reg; /**< Type used for register access */ 2808 } PIO_MDDR_Type; 2809 #endif 2810 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2811 2812 #define PIO_MDDR_OFFSET (0x54) /**< (PIO_MDDR) Multi-driver Disable Register Offset */ 2813 2814 #define PIO_MDDR_P0_Pos 0 /**< (PIO_MDDR) Multi-drive Disable Position */ 2815 #define PIO_MDDR_P0_Msk (_U_(0x1) << PIO_MDDR_P0_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2816 #define PIO_MDDR_P0 PIO_MDDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P0_Msk instead */ 2817 #define PIO_MDDR_P1_Pos 1 /**< (PIO_MDDR) Multi-drive Disable Position */ 2818 #define PIO_MDDR_P1_Msk (_U_(0x1) << PIO_MDDR_P1_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2819 #define PIO_MDDR_P1 PIO_MDDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P1_Msk instead */ 2820 #define PIO_MDDR_P2_Pos 2 /**< (PIO_MDDR) Multi-drive Disable Position */ 2821 #define PIO_MDDR_P2_Msk (_U_(0x1) << PIO_MDDR_P2_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2822 #define PIO_MDDR_P2 PIO_MDDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P2_Msk instead */ 2823 #define PIO_MDDR_P3_Pos 3 /**< (PIO_MDDR) Multi-drive Disable Position */ 2824 #define PIO_MDDR_P3_Msk (_U_(0x1) << PIO_MDDR_P3_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2825 #define PIO_MDDR_P3 PIO_MDDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P3_Msk instead */ 2826 #define PIO_MDDR_P4_Pos 4 /**< (PIO_MDDR) Multi-drive Disable Position */ 2827 #define PIO_MDDR_P4_Msk (_U_(0x1) << PIO_MDDR_P4_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2828 #define PIO_MDDR_P4 PIO_MDDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P4_Msk instead */ 2829 #define PIO_MDDR_P5_Pos 5 /**< (PIO_MDDR) Multi-drive Disable Position */ 2830 #define PIO_MDDR_P5_Msk (_U_(0x1) << PIO_MDDR_P5_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2831 #define PIO_MDDR_P5 PIO_MDDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P5_Msk instead */ 2832 #define PIO_MDDR_P6_Pos 6 /**< (PIO_MDDR) Multi-drive Disable Position */ 2833 #define PIO_MDDR_P6_Msk (_U_(0x1) << PIO_MDDR_P6_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2834 #define PIO_MDDR_P6 PIO_MDDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P6_Msk instead */ 2835 #define PIO_MDDR_P7_Pos 7 /**< (PIO_MDDR) Multi-drive Disable Position */ 2836 #define PIO_MDDR_P7_Msk (_U_(0x1) << PIO_MDDR_P7_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2837 #define PIO_MDDR_P7 PIO_MDDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P7_Msk instead */ 2838 #define PIO_MDDR_P8_Pos 8 /**< (PIO_MDDR) Multi-drive Disable Position */ 2839 #define PIO_MDDR_P8_Msk (_U_(0x1) << PIO_MDDR_P8_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2840 #define PIO_MDDR_P8 PIO_MDDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P8_Msk instead */ 2841 #define PIO_MDDR_P9_Pos 9 /**< (PIO_MDDR) Multi-drive Disable Position */ 2842 #define PIO_MDDR_P9_Msk (_U_(0x1) << PIO_MDDR_P9_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2843 #define PIO_MDDR_P9 PIO_MDDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P9_Msk instead */ 2844 #define PIO_MDDR_P10_Pos 10 /**< (PIO_MDDR) Multi-drive Disable Position */ 2845 #define PIO_MDDR_P10_Msk (_U_(0x1) << PIO_MDDR_P10_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2846 #define PIO_MDDR_P10 PIO_MDDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P10_Msk instead */ 2847 #define PIO_MDDR_P11_Pos 11 /**< (PIO_MDDR) Multi-drive Disable Position */ 2848 #define PIO_MDDR_P11_Msk (_U_(0x1) << PIO_MDDR_P11_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2849 #define PIO_MDDR_P11 PIO_MDDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P11_Msk instead */ 2850 #define PIO_MDDR_P12_Pos 12 /**< (PIO_MDDR) Multi-drive Disable Position */ 2851 #define PIO_MDDR_P12_Msk (_U_(0x1) << PIO_MDDR_P12_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2852 #define PIO_MDDR_P12 PIO_MDDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P12_Msk instead */ 2853 #define PIO_MDDR_P13_Pos 13 /**< (PIO_MDDR) Multi-drive Disable Position */ 2854 #define PIO_MDDR_P13_Msk (_U_(0x1) << PIO_MDDR_P13_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2855 #define PIO_MDDR_P13 PIO_MDDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P13_Msk instead */ 2856 #define PIO_MDDR_P14_Pos 14 /**< (PIO_MDDR) Multi-drive Disable Position */ 2857 #define PIO_MDDR_P14_Msk (_U_(0x1) << PIO_MDDR_P14_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2858 #define PIO_MDDR_P14 PIO_MDDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P14_Msk instead */ 2859 #define PIO_MDDR_P15_Pos 15 /**< (PIO_MDDR) Multi-drive Disable Position */ 2860 #define PIO_MDDR_P15_Msk (_U_(0x1) << PIO_MDDR_P15_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2861 #define PIO_MDDR_P15 PIO_MDDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P15_Msk instead */ 2862 #define PIO_MDDR_P16_Pos 16 /**< (PIO_MDDR) Multi-drive Disable Position */ 2863 #define PIO_MDDR_P16_Msk (_U_(0x1) << PIO_MDDR_P16_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2864 #define PIO_MDDR_P16 PIO_MDDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P16_Msk instead */ 2865 #define PIO_MDDR_P17_Pos 17 /**< (PIO_MDDR) Multi-drive Disable Position */ 2866 #define PIO_MDDR_P17_Msk (_U_(0x1) << PIO_MDDR_P17_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2867 #define PIO_MDDR_P17 PIO_MDDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P17_Msk instead */ 2868 #define PIO_MDDR_P18_Pos 18 /**< (PIO_MDDR) Multi-drive Disable Position */ 2869 #define PIO_MDDR_P18_Msk (_U_(0x1) << PIO_MDDR_P18_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2870 #define PIO_MDDR_P18 PIO_MDDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P18_Msk instead */ 2871 #define PIO_MDDR_P19_Pos 19 /**< (PIO_MDDR) Multi-drive Disable Position */ 2872 #define PIO_MDDR_P19_Msk (_U_(0x1) << PIO_MDDR_P19_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2873 #define PIO_MDDR_P19 PIO_MDDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P19_Msk instead */ 2874 #define PIO_MDDR_P20_Pos 20 /**< (PIO_MDDR) Multi-drive Disable Position */ 2875 #define PIO_MDDR_P20_Msk (_U_(0x1) << PIO_MDDR_P20_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2876 #define PIO_MDDR_P20 PIO_MDDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P20_Msk instead */ 2877 #define PIO_MDDR_P21_Pos 21 /**< (PIO_MDDR) Multi-drive Disable Position */ 2878 #define PIO_MDDR_P21_Msk (_U_(0x1) << PIO_MDDR_P21_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2879 #define PIO_MDDR_P21 PIO_MDDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P21_Msk instead */ 2880 #define PIO_MDDR_P22_Pos 22 /**< (PIO_MDDR) Multi-drive Disable Position */ 2881 #define PIO_MDDR_P22_Msk (_U_(0x1) << PIO_MDDR_P22_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2882 #define PIO_MDDR_P22 PIO_MDDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P22_Msk instead */ 2883 #define PIO_MDDR_P23_Pos 23 /**< (PIO_MDDR) Multi-drive Disable Position */ 2884 #define PIO_MDDR_P23_Msk (_U_(0x1) << PIO_MDDR_P23_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2885 #define PIO_MDDR_P23 PIO_MDDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P23_Msk instead */ 2886 #define PIO_MDDR_P24_Pos 24 /**< (PIO_MDDR) Multi-drive Disable Position */ 2887 #define PIO_MDDR_P24_Msk (_U_(0x1) << PIO_MDDR_P24_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2888 #define PIO_MDDR_P24 PIO_MDDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P24_Msk instead */ 2889 #define PIO_MDDR_P25_Pos 25 /**< (PIO_MDDR) Multi-drive Disable Position */ 2890 #define PIO_MDDR_P25_Msk (_U_(0x1) << PIO_MDDR_P25_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2891 #define PIO_MDDR_P25 PIO_MDDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P25_Msk instead */ 2892 #define PIO_MDDR_P26_Pos 26 /**< (PIO_MDDR) Multi-drive Disable Position */ 2893 #define PIO_MDDR_P26_Msk (_U_(0x1) << PIO_MDDR_P26_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2894 #define PIO_MDDR_P26 PIO_MDDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P26_Msk instead */ 2895 #define PIO_MDDR_P27_Pos 27 /**< (PIO_MDDR) Multi-drive Disable Position */ 2896 #define PIO_MDDR_P27_Msk (_U_(0x1) << PIO_MDDR_P27_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2897 #define PIO_MDDR_P27 PIO_MDDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P27_Msk instead */ 2898 #define PIO_MDDR_P28_Pos 28 /**< (PIO_MDDR) Multi-drive Disable Position */ 2899 #define PIO_MDDR_P28_Msk (_U_(0x1) << PIO_MDDR_P28_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2900 #define PIO_MDDR_P28 PIO_MDDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P28_Msk instead */ 2901 #define PIO_MDDR_P29_Pos 29 /**< (PIO_MDDR) Multi-drive Disable Position */ 2902 #define PIO_MDDR_P29_Msk (_U_(0x1) << PIO_MDDR_P29_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2903 #define PIO_MDDR_P29 PIO_MDDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P29_Msk instead */ 2904 #define PIO_MDDR_P30_Pos 30 /**< (PIO_MDDR) Multi-drive Disable Position */ 2905 #define PIO_MDDR_P30_Msk (_U_(0x1) << PIO_MDDR_P30_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2906 #define PIO_MDDR_P30 PIO_MDDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P30_Msk instead */ 2907 #define PIO_MDDR_P31_Pos 31 /**< (PIO_MDDR) Multi-drive Disable Position */ 2908 #define PIO_MDDR_P31_Msk (_U_(0x1) << PIO_MDDR_P31_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ 2909 #define PIO_MDDR_P31 PIO_MDDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P31_Msk instead */ 2910 #define PIO_MDDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_MDDR) Register MASK (Use PIO_MDDR_Msk instead) */ 2911 #define PIO_MDDR_Msk _U_(0xFFFFFFFF) /**< (PIO_MDDR) Register Mask */ 2912 2913 #define PIO_MDDR_P_Pos 0 /**< (PIO_MDDR Position) Multi-drive Disable */ 2914 #define PIO_MDDR_P_Msk (_U_(0xFFFFFFFF) << PIO_MDDR_P_Pos) /**< (PIO_MDDR Mask) P */ 2915 #define PIO_MDDR_P(value) (PIO_MDDR_P_Msk & ((value) << PIO_MDDR_P_Pos)) 2916 2917 /* -------- PIO_MDSR : (PIO Offset: 0x58) (R/ 32) Multi-driver Status Register -------- */ 2918 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2919 #if COMPONENT_TYPEDEF_STYLE == 'N' 2920 typedef union { 2921 struct { 2922 uint32_t P0:1; /**< bit: 0 Multi-drive Status */ 2923 uint32_t P1:1; /**< bit: 1 Multi-drive Status */ 2924 uint32_t P2:1; /**< bit: 2 Multi-drive Status */ 2925 uint32_t P3:1; /**< bit: 3 Multi-drive Status */ 2926 uint32_t P4:1; /**< bit: 4 Multi-drive Status */ 2927 uint32_t P5:1; /**< bit: 5 Multi-drive Status */ 2928 uint32_t P6:1; /**< bit: 6 Multi-drive Status */ 2929 uint32_t P7:1; /**< bit: 7 Multi-drive Status */ 2930 uint32_t P8:1; /**< bit: 8 Multi-drive Status */ 2931 uint32_t P9:1; /**< bit: 9 Multi-drive Status */ 2932 uint32_t P10:1; /**< bit: 10 Multi-drive Status */ 2933 uint32_t P11:1; /**< bit: 11 Multi-drive Status */ 2934 uint32_t P12:1; /**< bit: 12 Multi-drive Status */ 2935 uint32_t P13:1; /**< bit: 13 Multi-drive Status */ 2936 uint32_t P14:1; /**< bit: 14 Multi-drive Status */ 2937 uint32_t P15:1; /**< bit: 15 Multi-drive Status */ 2938 uint32_t P16:1; /**< bit: 16 Multi-drive Status */ 2939 uint32_t P17:1; /**< bit: 17 Multi-drive Status */ 2940 uint32_t P18:1; /**< bit: 18 Multi-drive Status */ 2941 uint32_t P19:1; /**< bit: 19 Multi-drive Status */ 2942 uint32_t P20:1; /**< bit: 20 Multi-drive Status */ 2943 uint32_t P21:1; /**< bit: 21 Multi-drive Status */ 2944 uint32_t P22:1; /**< bit: 22 Multi-drive Status */ 2945 uint32_t P23:1; /**< bit: 23 Multi-drive Status */ 2946 uint32_t P24:1; /**< bit: 24 Multi-drive Status */ 2947 uint32_t P25:1; /**< bit: 25 Multi-drive Status */ 2948 uint32_t P26:1; /**< bit: 26 Multi-drive Status */ 2949 uint32_t P27:1; /**< bit: 27 Multi-drive Status */ 2950 uint32_t P28:1; /**< bit: 28 Multi-drive Status */ 2951 uint32_t P29:1; /**< bit: 29 Multi-drive Status */ 2952 uint32_t P30:1; /**< bit: 30 Multi-drive Status */ 2953 uint32_t P31:1; /**< bit: 31 Multi-drive Status */ 2954 } bit; /**< Structure used for bit access */ 2955 struct { 2956 uint32_t P:32; /**< bit: 0..31 Multi-drive Status */ 2957 } vec; /**< Structure used for vec access */ 2958 uint32_t reg; /**< Type used for register access */ 2959 } PIO_MDSR_Type; 2960 #endif 2961 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2962 2963 #define PIO_MDSR_OFFSET (0x58) /**< (PIO_MDSR) Multi-driver Status Register Offset */ 2964 2965 #define PIO_MDSR_P0_Pos 0 /**< (PIO_MDSR) Multi-drive Status Position */ 2966 #define PIO_MDSR_P0_Msk (_U_(0x1) << PIO_MDSR_P0_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 2967 #define PIO_MDSR_P0 PIO_MDSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P0_Msk instead */ 2968 #define PIO_MDSR_P1_Pos 1 /**< (PIO_MDSR) Multi-drive Status Position */ 2969 #define PIO_MDSR_P1_Msk (_U_(0x1) << PIO_MDSR_P1_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 2970 #define PIO_MDSR_P1 PIO_MDSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P1_Msk instead */ 2971 #define PIO_MDSR_P2_Pos 2 /**< (PIO_MDSR) Multi-drive Status Position */ 2972 #define PIO_MDSR_P2_Msk (_U_(0x1) << PIO_MDSR_P2_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 2973 #define PIO_MDSR_P2 PIO_MDSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P2_Msk instead */ 2974 #define PIO_MDSR_P3_Pos 3 /**< (PIO_MDSR) Multi-drive Status Position */ 2975 #define PIO_MDSR_P3_Msk (_U_(0x1) << PIO_MDSR_P3_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 2976 #define PIO_MDSR_P3 PIO_MDSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P3_Msk instead */ 2977 #define PIO_MDSR_P4_Pos 4 /**< (PIO_MDSR) Multi-drive Status Position */ 2978 #define PIO_MDSR_P4_Msk (_U_(0x1) << PIO_MDSR_P4_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 2979 #define PIO_MDSR_P4 PIO_MDSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P4_Msk instead */ 2980 #define PIO_MDSR_P5_Pos 5 /**< (PIO_MDSR) Multi-drive Status Position */ 2981 #define PIO_MDSR_P5_Msk (_U_(0x1) << PIO_MDSR_P5_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 2982 #define PIO_MDSR_P5 PIO_MDSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P5_Msk instead */ 2983 #define PIO_MDSR_P6_Pos 6 /**< (PIO_MDSR) Multi-drive Status Position */ 2984 #define PIO_MDSR_P6_Msk (_U_(0x1) << PIO_MDSR_P6_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 2985 #define PIO_MDSR_P6 PIO_MDSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P6_Msk instead */ 2986 #define PIO_MDSR_P7_Pos 7 /**< (PIO_MDSR) Multi-drive Status Position */ 2987 #define PIO_MDSR_P7_Msk (_U_(0x1) << PIO_MDSR_P7_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 2988 #define PIO_MDSR_P7 PIO_MDSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P7_Msk instead */ 2989 #define PIO_MDSR_P8_Pos 8 /**< (PIO_MDSR) Multi-drive Status Position */ 2990 #define PIO_MDSR_P8_Msk (_U_(0x1) << PIO_MDSR_P8_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 2991 #define PIO_MDSR_P8 PIO_MDSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P8_Msk instead */ 2992 #define PIO_MDSR_P9_Pos 9 /**< (PIO_MDSR) Multi-drive Status Position */ 2993 #define PIO_MDSR_P9_Msk (_U_(0x1) << PIO_MDSR_P9_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 2994 #define PIO_MDSR_P9 PIO_MDSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P9_Msk instead */ 2995 #define PIO_MDSR_P10_Pos 10 /**< (PIO_MDSR) Multi-drive Status Position */ 2996 #define PIO_MDSR_P10_Msk (_U_(0x1) << PIO_MDSR_P10_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 2997 #define PIO_MDSR_P10 PIO_MDSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P10_Msk instead */ 2998 #define PIO_MDSR_P11_Pos 11 /**< (PIO_MDSR) Multi-drive Status Position */ 2999 #define PIO_MDSR_P11_Msk (_U_(0x1) << PIO_MDSR_P11_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3000 #define PIO_MDSR_P11 PIO_MDSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P11_Msk instead */ 3001 #define PIO_MDSR_P12_Pos 12 /**< (PIO_MDSR) Multi-drive Status Position */ 3002 #define PIO_MDSR_P12_Msk (_U_(0x1) << PIO_MDSR_P12_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3003 #define PIO_MDSR_P12 PIO_MDSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P12_Msk instead */ 3004 #define PIO_MDSR_P13_Pos 13 /**< (PIO_MDSR) Multi-drive Status Position */ 3005 #define PIO_MDSR_P13_Msk (_U_(0x1) << PIO_MDSR_P13_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3006 #define PIO_MDSR_P13 PIO_MDSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P13_Msk instead */ 3007 #define PIO_MDSR_P14_Pos 14 /**< (PIO_MDSR) Multi-drive Status Position */ 3008 #define PIO_MDSR_P14_Msk (_U_(0x1) << PIO_MDSR_P14_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3009 #define PIO_MDSR_P14 PIO_MDSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P14_Msk instead */ 3010 #define PIO_MDSR_P15_Pos 15 /**< (PIO_MDSR) Multi-drive Status Position */ 3011 #define PIO_MDSR_P15_Msk (_U_(0x1) << PIO_MDSR_P15_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3012 #define PIO_MDSR_P15 PIO_MDSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P15_Msk instead */ 3013 #define PIO_MDSR_P16_Pos 16 /**< (PIO_MDSR) Multi-drive Status Position */ 3014 #define PIO_MDSR_P16_Msk (_U_(0x1) << PIO_MDSR_P16_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3015 #define PIO_MDSR_P16 PIO_MDSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P16_Msk instead */ 3016 #define PIO_MDSR_P17_Pos 17 /**< (PIO_MDSR) Multi-drive Status Position */ 3017 #define PIO_MDSR_P17_Msk (_U_(0x1) << PIO_MDSR_P17_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3018 #define PIO_MDSR_P17 PIO_MDSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P17_Msk instead */ 3019 #define PIO_MDSR_P18_Pos 18 /**< (PIO_MDSR) Multi-drive Status Position */ 3020 #define PIO_MDSR_P18_Msk (_U_(0x1) << PIO_MDSR_P18_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3021 #define PIO_MDSR_P18 PIO_MDSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P18_Msk instead */ 3022 #define PIO_MDSR_P19_Pos 19 /**< (PIO_MDSR) Multi-drive Status Position */ 3023 #define PIO_MDSR_P19_Msk (_U_(0x1) << PIO_MDSR_P19_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3024 #define PIO_MDSR_P19 PIO_MDSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P19_Msk instead */ 3025 #define PIO_MDSR_P20_Pos 20 /**< (PIO_MDSR) Multi-drive Status Position */ 3026 #define PIO_MDSR_P20_Msk (_U_(0x1) << PIO_MDSR_P20_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3027 #define PIO_MDSR_P20 PIO_MDSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P20_Msk instead */ 3028 #define PIO_MDSR_P21_Pos 21 /**< (PIO_MDSR) Multi-drive Status Position */ 3029 #define PIO_MDSR_P21_Msk (_U_(0x1) << PIO_MDSR_P21_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3030 #define PIO_MDSR_P21 PIO_MDSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P21_Msk instead */ 3031 #define PIO_MDSR_P22_Pos 22 /**< (PIO_MDSR) Multi-drive Status Position */ 3032 #define PIO_MDSR_P22_Msk (_U_(0x1) << PIO_MDSR_P22_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3033 #define PIO_MDSR_P22 PIO_MDSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P22_Msk instead */ 3034 #define PIO_MDSR_P23_Pos 23 /**< (PIO_MDSR) Multi-drive Status Position */ 3035 #define PIO_MDSR_P23_Msk (_U_(0x1) << PIO_MDSR_P23_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3036 #define PIO_MDSR_P23 PIO_MDSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P23_Msk instead */ 3037 #define PIO_MDSR_P24_Pos 24 /**< (PIO_MDSR) Multi-drive Status Position */ 3038 #define PIO_MDSR_P24_Msk (_U_(0x1) << PIO_MDSR_P24_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3039 #define PIO_MDSR_P24 PIO_MDSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P24_Msk instead */ 3040 #define PIO_MDSR_P25_Pos 25 /**< (PIO_MDSR) Multi-drive Status Position */ 3041 #define PIO_MDSR_P25_Msk (_U_(0x1) << PIO_MDSR_P25_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3042 #define PIO_MDSR_P25 PIO_MDSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P25_Msk instead */ 3043 #define PIO_MDSR_P26_Pos 26 /**< (PIO_MDSR) Multi-drive Status Position */ 3044 #define PIO_MDSR_P26_Msk (_U_(0x1) << PIO_MDSR_P26_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3045 #define PIO_MDSR_P26 PIO_MDSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P26_Msk instead */ 3046 #define PIO_MDSR_P27_Pos 27 /**< (PIO_MDSR) Multi-drive Status Position */ 3047 #define PIO_MDSR_P27_Msk (_U_(0x1) << PIO_MDSR_P27_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3048 #define PIO_MDSR_P27 PIO_MDSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P27_Msk instead */ 3049 #define PIO_MDSR_P28_Pos 28 /**< (PIO_MDSR) Multi-drive Status Position */ 3050 #define PIO_MDSR_P28_Msk (_U_(0x1) << PIO_MDSR_P28_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3051 #define PIO_MDSR_P28 PIO_MDSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P28_Msk instead */ 3052 #define PIO_MDSR_P29_Pos 29 /**< (PIO_MDSR) Multi-drive Status Position */ 3053 #define PIO_MDSR_P29_Msk (_U_(0x1) << PIO_MDSR_P29_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3054 #define PIO_MDSR_P29 PIO_MDSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P29_Msk instead */ 3055 #define PIO_MDSR_P30_Pos 30 /**< (PIO_MDSR) Multi-drive Status Position */ 3056 #define PIO_MDSR_P30_Msk (_U_(0x1) << PIO_MDSR_P30_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3057 #define PIO_MDSR_P30 PIO_MDSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P30_Msk instead */ 3058 #define PIO_MDSR_P31_Pos 31 /**< (PIO_MDSR) Multi-drive Status Position */ 3059 #define PIO_MDSR_P31_Msk (_U_(0x1) << PIO_MDSR_P31_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ 3060 #define PIO_MDSR_P31 PIO_MDSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P31_Msk instead */ 3061 #define PIO_MDSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_MDSR) Register MASK (Use PIO_MDSR_Msk instead) */ 3062 #define PIO_MDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_MDSR) Register Mask */ 3063 3064 #define PIO_MDSR_P_Pos 0 /**< (PIO_MDSR Position) Multi-drive Status */ 3065 #define PIO_MDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_MDSR_P_Pos) /**< (PIO_MDSR Mask) P */ 3066 #define PIO_MDSR_P(value) (PIO_MDSR_P_Msk & ((value) << PIO_MDSR_P_Pos)) 3067 3068 /* -------- PIO_PUDR : (PIO Offset: 0x60) (/W 32) Pull-up Disable Register -------- */ 3069 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3070 #if COMPONENT_TYPEDEF_STYLE == 'N' 3071 typedef union { 3072 struct { 3073 uint32_t P0:1; /**< bit: 0 Pull-Up Disable */ 3074 uint32_t P1:1; /**< bit: 1 Pull-Up Disable */ 3075 uint32_t P2:1; /**< bit: 2 Pull-Up Disable */ 3076 uint32_t P3:1; /**< bit: 3 Pull-Up Disable */ 3077 uint32_t P4:1; /**< bit: 4 Pull-Up Disable */ 3078 uint32_t P5:1; /**< bit: 5 Pull-Up Disable */ 3079 uint32_t P6:1; /**< bit: 6 Pull-Up Disable */ 3080 uint32_t P7:1; /**< bit: 7 Pull-Up Disable */ 3081 uint32_t P8:1; /**< bit: 8 Pull-Up Disable */ 3082 uint32_t P9:1; /**< bit: 9 Pull-Up Disable */ 3083 uint32_t P10:1; /**< bit: 10 Pull-Up Disable */ 3084 uint32_t P11:1; /**< bit: 11 Pull-Up Disable */ 3085 uint32_t P12:1; /**< bit: 12 Pull-Up Disable */ 3086 uint32_t P13:1; /**< bit: 13 Pull-Up Disable */ 3087 uint32_t P14:1; /**< bit: 14 Pull-Up Disable */ 3088 uint32_t P15:1; /**< bit: 15 Pull-Up Disable */ 3089 uint32_t P16:1; /**< bit: 16 Pull-Up Disable */ 3090 uint32_t P17:1; /**< bit: 17 Pull-Up Disable */ 3091 uint32_t P18:1; /**< bit: 18 Pull-Up Disable */ 3092 uint32_t P19:1; /**< bit: 19 Pull-Up Disable */ 3093 uint32_t P20:1; /**< bit: 20 Pull-Up Disable */ 3094 uint32_t P21:1; /**< bit: 21 Pull-Up Disable */ 3095 uint32_t P22:1; /**< bit: 22 Pull-Up Disable */ 3096 uint32_t P23:1; /**< bit: 23 Pull-Up Disable */ 3097 uint32_t P24:1; /**< bit: 24 Pull-Up Disable */ 3098 uint32_t P25:1; /**< bit: 25 Pull-Up Disable */ 3099 uint32_t P26:1; /**< bit: 26 Pull-Up Disable */ 3100 uint32_t P27:1; /**< bit: 27 Pull-Up Disable */ 3101 uint32_t P28:1; /**< bit: 28 Pull-Up Disable */ 3102 uint32_t P29:1; /**< bit: 29 Pull-Up Disable */ 3103 uint32_t P30:1; /**< bit: 30 Pull-Up Disable */ 3104 uint32_t P31:1; /**< bit: 31 Pull-Up Disable */ 3105 } bit; /**< Structure used for bit access */ 3106 struct { 3107 uint32_t P:32; /**< bit: 0..31 Pull-Up Disable */ 3108 } vec; /**< Structure used for vec access */ 3109 uint32_t reg; /**< Type used for register access */ 3110 } PIO_PUDR_Type; 3111 #endif 3112 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3113 3114 #define PIO_PUDR_OFFSET (0x60) /**< (PIO_PUDR) Pull-up Disable Register Offset */ 3115 3116 #define PIO_PUDR_P0_Pos 0 /**< (PIO_PUDR) Pull-Up Disable Position */ 3117 #define PIO_PUDR_P0_Msk (_U_(0x1) << PIO_PUDR_P0_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3118 #define PIO_PUDR_P0 PIO_PUDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P0_Msk instead */ 3119 #define PIO_PUDR_P1_Pos 1 /**< (PIO_PUDR) Pull-Up Disable Position */ 3120 #define PIO_PUDR_P1_Msk (_U_(0x1) << PIO_PUDR_P1_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3121 #define PIO_PUDR_P1 PIO_PUDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P1_Msk instead */ 3122 #define PIO_PUDR_P2_Pos 2 /**< (PIO_PUDR) Pull-Up Disable Position */ 3123 #define PIO_PUDR_P2_Msk (_U_(0x1) << PIO_PUDR_P2_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3124 #define PIO_PUDR_P2 PIO_PUDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P2_Msk instead */ 3125 #define PIO_PUDR_P3_Pos 3 /**< (PIO_PUDR) Pull-Up Disable Position */ 3126 #define PIO_PUDR_P3_Msk (_U_(0x1) << PIO_PUDR_P3_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3127 #define PIO_PUDR_P3 PIO_PUDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P3_Msk instead */ 3128 #define PIO_PUDR_P4_Pos 4 /**< (PIO_PUDR) Pull-Up Disable Position */ 3129 #define PIO_PUDR_P4_Msk (_U_(0x1) << PIO_PUDR_P4_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3130 #define PIO_PUDR_P4 PIO_PUDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P4_Msk instead */ 3131 #define PIO_PUDR_P5_Pos 5 /**< (PIO_PUDR) Pull-Up Disable Position */ 3132 #define PIO_PUDR_P5_Msk (_U_(0x1) << PIO_PUDR_P5_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3133 #define PIO_PUDR_P5 PIO_PUDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P5_Msk instead */ 3134 #define PIO_PUDR_P6_Pos 6 /**< (PIO_PUDR) Pull-Up Disable Position */ 3135 #define PIO_PUDR_P6_Msk (_U_(0x1) << PIO_PUDR_P6_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3136 #define PIO_PUDR_P6 PIO_PUDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P6_Msk instead */ 3137 #define PIO_PUDR_P7_Pos 7 /**< (PIO_PUDR) Pull-Up Disable Position */ 3138 #define PIO_PUDR_P7_Msk (_U_(0x1) << PIO_PUDR_P7_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3139 #define PIO_PUDR_P7 PIO_PUDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P7_Msk instead */ 3140 #define PIO_PUDR_P8_Pos 8 /**< (PIO_PUDR) Pull-Up Disable Position */ 3141 #define PIO_PUDR_P8_Msk (_U_(0x1) << PIO_PUDR_P8_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3142 #define PIO_PUDR_P8 PIO_PUDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P8_Msk instead */ 3143 #define PIO_PUDR_P9_Pos 9 /**< (PIO_PUDR) Pull-Up Disable Position */ 3144 #define PIO_PUDR_P9_Msk (_U_(0x1) << PIO_PUDR_P9_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3145 #define PIO_PUDR_P9 PIO_PUDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P9_Msk instead */ 3146 #define PIO_PUDR_P10_Pos 10 /**< (PIO_PUDR) Pull-Up Disable Position */ 3147 #define PIO_PUDR_P10_Msk (_U_(0x1) << PIO_PUDR_P10_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3148 #define PIO_PUDR_P10 PIO_PUDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P10_Msk instead */ 3149 #define PIO_PUDR_P11_Pos 11 /**< (PIO_PUDR) Pull-Up Disable Position */ 3150 #define PIO_PUDR_P11_Msk (_U_(0x1) << PIO_PUDR_P11_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3151 #define PIO_PUDR_P11 PIO_PUDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P11_Msk instead */ 3152 #define PIO_PUDR_P12_Pos 12 /**< (PIO_PUDR) Pull-Up Disable Position */ 3153 #define PIO_PUDR_P12_Msk (_U_(0x1) << PIO_PUDR_P12_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3154 #define PIO_PUDR_P12 PIO_PUDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P12_Msk instead */ 3155 #define PIO_PUDR_P13_Pos 13 /**< (PIO_PUDR) Pull-Up Disable Position */ 3156 #define PIO_PUDR_P13_Msk (_U_(0x1) << PIO_PUDR_P13_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3157 #define PIO_PUDR_P13 PIO_PUDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P13_Msk instead */ 3158 #define PIO_PUDR_P14_Pos 14 /**< (PIO_PUDR) Pull-Up Disable Position */ 3159 #define PIO_PUDR_P14_Msk (_U_(0x1) << PIO_PUDR_P14_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3160 #define PIO_PUDR_P14 PIO_PUDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P14_Msk instead */ 3161 #define PIO_PUDR_P15_Pos 15 /**< (PIO_PUDR) Pull-Up Disable Position */ 3162 #define PIO_PUDR_P15_Msk (_U_(0x1) << PIO_PUDR_P15_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3163 #define PIO_PUDR_P15 PIO_PUDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P15_Msk instead */ 3164 #define PIO_PUDR_P16_Pos 16 /**< (PIO_PUDR) Pull-Up Disable Position */ 3165 #define PIO_PUDR_P16_Msk (_U_(0x1) << PIO_PUDR_P16_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3166 #define PIO_PUDR_P16 PIO_PUDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P16_Msk instead */ 3167 #define PIO_PUDR_P17_Pos 17 /**< (PIO_PUDR) Pull-Up Disable Position */ 3168 #define PIO_PUDR_P17_Msk (_U_(0x1) << PIO_PUDR_P17_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3169 #define PIO_PUDR_P17 PIO_PUDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P17_Msk instead */ 3170 #define PIO_PUDR_P18_Pos 18 /**< (PIO_PUDR) Pull-Up Disable Position */ 3171 #define PIO_PUDR_P18_Msk (_U_(0x1) << PIO_PUDR_P18_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3172 #define PIO_PUDR_P18 PIO_PUDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P18_Msk instead */ 3173 #define PIO_PUDR_P19_Pos 19 /**< (PIO_PUDR) Pull-Up Disable Position */ 3174 #define PIO_PUDR_P19_Msk (_U_(0x1) << PIO_PUDR_P19_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3175 #define PIO_PUDR_P19 PIO_PUDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P19_Msk instead */ 3176 #define PIO_PUDR_P20_Pos 20 /**< (PIO_PUDR) Pull-Up Disable Position */ 3177 #define PIO_PUDR_P20_Msk (_U_(0x1) << PIO_PUDR_P20_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3178 #define PIO_PUDR_P20 PIO_PUDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P20_Msk instead */ 3179 #define PIO_PUDR_P21_Pos 21 /**< (PIO_PUDR) Pull-Up Disable Position */ 3180 #define PIO_PUDR_P21_Msk (_U_(0x1) << PIO_PUDR_P21_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3181 #define PIO_PUDR_P21 PIO_PUDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P21_Msk instead */ 3182 #define PIO_PUDR_P22_Pos 22 /**< (PIO_PUDR) Pull-Up Disable Position */ 3183 #define PIO_PUDR_P22_Msk (_U_(0x1) << PIO_PUDR_P22_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3184 #define PIO_PUDR_P22 PIO_PUDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P22_Msk instead */ 3185 #define PIO_PUDR_P23_Pos 23 /**< (PIO_PUDR) Pull-Up Disable Position */ 3186 #define PIO_PUDR_P23_Msk (_U_(0x1) << PIO_PUDR_P23_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3187 #define PIO_PUDR_P23 PIO_PUDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P23_Msk instead */ 3188 #define PIO_PUDR_P24_Pos 24 /**< (PIO_PUDR) Pull-Up Disable Position */ 3189 #define PIO_PUDR_P24_Msk (_U_(0x1) << PIO_PUDR_P24_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3190 #define PIO_PUDR_P24 PIO_PUDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P24_Msk instead */ 3191 #define PIO_PUDR_P25_Pos 25 /**< (PIO_PUDR) Pull-Up Disable Position */ 3192 #define PIO_PUDR_P25_Msk (_U_(0x1) << PIO_PUDR_P25_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3193 #define PIO_PUDR_P25 PIO_PUDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P25_Msk instead */ 3194 #define PIO_PUDR_P26_Pos 26 /**< (PIO_PUDR) Pull-Up Disable Position */ 3195 #define PIO_PUDR_P26_Msk (_U_(0x1) << PIO_PUDR_P26_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3196 #define PIO_PUDR_P26 PIO_PUDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P26_Msk instead */ 3197 #define PIO_PUDR_P27_Pos 27 /**< (PIO_PUDR) Pull-Up Disable Position */ 3198 #define PIO_PUDR_P27_Msk (_U_(0x1) << PIO_PUDR_P27_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3199 #define PIO_PUDR_P27 PIO_PUDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P27_Msk instead */ 3200 #define PIO_PUDR_P28_Pos 28 /**< (PIO_PUDR) Pull-Up Disable Position */ 3201 #define PIO_PUDR_P28_Msk (_U_(0x1) << PIO_PUDR_P28_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3202 #define PIO_PUDR_P28 PIO_PUDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P28_Msk instead */ 3203 #define PIO_PUDR_P29_Pos 29 /**< (PIO_PUDR) Pull-Up Disable Position */ 3204 #define PIO_PUDR_P29_Msk (_U_(0x1) << PIO_PUDR_P29_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3205 #define PIO_PUDR_P29 PIO_PUDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P29_Msk instead */ 3206 #define PIO_PUDR_P30_Pos 30 /**< (PIO_PUDR) Pull-Up Disable Position */ 3207 #define PIO_PUDR_P30_Msk (_U_(0x1) << PIO_PUDR_P30_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3208 #define PIO_PUDR_P30 PIO_PUDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P30_Msk instead */ 3209 #define PIO_PUDR_P31_Pos 31 /**< (PIO_PUDR) Pull-Up Disable Position */ 3210 #define PIO_PUDR_P31_Msk (_U_(0x1) << PIO_PUDR_P31_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ 3211 #define PIO_PUDR_P31 PIO_PUDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P31_Msk instead */ 3212 #define PIO_PUDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PUDR) Register MASK (Use PIO_PUDR_Msk instead) */ 3213 #define PIO_PUDR_Msk _U_(0xFFFFFFFF) /**< (PIO_PUDR) Register Mask */ 3214 3215 #define PIO_PUDR_P_Pos 0 /**< (PIO_PUDR Position) Pull-Up Disable */ 3216 #define PIO_PUDR_P_Msk (_U_(0xFFFFFFFF) << PIO_PUDR_P_Pos) /**< (PIO_PUDR Mask) P */ 3217 #define PIO_PUDR_P(value) (PIO_PUDR_P_Msk & ((value) << PIO_PUDR_P_Pos)) 3218 3219 /* -------- PIO_PUER : (PIO Offset: 0x64) (/W 32) Pull-up Enable Register -------- */ 3220 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3221 #if COMPONENT_TYPEDEF_STYLE == 'N' 3222 typedef union { 3223 struct { 3224 uint32_t P0:1; /**< bit: 0 Pull-Up Enable */ 3225 uint32_t P1:1; /**< bit: 1 Pull-Up Enable */ 3226 uint32_t P2:1; /**< bit: 2 Pull-Up Enable */ 3227 uint32_t P3:1; /**< bit: 3 Pull-Up Enable */ 3228 uint32_t P4:1; /**< bit: 4 Pull-Up Enable */ 3229 uint32_t P5:1; /**< bit: 5 Pull-Up Enable */ 3230 uint32_t P6:1; /**< bit: 6 Pull-Up Enable */ 3231 uint32_t P7:1; /**< bit: 7 Pull-Up Enable */ 3232 uint32_t P8:1; /**< bit: 8 Pull-Up Enable */ 3233 uint32_t P9:1; /**< bit: 9 Pull-Up Enable */ 3234 uint32_t P10:1; /**< bit: 10 Pull-Up Enable */ 3235 uint32_t P11:1; /**< bit: 11 Pull-Up Enable */ 3236 uint32_t P12:1; /**< bit: 12 Pull-Up Enable */ 3237 uint32_t P13:1; /**< bit: 13 Pull-Up Enable */ 3238 uint32_t P14:1; /**< bit: 14 Pull-Up Enable */ 3239 uint32_t P15:1; /**< bit: 15 Pull-Up Enable */ 3240 uint32_t P16:1; /**< bit: 16 Pull-Up Enable */ 3241 uint32_t P17:1; /**< bit: 17 Pull-Up Enable */ 3242 uint32_t P18:1; /**< bit: 18 Pull-Up Enable */ 3243 uint32_t P19:1; /**< bit: 19 Pull-Up Enable */ 3244 uint32_t P20:1; /**< bit: 20 Pull-Up Enable */ 3245 uint32_t P21:1; /**< bit: 21 Pull-Up Enable */ 3246 uint32_t P22:1; /**< bit: 22 Pull-Up Enable */ 3247 uint32_t P23:1; /**< bit: 23 Pull-Up Enable */ 3248 uint32_t P24:1; /**< bit: 24 Pull-Up Enable */ 3249 uint32_t P25:1; /**< bit: 25 Pull-Up Enable */ 3250 uint32_t P26:1; /**< bit: 26 Pull-Up Enable */ 3251 uint32_t P27:1; /**< bit: 27 Pull-Up Enable */ 3252 uint32_t P28:1; /**< bit: 28 Pull-Up Enable */ 3253 uint32_t P29:1; /**< bit: 29 Pull-Up Enable */ 3254 uint32_t P30:1; /**< bit: 30 Pull-Up Enable */ 3255 uint32_t P31:1; /**< bit: 31 Pull-Up Enable */ 3256 } bit; /**< Structure used for bit access */ 3257 struct { 3258 uint32_t P:32; /**< bit: 0..31 Pull-Up Enable */ 3259 } vec; /**< Structure used for vec access */ 3260 uint32_t reg; /**< Type used for register access */ 3261 } PIO_PUER_Type; 3262 #endif 3263 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3264 3265 #define PIO_PUER_OFFSET (0x64) /**< (PIO_PUER) Pull-up Enable Register Offset */ 3266 3267 #define PIO_PUER_P0_Pos 0 /**< (PIO_PUER) Pull-Up Enable Position */ 3268 #define PIO_PUER_P0_Msk (_U_(0x1) << PIO_PUER_P0_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3269 #define PIO_PUER_P0 PIO_PUER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P0_Msk instead */ 3270 #define PIO_PUER_P1_Pos 1 /**< (PIO_PUER) Pull-Up Enable Position */ 3271 #define PIO_PUER_P1_Msk (_U_(0x1) << PIO_PUER_P1_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3272 #define PIO_PUER_P1 PIO_PUER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P1_Msk instead */ 3273 #define PIO_PUER_P2_Pos 2 /**< (PIO_PUER) Pull-Up Enable Position */ 3274 #define PIO_PUER_P2_Msk (_U_(0x1) << PIO_PUER_P2_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3275 #define PIO_PUER_P2 PIO_PUER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P2_Msk instead */ 3276 #define PIO_PUER_P3_Pos 3 /**< (PIO_PUER) Pull-Up Enable Position */ 3277 #define PIO_PUER_P3_Msk (_U_(0x1) << PIO_PUER_P3_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3278 #define PIO_PUER_P3 PIO_PUER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P3_Msk instead */ 3279 #define PIO_PUER_P4_Pos 4 /**< (PIO_PUER) Pull-Up Enable Position */ 3280 #define PIO_PUER_P4_Msk (_U_(0x1) << PIO_PUER_P4_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3281 #define PIO_PUER_P4 PIO_PUER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P4_Msk instead */ 3282 #define PIO_PUER_P5_Pos 5 /**< (PIO_PUER) Pull-Up Enable Position */ 3283 #define PIO_PUER_P5_Msk (_U_(0x1) << PIO_PUER_P5_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3284 #define PIO_PUER_P5 PIO_PUER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P5_Msk instead */ 3285 #define PIO_PUER_P6_Pos 6 /**< (PIO_PUER) Pull-Up Enable Position */ 3286 #define PIO_PUER_P6_Msk (_U_(0x1) << PIO_PUER_P6_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3287 #define PIO_PUER_P6 PIO_PUER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P6_Msk instead */ 3288 #define PIO_PUER_P7_Pos 7 /**< (PIO_PUER) Pull-Up Enable Position */ 3289 #define PIO_PUER_P7_Msk (_U_(0x1) << PIO_PUER_P7_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3290 #define PIO_PUER_P7 PIO_PUER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P7_Msk instead */ 3291 #define PIO_PUER_P8_Pos 8 /**< (PIO_PUER) Pull-Up Enable Position */ 3292 #define PIO_PUER_P8_Msk (_U_(0x1) << PIO_PUER_P8_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3293 #define PIO_PUER_P8 PIO_PUER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P8_Msk instead */ 3294 #define PIO_PUER_P9_Pos 9 /**< (PIO_PUER) Pull-Up Enable Position */ 3295 #define PIO_PUER_P9_Msk (_U_(0x1) << PIO_PUER_P9_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3296 #define PIO_PUER_P9 PIO_PUER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P9_Msk instead */ 3297 #define PIO_PUER_P10_Pos 10 /**< (PIO_PUER) Pull-Up Enable Position */ 3298 #define PIO_PUER_P10_Msk (_U_(0x1) << PIO_PUER_P10_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3299 #define PIO_PUER_P10 PIO_PUER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P10_Msk instead */ 3300 #define PIO_PUER_P11_Pos 11 /**< (PIO_PUER) Pull-Up Enable Position */ 3301 #define PIO_PUER_P11_Msk (_U_(0x1) << PIO_PUER_P11_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3302 #define PIO_PUER_P11 PIO_PUER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P11_Msk instead */ 3303 #define PIO_PUER_P12_Pos 12 /**< (PIO_PUER) Pull-Up Enable Position */ 3304 #define PIO_PUER_P12_Msk (_U_(0x1) << PIO_PUER_P12_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3305 #define PIO_PUER_P12 PIO_PUER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P12_Msk instead */ 3306 #define PIO_PUER_P13_Pos 13 /**< (PIO_PUER) Pull-Up Enable Position */ 3307 #define PIO_PUER_P13_Msk (_U_(0x1) << PIO_PUER_P13_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3308 #define PIO_PUER_P13 PIO_PUER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P13_Msk instead */ 3309 #define PIO_PUER_P14_Pos 14 /**< (PIO_PUER) Pull-Up Enable Position */ 3310 #define PIO_PUER_P14_Msk (_U_(0x1) << PIO_PUER_P14_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3311 #define PIO_PUER_P14 PIO_PUER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P14_Msk instead */ 3312 #define PIO_PUER_P15_Pos 15 /**< (PIO_PUER) Pull-Up Enable Position */ 3313 #define PIO_PUER_P15_Msk (_U_(0x1) << PIO_PUER_P15_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3314 #define PIO_PUER_P15 PIO_PUER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P15_Msk instead */ 3315 #define PIO_PUER_P16_Pos 16 /**< (PIO_PUER) Pull-Up Enable Position */ 3316 #define PIO_PUER_P16_Msk (_U_(0x1) << PIO_PUER_P16_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3317 #define PIO_PUER_P16 PIO_PUER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P16_Msk instead */ 3318 #define PIO_PUER_P17_Pos 17 /**< (PIO_PUER) Pull-Up Enable Position */ 3319 #define PIO_PUER_P17_Msk (_U_(0x1) << PIO_PUER_P17_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3320 #define PIO_PUER_P17 PIO_PUER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P17_Msk instead */ 3321 #define PIO_PUER_P18_Pos 18 /**< (PIO_PUER) Pull-Up Enable Position */ 3322 #define PIO_PUER_P18_Msk (_U_(0x1) << PIO_PUER_P18_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3323 #define PIO_PUER_P18 PIO_PUER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P18_Msk instead */ 3324 #define PIO_PUER_P19_Pos 19 /**< (PIO_PUER) Pull-Up Enable Position */ 3325 #define PIO_PUER_P19_Msk (_U_(0x1) << PIO_PUER_P19_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3326 #define PIO_PUER_P19 PIO_PUER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P19_Msk instead */ 3327 #define PIO_PUER_P20_Pos 20 /**< (PIO_PUER) Pull-Up Enable Position */ 3328 #define PIO_PUER_P20_Msk (_U_(0x1) << PIO_PUER_P20_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3329 #define PIO_PUER_P20 PIO_PUER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P20_Msk instead */ 3330 #define PIO_PUER_P21_Pos 21 /**< (PIO_PUER) Pull-Up Enable Position */ 3331 #define PIO_PUER_P21_Msk (_U_(0x1) << PIO_PUER_P21_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3332 #define PIO_PUER_P21 PIO_PUER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P21_Msk instead */ 3333 #define PIO_PUER_P22_Pos 22 /**< (PIO_PUER) Pull-Up Enable Position */ 3334 #define PIO_PUER_P22_Msk (_U_(0x1) << PIO_PUER_P22_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3335 #define PIO_PUER_P22 PIO_PUER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P22_Msk instead */ 3336 #define PIO_PUER_P23_Pos 23 /**< (PIO_PUER) Pull-Up Enable Position */ 3337 #define PIO_PUER_P23_Msk (_U_(0x1) << PIO_PUER_P23_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3338 #define PIO_PUER_P23 PIO_PUER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P23_Msk instead */ 3339 #define PIO_PUER_P24_Pos 24 /**< (PIO_PUER) Pull-Up Enable Position */ 3340 #define PIO_PUER_P24_Msk (_U_(0x1) << PIO_PUER_P24_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3341 #define PIO_PUER_P24 PIO_PUER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P24_Msk instead */ 3342 #define PIO_PUER_P25_Pos 25 /**< (PIO_PUER) Pull-Up Enable Position */ 3343 #define PIO_PUER_P25_Msk (_U_(0x1) << PIO_PUER_P25_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3344 #define PIO_PUER_P25 PIO_PUER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P25_Msk instead */ 3345 #define PIO_PUER_P26_Pos 26 /**< (PIO_PUER) Pull-Up Enable Position */ 3346 #define PIO_PUER_P26_Msk (_U_(0x1) << PIO_PUER_P26_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3347 #define PIO_PUER_P26 PIO_PUER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P26_Msk instead */ 3348 #define PIO_PUER_P27_Pos 27 /**< (PIO_PUER) Pull-Up Enable Position */ 3349 #define PIO_PUER_P27_Msk (_U_(0x1) << PIO_PUER_P27_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3350 #define PIO_PUER_P27 PIO_PUER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P27_Msk instead */ 3351 #define PIO_PUER_P28_Pos 28 /**< (PIO_PUER) Pull-Up Enable Position */ 3352 #define PIO_PUER_P28_Msk (_U_(0x1) << PIO_PUER_P28_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3353 #define PIO_PUER_P28 PIO_PUER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P28_Msk instead */ 3354 #define PIO_PUER_P29_Pos 29 /**< (PIO_PUER) Pull-Up Enable Position */ 3355 #define PIO_PUER_P29_Msk (_U_(0x1) << PIO_PUER_P29_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3356 #define PIO_PUER_P29 PIO_PUER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P29_Msk instead */ 3357 #define PIO_PUER_P30_Pos 30 /**< (PIO_PUER) Pull-Up Enable Position */ 3358 #define PIO_PUER_P30_Msk (_U_(0x1) << PIO_PUER_P30_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3359 #define PIO_PUER_P30 PIO_PUER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P30_Msk instead */ 3360 #define PIO_PUER_P31_Pos 31 /**< (PIO_PUER) Pull-Up Enable Position */ 3361 #define PIO_PUER_P31_Msk (_U_(0x1) << PIO_PUER_P31_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ 3362 #define PIO_PUER_P31 PIO_PUER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P31_Msk instead */ 3363 #define PIO_PUER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PUER) Register MASK (Use PIO_PUER_Msk instead) */ 3364 #define PIO_PUER_Msk _U_(0xFFFFFFFF) /**< (PIO_PUER) Register Mask */ 3365 3366 #define PIO_PUER_P_Pos 0 /**< (PIO_PUER Position) Pull-Up Enable */ 3367 #define PIO_PUER_P_Msk (_U_(0xFFFFFFFF) << PIO_PUER_P_Pos) /**< (PIO_PUER Mask) P */ 3368 #define PIO_PUER_P(value) (PIO_PUER_P_Msk & ((value) << PIO_PUER_P_Pos)) 3369 3370 /* -------- PIO_PUSR : (PIO Offset: 0x68) (R/ 32) Pad Pull-up Status Register -------- */ 3371 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3372 #if COMPONENT_TYPEDEF_STYLE == 'N' 3373 typedef union { 3374 struct { 3375 uint32_t P0:1; /**< bit: 0 Pull-Up Status */ 3376 uint32_t P1:1; /**< bit: 1 Pull-Up Status */ 3377 uint32_t P2:1; /**< bit: 2 Pull-Up Status */ 3378 uint32_t P3:1; /**< bit: 3 Pull-Up Status */ 3379 uint32_t P4:1; /**< bit: 4 Pull-Up Status */ 3380 uint32_t P5:1; /**< bit: 5 Pull-Up Status */ 3381 uint32_t P6:1; /**< bit: 6 Pull-Up Status */ 3382 uint32_t P7:1; /**< bit: 7 Pull-Up Status */ 3383 uint32_t P8:1; /**< bit: 8 Pull-Up Status */ 3384 uint32_t P9:1; /**< bit: 9 Pull-Up Status */ 3385 uint32_t P10:1; /**< bit: 10 Pull-Up Status */ 3386 uint32_t P11:1; /**< bit: 11 Pull-Up Status */ 3387 uint32_t P12:1; /**< bit: 12 Pull-Up Status */ 3388 uint32_t P13:1; /**< bit: 13 Pull-Up Status */ 3389 uint32_t P14:1; /**< bit: 14 Pull-Up Status */ 3390 uint32_t P15:1; /**< bit: 15 Pull-Up Status */ 3391 uint32_t P16:1; /**< bit: 16 Pull-Up Status */ 3392 uint32_t P17:1; /**< bit: 17 Pull-Up Status */ 3393 uint32_t P18:1; /**< bit: 18 Pull-Up Status */ 3394 uint32_t P19:1; /**< bit: 19 Pull-Up Status */ 3395 uint32_t P20:1; /**< bit: 20 Pull-Up Status */ 3396 uint32_t P21:1; /**< bit: 21 Pull-Up Status */ 3397 uint32_t P22:1; /**< bit: 22 Pull-Up Status */ 3398 uint32_t P23:1; /**< bit: 23 Pull-Up Status */ 3399 uint32_t P24:1; /**< bit: 24 Pull-Up Status */ 3400 uint32_t P25:1; /**< bit: 25 Pull-Up Status */ 3401 uint32_t P26:1; /**< bit: 26 Pull-Up Status */ 3402 uint32_t P27:1; /**< bit: 27 Pull-Up Status */ 3403 uint32_t P28:1; /**< bit: 28 Pull-Up Status */ 3404 uint32_t P29:1; /**< bit: 29 Pull-Up Status */ 3405 uint32_t P30:1; /**< bit: 30 Pull-Up Status */ 3406 uint32_t P31:1; /**< bit: 31 Pull-Up Status */ 3407 } bit; /**< Structure used for bit access */ 3408 struct { 3409 uint32_t P:32; /**< bit: 0..31 Pull-Up Status */ 3410 } vec; /**< Structure used for vec access */ 3411 uint32_t reg; /**< Type used for register access */ 3412 } PIO_PUSR_Type; 3413 #endif 3414 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3415 3416 #define PIO_PUSR_OFFSET (0x68) /**< (PIO_PUSR) Pad Pull-up Status Register Offset */ 3417 3418 #define PIO_PUSR_P0_Pos 0 /**< (PIO_PUSR) Pull-Up Status Position */ 3419 #define PIO_PUSR_P0_Msk (_U_(0x1) << PIO_PUSR_P0_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3420 #define PIO_PUSR_P0 PIO_PUSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P0_Msk instead */ 3421 #define PIO_PUSR_P1_Pos 1 /**< (PIO_PUSR) Pull-Up Status Position */ 3422 #define PIO_PUSR_P1_Msk (_U_(0x1) << PIO_PUSR_P1_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3423 #define PIO_PUSR_P1 PIO_PUSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P1_Msk instead */ 3424 #define PIO_PUSR_P2_Pos 2 /**< (PIO_PUSR) Pull-Up Status Position */ 3425 #define PIO_PUSR_P2_Msk (_U_(0x1) << PIO_PUSR_P2_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3426 #define PIO_PUSR_P2 PIO_PUSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P2_Msk instead */ 3427 #define PIO_PUSR_P3_Pos 3 /**< (PIO_PUSR) Pull-Up Status Position */ 3428 #define PIO_PUSR_P3_Msk (_U_(0x1) << PIO_PUSR_P3_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3429 #define PIO_PUSR_P3 PIO_PUSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P3_Msk instead */ 3430 #define PIO_PUSR_P4_Pos 4 /**< (PIO_PUSR) Pull-Up Status Position */ 3431 #define PIO_PUSR_P4_Msk (_U_(0x1) << PIO_PUSR_P4_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3432 #define PIO_PUSR_P4 PIO_PUSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P4_Msk instead */ 3433 #define PIO_PUSR_P5_Pos 5 /**< (PIO_PUSR) Pull-Up Status Position */ 3434 #define PIO_PUSR_P5_Msk (_U_(0x1) << PIO_PUSR_P5_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3435 #define PIO_PUSR_P5 PIO_PUSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P5_Msk instead */ 3436 #define PIO_PUSR_P6_Pos 6 /**< (PIO_PUSR) Pull-Up Status Position */ 3437 #define PIO_PUSR_P6_Msk (_U_(0x1) << PIO_PUSR_P6_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3438 #define PIO_PUSR_P6 PIO_PUSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P6_Msk instead */ 3439 #define PIO_PUSR_P7_Pos 7 /**< (PIO_PUSR) Pull-Up Status Position */ 3440 #define PIO_PUSR_P7_Msk (_U_(0x1) << PIO_PUSR_P7_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3441 #define PIO_PUSR_P7 PIO_PUSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P7_Msk instead */ 3442 #define PIO_PUSR_P8_Pos 8 /**< (PIO_PUSR) Pull-Up Status Position */ 3443 #define PIO_PUSR_P8_Msk (_U_(0x1) << PIO_PUSR_P8_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3444 #define PIO_PUSR_P8 PIO_PUSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P8_Msk instead */ 3445 #define PIO_PUSR_P9_Pos 9 /**< (PIO_PUSR) Pull-Up Status Position */ 3446 #define PIO_PUSR_P9_Msk (_U_(0x1) << PIO_PUSR_P9_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3447 #define PIO_PUSR_P9 PIO_PUSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P9_Msk instead */ 3448 #define PIO_PUSR_P10_Pos 10 /**< (PIO_PUSR) Pull-Up Status Position */ 3449 #define PIO_PUSR_P10_Msk (_U_(0x1) << PIO_PUSR_P10_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3450 #define PIO_PUSR_P10 PIO_PUSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P10_Msk instead */ 3451 #define PIO_PUSR_P11_Pos 11 /**< (PIO_PUSR) Pull-Up Status Position */ 3452 #define PIO_PUSR_P11_Msk (_U_(0x1) << PIO_PUSR_P11_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3453 #define PIO_PUSR_P11 PIO_PUSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P11_Msk instead */ 3454 #define PIO_PUSR_P12_Pos 12 /**< (PIO_PUSR) Pull-Up Status Position */ 3455 #define PIO_PUSR_P12_Msk (_U_(0x1) << PIO_PUSR_P12_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3456 #define PIO_PUSR_P12 PIO_PUSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P12_Msk instead */ 3457 #define PIO_PUSR_P13_Pos 13 /**< (PIO_PUSR) Pull-Up Status Position */ 3458 #define PIO_PUSR_P13_Msk (_U_(0x1) << PIO_PUSR_P13_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3459 #define PIO_PUSR_P13 PIO_PUSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P13_Msk instead */ 3460 #define PIO_PUSR_P14_Pos 14 /**< (PIO_PUSR) Pull-Up Status Position */ 3461 #define PIO_PUSR_P14_Msk (_U_(0x1) << PIO_PUSR_P14_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3462 #define PIO_PUSR_P14 PIO_PUSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P14_Msk instead */ 3463 #define PIO_PUSR_P15_Pos 15 /**< (PIO_PUSR) Pull-Up Status Position */ 3464 #define PIO_PUSR_P15_Msk (_U_(0x1) << PIO_PUSR_P15_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3465 #define PIO_PUSR_P15 PIO_PUSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P15_Msk instead */ 3466 #define PIO_PUSR_P16_Pos 16 /**< (PIO_PUSR) Pull-Up Status Position */ 3467 #define PIO_PUSR_P16_Msk (_U_(0x1) << PIO_PUSR_P16_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3468 #define PIO_PUSR_P16 PIO_PUSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P16_Msk instead */ 3469 #define PIO_PUSR_P17_Pos 17 /**< (PIO_PUSR) Pull-Up Status Position */ 3470 #define PIO_PUSR_P17_Msk (_U_(0x1) << PIO_PUSR_P17_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3471 #define PIO_PUSR_P17 PIO_PUSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P17_Msk instead */ 3472 #define PIO_PUSR_P18_Pos 18 /**< (PIO_PUSR) Pull-Up Status Position */ 3473 #define PIO_PUSR_P18_Msk (_U_(0x1) << PIO_PUSR_P18_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3474 #define PIO_PUSR_P18 PIO_PUSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P18_Msk instead */ 3475 #define PIO_PUSR_P19_Pos 19 /**< (PIO_PUSR) Pull-Up Status Position */ 3476 #define PIO_PUSR_P19_Msk (_U_(0x1) << PIO_PUSR_P19_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3477 #define PIO_PUSR_P19 PIO_PUSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P19_Msk instead */ 3478 #define PIO_PUSR_P20_Pos 20 /**< (PIO_PUSR) Pull-Up Status Position */ 3479 #define PIO_PUSR_P20_Msk (_U_(0x1) << PIO_PUSR_P20_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3480 #define PIO_PUSR_P20 PIO_PUSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P20_Msk instead */ 3481 #define PIO_PUSR_P21_Pos 21 /**< (PIO_PUSR) Pull-Up Status Position */ 3482 #define PIO_PUSR_P21_Msk (_U_(0x1) << PIO_PUSR_P21_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3483 #define PIO_PUSR_P21 PIO_PUSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P21_Msk instead */ 3484 #define PIO_PUSR_P22_Pos 22 /**< (PIO_PUSR) Pull-Up Status Position */ 3485 #define PIO_PUSR_P22_Msk (_U_(0x1) << PIO_PUSR_P22_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3486 #define PIO_PUSR_P22 PIO_PUSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P22_Msk instead */ 3487 #define PIO_PUSR_P23_Pos 23 /**< (PIO_PUSR) Pull-Up Status Position */ 3488 #define PIO_PUSR_P23_Msk (_U_(0x1) << PIO_PUSR_P23_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3489 #define PIO_PUSR_P23 PIO_PUSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P23_Msk instead */ 3490 #define PIO_PUSR_P24_Pos 24 /**< (PIO_PUSR) Pull-Up Status Position */ 3491 #define PIO_PUSR_P24_Msk (_U_(0x1) << PIO_PUSR_P24_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3492 #define PIO_PUSR_P24 PIO_PUSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P24_Msk instead */ 3493 #define PIO_PUSR_P25_Pos 25 /**< (PIO_PUSR) Pull-Up Status Position */ 3494 #define PIO_PUSR_P25_Msk (_U_(0x1) << PIO_PUSR_P25_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3495 #define PIO_PUSR_P25 PIO_PUSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P25_Msk instead */ 3496 #define PIO_PUSR_P26_Pos 26 /**< (PIO_PUSR) Pull-Up Status Position */ 3497 #define PIO_PUSR_P26_Msk (_U_(0x1) << PIO_PUSR_P26_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3498 #define PIO_PUSR_P26 PIO_PUSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P26_Msk instead */ 3499 #define PIO_PUSR_P27_Pos 27 /**< (PIO_PUSR) Pull-Up Status Position */ 3500 #define PIO_PUSR_P27_Msk (_U_(0x1) << PIO_PUSR_P27_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3501 #define PIO_PUSR_P27 PIO_PUSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P27_Msk instead */ 3502 #define PIO_PUSR_P28_Pos 28 /**< (PIO_PUSR) Pull-Up Status Position */ 3503 #define PIO_PUSR_P28_Msk (_U_(0x1) << PIO_PUSR_P28_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3504 #define PIO_PUSR_P28 PIO_PUSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P28_Msk instead */ 3505 #define PIO_PUSR_P29_Pos 29 /**< (PIO_PUSR) Pull-Up Status Position */ 3506 #define PIO_PUSR_P29_Msk (_U_(0x1) << PIO_PUSR_P29_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3507 #define PIO_PUSR_P29 PIO_PUSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P29_Msk instead */ 3508 #define PIO_PUSR_P30_Pos 30 /**< (PIO_PUSR) Pull-Up Status Position */ 3509 #define PIO_PUSR_P30_Msk (_U_(0x1) << PIO_PUSR_P30_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3510 #define PIO_PUSR_P30 PIO_PUSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P30_Msk instead */ 3511 #define PIO_PUSR_P31_Pos 31 /**< (PIO_PUSR) Pull-Up Status Position */ 3512 #define PIO_PUSR_P31_Msk (_U_(0x1) << PIO_PUSR_P31_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ 3513 #define PIO_PUSR_P31 PIO_PUSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P31_Msk instead */ 3514 #define PIO_PUSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PUSR) Register MASK (Use PIO_PUSR_Msk instead) */ 3515 #define PIO_PUSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PUSR) Register Mask */ 3516 3517 #define PIO_PUSR_P_Pos 0 /**< (PIO_PUSR Position) Pull-Up Status */ 3518 #define PIO_PUSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PUSR_P_Pos) /**< (PIO_PUSR Mask) P */ 3519 #define PIO_PUSR_P(value) (PIO_PUSR_P_Msk & ((value) << PIO_PUSR_P_Pos)) 3520 3521 /* -------- PIO_ABCDSR : (PIO Offset: 0x70) (R/W 32) Peripheral ABCD Select Register 0 -------- */ 3522 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3523 #if COMPONENT_TYPEDEF_STYLE == 'N' 3524 typedef union { 3525 struct { 3526 uint32_t P0:1; /**< bit: 0 Peripheral Select */ 3527 uint32_t P1:1; /**< bit: 1 Peripheral Select */ 3528 uint32_t P2:1; /**< bit: 2 Peripheral Select */ 3529 uint32_t P3:1; /**< bit: 3 Peripheral Select */ 3530 uint32_t P4:1; /**< bit: 4 Peripheral Select */ 3531 uint32_t P5:1; /**< bit: 5 Peripheral Select */ 3532 uint32_t P6:1; /**< bit: 6 Peripheral Select */ 3533 uint32_t P7:1; /**< bit: 7 Peripheral Select */ 3534 uint32_t P8:1; /**< bit: 8 Peripheral Select */ 3535 uint32_t P9:1; /**< bit: 9 Peripheral Select */ 3536 uint32_t P10:1; /**< bit: 10 Peripheral Select */ 3537 uint32_t P11:1; /**< bit: 11 Peripheral Select */ 3538 uint32_t P12:1; /**< bit: 12 Peripheral Select */ 3539 uint32_t P13:1; /**< bit: 13 Peripheral Select */ 3540 uint32_t P14:1; /**< bit: 14 Peripheral Select */ 3541 uint32_t P15:1; /**< bit: 15 Peripheral Select */ 3542 uint32_t P16:1; /**< bit: 16 Peripheral Select */ 3543 uint32_t P17:1; /**< bit: 17 Peripheral Select */ 3544 uint32_t P18:1; /**< bit: 18 Peripheral Select */ 3545 uint32_t P19:1; /**< bit: 19 Peripheral Select */ 3546 uint32_t P20:1; /**< bit: 20 Peripheral Select */ 3547 uint32_t P21:1; /**< bit: 21 Peripheral Select */ 3548 uint32_t P22:1; /**< bit: 22 Peripheral Select */ 3549 uint32_t P23:1; /**< bit: 23 Peripheral Select */ 3550 uint32_t P24:1; /**< bit: 24 Peripheral Select */ 3551 uint32_t P25:1; /**< bit: 25 Peripheral Select */ 3552 uint32_t P26:1; /**< bit: 26 Peripheral Select */ 3553 uint32_t P27:1; /**< bit: 27 Peripheral Select */ 3554 uint32_t P28:1; /**< bit: 28 Peripheral Select */ 3555 uint32_t P29:1; /**< bit: 29 Peripheral Select */ 3556 uint32_t P30:1; /**< bit: 30 Peripheral Select */ 3557 uint32_t P31:1; /**< bit: 31 Peripheral Select */ 3558 } bit; /**< Structure used for bit access */ 3559 struct { 3560 uint32_t P:32; /**< bit: 0..31 Peripheral Select */ 3561 } vec; /**< Structure used for vec access */ 3562 uint32_t reg; /**< Type used for register access */ 3563 } PIO_ABCDSR_Type; 3564 #endif 3565 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3566 3567 #define PIO_ABCDSR_OFFSET (0x70) /**< (PIO_ABCDSR) Peripheral ABCD Select Register 0 Offset */ 3568 3569 #define PIO_ABCDSR_P0_Pos 0 /**< (PIO_ABCDSR) Peripheral Select Position */ 3570 #define PIO_ABCDSR_P0_Msk (_U_(0x1) << PIO_ABCDSR_P0_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3571 #define PIO_ABCDSR_P0 PIO_ABCDSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P0_Msk instead */ 3572 #define PIO_ABCDSR_P1_Pos 1 /**< (PIO_ABCDSR) Peripheral Select Position */ 3573 #define PIO_ABCDSR_P1_Msk (_U_(0x1) << PIO_ABCDSR_P1_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3574 #define PIO_ABCDSR_P1 PIO_ABCDSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P1_Msk instead */ 3575 #define PIO_ABCDSR_P2_Pos 2 /**< (PIO_ABCDSR) Peripheral Select Position */ 3576 #define PIO_ABCDSR_P2_Msk (_U_(0x1) << PIO_ABCDSR_P2_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3577 #define PIO_ABCDSR_P2 PIO_ABCDSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P2_Msk instead */ 3578 #define PIO_ABCDSR_P3_Pos 3 /**< (PIO_ABCDSR) Peripheral Select Position */ 3579 #define PIO_ABCDSR_P3_Msk (_U_(0x1) << PIO_ABCDSR_P3_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3580 #define PIO_ABCDSR_P3 PIO_ABCDSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P3_Msk instead */ 3581 #define PIO_ABCDSR_P4_Pos 4 /**< (PIO_ABCDSR) Peripheral Select Position */ 3582 #define PIO_ABCDSR_P4_Msk (_U_(0x1) << PIO_ABCDSR_P4_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3583 #define PIO_ABCDSR_P4 PIO_ABCDSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P4_Msk instead */ 3584 #define PIO_ABCDSR_P5_Pos 5 /**< (PIO_ABCDSR) Peripheral Select Position */ 3585 #define PIO_ABCDSR_P5_Msk (_U_(0x1) << PIO_ABCDSR_P5_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3586 #define PIO_ABCDSR_P5 PIO_ABCDSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P5_Msk instead */ 3587 #define PIO_ABCDSR_P6_Pos 6 /**< (PIO_ABCDSR) Peripheral Select Position */ 3588 #define PIO_ABCDSR_P6_Msk (_U_(0x1) << PIO_ABCDSR_P6_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3589 #define PIO_ABCDSR_P6 PIO_ABCDSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P6_Msk instead */ 3590 #define PIO_ABCDSR_P7_Pos 7 /**< (PIO_ABCDSR) Peripheral Select Position */ 3591 #define PIO_ABCDSR_P7_Msk (_U_(0x1) << PIO_ABCDSR_P7_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3592 #define PIO_ABCDSR_P7 PIO_ABCDSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P7_Msk instead */ 3593 #define PIO_ABCDSR_P8_Pos 8 /**< (PIO_ABCDSR) Peripheral Select Position */ 3594 #define PIO_ABCDSR_P8_Msk (_U_(0x1) << PIO_ABCDSR_P8_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3595 #define PIO_ABCDSR_P8 PIO_ABCDSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P8_Msk instead */ 3596 #define PIO_ABCDSR_P9_Pos 9 /**< (PIO_ABCDSR) Peripheral Select Position */ 3597 #define PIO_ABCDSR_P9_Msk (_U_(0x1) << PIO_ABCDSR_P9_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3598 #define PIO_ABCDSR_P9 PIO_ABCDSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P9_Msk instead */ 3599 #define PIO_ABCDSR_P10_Pos 10 /**< (PIO_ABCDSR) Peripheral Select Position */ 3600 #define PIO_ABCDSR_P10_Msk (_U_(0x1) << PIO_ABCDSR_P10_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3601 #define PIO_ABCDSR_P10 PIO_ABCDSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P10_Msk instead */ 3602 #define PIO_ABCDSR_P11_Pos 11 /**< (PIO_ABCDSR) Peripheral Select Position */ 3603 #define PIO_ABCDSR_P11_Msk (_U_(0x1) << PIO_ABCDSR_P11_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3604 #define PIO_ABCDSR_P11 PIO_ABCDSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P11_Msk instead */ 3605 #define PIO_ABCDSR_P12_Pos 12 /**< (PIO_ABCDSR) Peripheral Select Position */ 3606 #define PIO_ABCDSR_P12_Msk (_U_(0x1) << PIO_ABCDSR_P12_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3607 #define PIO_ABCDSR_P12 PIO_ABCDSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P12_Msk instead */ 3608 #define PIO_ABCDSR_P13_Pos 13 /**< (PIO_ABCDSR) Peripheral Select Position */ 3609 #define PIO_ABCDSR_P13_Msk (_U_(0x1) << PIO_ABCDSR_P13_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3610 #define PIO_ABCDSR_P13 PIO_ABCDSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P13_Msk instead */ 3611 #define PIO_ABCDSR_P14_Pos 14 /**< (PIO_ABCDSR) Peripheral Select Position */ 3612 #define PIO_ABCDSR_P14_Msk (_U_(0x1) << PIO_ABCDSR_P14_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3613 #define PIO_ABCDSR_P14 PIO_ABCDSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P14_Msk instead */ 3614 #define PIO_ABCDSR_P15_Pos 15 /**< (PIO_ABCDSR) Peripheral Select Position */ 3615 #define PIO_ABCDSR_P15_Msk (_U_(0x1) << PIO_ABCDSR_P15_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3616 #define PIO_ABCDSR_P15 PIO_ABCDSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P15_Msk instead */ 3617 #define PIO_ABCDSR_P16_Pos 16 /**< (PIO_ABCDSR) Peripheral Select Position */ 3618 #define PIO_ABCDSR_P16_Msk (_U_(0x1) << PIO_ABCDSR_P16_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3619 #define PIO_ABCDSR_P16 PIO_ABCDSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P16_Msk instead */ 3620 #define PIO_ABCDSR_P17_Pos 17 /**< (PIO_ABCDSR) Peripheral Select Position */ 3621 #define PIO_ABCDSR_P17_Msk (_U_(0x1) << PIO_ABCDSR_P17_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3622 #define PIO_ABCDSR_P17 PIO_ABCDSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P17_Msk instead */ 3623 #define PIO_ABCDSR_P18_Pos 18 /**< (PIO_ABCDSR) Peripheral Select Position */ 3624 #define PIO_ABCDSR_P18_Msk (_U_(0x1) << PIO_ABCDSR_P18_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3625 #define PIO_ABCDSR_P18 PIO_ABCDSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P18_Msk instead */ 3626 #define PIO_ABCDSR_P19_Pos 19 /**< (PIO_ABCDSR) Peripheral Select Position */ 3627 #define PIO_ABCDSR_P19_Msk (_U_(0x1) << PIO_ABCDSR_P19_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3628 #define PIO_ABCDSR_P19 PIO_ABCDSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P19_Msk instead */ 3629 #define PIO_ABCDSR_P20_Pos 20 /**< (PIO_ABCDSR) Peripheral Select Position */ 3630 #define PIO_ABCDSR_P20_Msk (_U_(0x1) << PIO_ABCDSR_P20_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3631 #define PIO_ABCDSR_P20 PIO_ABCDSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P20_Msk instead */ 3632 #define PIO_ABCDSR_P21_Pos 21 /**< (PIO_ABCDSR) Peripheral Select Position */ 3633 #define PIO_ABCDSR_P21_Msk (_U_(0x1) << PIO_ABCDSR_P21_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3634 #define PIO_ABCDSR_P21 PIO_ABCDSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P21_Msk instead */ 3635 #define PIO_ABCDSR_P22_Pos 22 /**< (PIO_ABCDSR) Peripheral Select Position */ 3636 #define PIO_ABCDSR_P22_Msk (_U_(0x1) << PIO_ABCDSR_P22_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3637 #define PIO_ABCDSR_P22 PIO_ABCDSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P22_Msk instead */ 3638 #define PIO_ABCDSR_P23_Pos 23 /**< (PIO_ABCDSR) Peripheral Select Position */ 3639 #define PIO_ABCDSR_P23_Msk (_U_(0x1) << PIO_ABCDSR_P23_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3640 #define PIO_ABCDSR_P23 PIO_ABCDSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P23_Msk instead */ 3641 #define PIO_ABCDSR_P24_Pos 24 /**< (PIO_ABCDSR) Peripheral Select Position */ 3642 #define PIO_ABCDSR_P24_Msk (_U_(0x1) << PIO_ABCDSR_P24_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3643 #define PIO_ABCDSR_P24 PIO_ABCDSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P24_Msk instead */ 3644 #define PIO_ABCDSR_P25_Pos 25 /**< (PIO_ABCDSR) Peripheral Select Position */ 3645 #define PIO_ABCDSR_P25_Msk (_U_(0x1) << PIO_ABCDSR_P25_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3646 #define PIO_ABCDSR_P25 PIO_ABCDSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P25_Msk instead */ 3647 #define PIO_ABCDSR_P26_Pos 26 /**< (PIO_ABCDSR) Peripheral Select Position */ 3648 #define PIO_ABCDSR_P26_Msk (_U_(0x1) << PIO_ABCDSR_P26_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3649 #define PIO_ABCDSR_P26 PIO_ABCDSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P26_Msk instead */ 3650 #define PIO_ABCDSR_P27_Pos 27 /**< (PIO_ABCDSR) Peripheral Select Position */ 3651 #define PIO_ABCDSR_P27_Msk (_U_(0x1) << PIO_ABCDSR_P27_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3652 #define PIO_ABCDSR_P27 PIO_ABCDSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P27_Msk instead */ 3653 #define PIO_ABCDSR_P28_Pos 28 /**< (PIO_ABCDSR) Peripheral Select Position */ 3654 #define PIO_ABCDSR_P28_Msk (_U_(0x1) << PIO_ABCDSR_P28_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3655 #define PIO_ABCDSR_P28 PIO_ABCDSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P28_Msk instead */ 3656 #define PIO_ABCDSR_P29_Pos 29 /**< (PIO_ABCDSR) Peripheral Select Position */ 3657 #define PIO_ABCDSR_P29_Msk (_U_(0x1) << PIO_ABCDSR_P29_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3658 #define PIO_ABCDSR_P29 PIO_ABCDSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P29_Msk instead */ 3659 #define PIO_ABCDSR_P30_Pos 30 /**< (PIO_ABCDSR) Peripheral Select Position */ 3660 #define PIO_ABCDSR_P30_Msk (_U_(0x1) << PIO_ABCDSR_P30_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3661 #define PIO_ABCDSR_P30 PIO_ABCDSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P30_Msk instead */ 3662 #define PIO_ABCDSR_P31_Pos 31 /**< (PIO_ABCDSR) Peripheral Select Position */ 3663 #define PIO_ABCDSR_P31_Msk (_U_(0x1) << PIO_ABCDSR_P31_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ 3664 #define PIO_ABCDSR_P31 PIO_ABCDSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P31_Msk instead */ 3665 #define PIO_ABCDSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_ABCDSR) Register MASK (Use PIO_ABCDSR_Msk instead) */ 3666 #define PIO_ABCDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_ABCDSR) Register Mask */ 3667 3668 #define PIO_ABCDSR_P_Pos 0 /**< (PIO_ABCDSR Position) Peripheral Select */ 3669 #define PIO_ABCDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_ABCDSR_P_Pos) /**< (PIO_ABCDSR Mask) P */ 3670 #define PIO_ABCDSR_P(value) (PIO_ABCDSR_P_Msk & ((value) << PIO_ABCDSR_P_Pos)) 3671 3672 /* -------- PIO_IFSCDR : (PIO Offset: 0x80) (/W 32) Input Filter Slow Clock Disable Register -------- */ 3673 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3674 #if COMPONENT_TYPEDEF_STYLE == 'N' 3675 typedef union { 3676 struct { 3677 uint32_t P0:1; /**< bit: 0 Peripheral Clock Glitch Filtering Select */ 3678 uint32_t P1:1; /**< bit: 1 Peripheral Clock Glitch Filtering Select */ 3679 uint32_t P2:1; /**< bit: 2 Peripheral Clock Glitch Filtering Select */ 3680 uint32_t P3:1; /**< bit: 3 Peripheral Clock Glitch Filtering Select */ 3681 uint32_t P4:1; /**< bit: 4 Peripheral Clock Glitch Filtering Select */ 3682 uint32_t P5:1; /**< bit: 5 Peripheral Clock Glitch Filtering Select */ 3683 uint32_t P6:1; /**< bit: 6 Peripheral Clock Glitch Filtering Select */ 3684 uint32_t P7:1; /**< bit: 7 Peripheral Clock Glitch Filtering Select */ 3685 uint32_t P8:1; /**< bit: 8 Peripheral Clock Glitch Filtering Select */ 3686 uint32_t P9:1; /**< bit: 9 Peripheral Clock Glitch Filtering Select */ 3687 uint32_t P10:1; /**< bit: 10 Peripheral Clock Glitch Filtering Select */ 3688 uint32_t P11:1; /**< bit: 11 Peripheral Clock Glitch Filtering Select */ 3689 uint32_t P12:1; /**< bit: 12 Peripheral Clock Glitch Filtering Select */ 3690 uint32_t P13:1; /**< bit: 13 Peripheral Clock Glitch Filtering Select */ 3691 uint32_t P14:1; /**< bit: 14 Peripheral Clock Glitch Filtering Select */ 3692 uint32_t P15:1; /**< bit: 15 Peripheral Clock Glitch Filtering Select */ 3693 uint32_t P16:1; /**< bit: 16 Peripheral Clock Glitch Filtering Select */ 3694 uint32_t P17:1; /**< bit: 17 Peripheral Clock Glitch Filtering Select */ 3695 uint32_t P18:1; /**< bit: 18 Peripheral Clock Glitch Filtering Select */ 3696 uint32_t P19:1; /**< bit: 19 Peripheral Clock Glitch Filtering Select */ 3697 uint32_t P20:1; /**< bit: 20 Peripheral Clock Glitch Filtering Select */ 3698 uint32_t P21:1; /**< bit: 21 Peripheral Clock Glitch Filtering Select */ 3699 uint32_t P22:1; /**< bit: 22 Peripheral Clock Glitch Filtering Select */ 3700 uint32_t P23:1; /**< bit: 23 Peripheral Clock Glitch Filtering Select */ 3701 uint32_t P24:1; /**< bit: 24 Peripheral Clock Glitch Filtering Select */ 3702 uint32_t P25:1; /**< bit: 25 Peripheral Clock Glitch Filtering Select */ 3703 uint32_t P26:1; /**< bit: 26 Peripheral Clock Glitch Filtering Select */ 3704 uint32_t P27:1; /**< bit: 27 Peripheral Clock Glitch Filtering Select */ 3705 uint32_t P28:1; /**< bit: 28 Peripheral Clock Glitch Filtering Select */ 3706 uint32_t P29:1; /**< bit: 29 Peripheral Clock Glitch Filtering Select */ 3707 uint32_t P30:1; /**< bit: 30 Peripheral Clock Glitch Filtering Select */ 3708 uint32_t P31:1; /**< bit: 31 Peripheral Clock Glitch Filtering Select */ 3709 } bit; /**< Structure used for bit access */ 3710 struct { 3711 uint32_t P:32; /**< bit: 0..31 Peripheral Clock Glitch Filtering Select */ 3712 } vec; /**< Structure used for vec access */ 3713 uint32_t reg; /**< Type used for register access */ 3714 } PIO_IFSCDR_Type; 3715 #endif 3716 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3717 3718 #define PIO_IFSCDR_OFFSET (0x80) /**< (PIO_IFSCDR) Input Filter Slow Clock Disable Register Offset */ 3719 3720 #define PIO_IFSCDR_P0_Pos 0 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3721 #define PIO_IFSCDR_P0_Msk (_U_(0x1) << PIO_IFSCDR_P0_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3722 #define PIO_IFSCDR_P0 PIO_IFSCDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P0_Msk instead */ 3723 #define PIO_IFSCDR_P1_Pos 1 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3724 #define PIO_IFSCDR_P1_Msk (_U_(0x1) << PIO_IFSCDR_P1_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3725 #define PIO_IFSCDR_P1 PIO_IFSCDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P1_Msk instead */ 3726 #define PIO_IFSCDR_P2_Pos 2 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3727 #define PIO_IFSCDR_P2_Msk (_U_(0x1) << PIO_IFSCDR_P2_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3728 #define PIO_IFSCDR_P2 PIO_IFSCDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P2_Msk instead */ 3729 #define PIO_IFSCDR_P3_Pos 3 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3730 #define PIO_IFSCDR_P3_Msk (_U_(0x1) << PIO_IFSCDR_P3_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3731 #define PIO_IFSCDR_P3 PIO_IFSCDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P3_Msk instead */ 3732 #define PIO_IFSCDR_P4_Pos 4 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3733 #define PIO_IFSCDR_P4_Msk (_U_(0x1) << PIO_IFSCDR_P4_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3734 #define PIO_IFSCDR_P4 PIO_IFSCDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P4_Msk instead */ 3735 #define PIO_IFSCDR_P5_Pos 5 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3736 #define PIO_IFSCDR_P5_Msk (_U_(0x1) << PIO_IFSCDR_P5_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3737 #define PIO_IFSCDR_P5 PIO_IFSCDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P5_Msk instead */ 3738 #define PIO_IFSCDR_P6_Pos 6 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3739 #define PIO_IFSCDR_P6_Msk (_U_(0x1) << PIO_IFSCDR_P6_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3740 #define PIO_IFSCDR_P6 PIO_IFSCDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P6_Msk instead */ 3741 #define PIO_IFSCDR_P7_Pos 7 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3742 #define PIO_IFSCDR_P7_Msk (_U_(0x1) << PIO_IFSCDR_P7_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3743 #define PIO_IFSCDR_P7 PIO_IFSCDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P7_Msk instead */ 3744 #define PIO_IFSCDR_P8_Pos 8 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3745 #define PIO_IFSCDR_P8_Msk (_U_(0x1) << PIO_IFSCDR_P8_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3746 #define PIO_IFSCDR_P8 PIO_IFSCDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P8_Msk instead */ 3747 #define PIO_IFSCDR_P9_Pos 9 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3748 #define PIO_IFSCDR_P9_Msk (_U_(0x1) << PIO_IFSCDR_P9_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3749 #define PIO_IFSCDR_P9 PIO_IFSCDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P9_Msk instead */ 3750 #define PIO_IFSCDR_P10_Pos 10 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3751 #define PIO_IFSCDR_P10_Msk (_U_(0x1) << PIO_IFSCDR_P10_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3752 #define PIO_IFSCDR_P10 PIO_IFSCDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P10_Msk instead */ 3753 #define PIO_IFSCDR_P11_Pos 11 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3754 #define PIO_IFSCDR_P11_Msk (_U_(0x1) << PIO_IFSCDR_P11_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3755 #define PIO_IFSCDR_P11 PIO_IFSCDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P11_Msk instead */ 3756 #define PIO_IFSCDR_P12_Pos 12 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3757 #define PIO_IFSCDR_P12_Msk (_U_(0x1) << PIO_IFSCDR_P12_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3758 #define PIO_IFSCDR_P12 PIO_IFSCDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P12_Msk instead */ 3759 #define PIO_IFSCDR_P13_Pos 13 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3760 #define PIO_IFSCDR_P13_Msk (_U_(0x1) << PIO_IFSCDR_P13_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3761 #define PIO_IFSCDR_P13 PIO_IFSCDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P13_Msk instead */ 3762 #define PIO_IFSCDR_P14_Pos 14 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3763 #define PIO_IFSCDR_P14_Msk (_U_(0x1) << PIO_IFSCDR_P14_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3764 #define PIO_IFSCDR_P14 PIO_IFSCDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P14_Msk instead */ 3765 #define PIO_IFSCDR_P15_Pos 15 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3766 #define PIO_IFSCDR_P15_Msk (_U_(0x1) << PIO_IFSCDR_P15_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3767 #define PIO_IFSCDR_P15 PIO_IFSCDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P15_Msk instead */ 3768 #define PIO_IFSCDR_P16_Pos 16 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3769 #define PIO_IFSCDR_P16_Msk (_U_(0x1) << PIO_IFSCDR_P16_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3770 #define PIO_IFSCDR_P16 PIO_IFSCDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P16_Msk instead */ 3771 #define PIO_IFSCDR_P17_Pos 17 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3772 #define PIO_IFSCDR_P17_Msk (_U_(0x1) << PIO_IFSCDR_P17_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3773 #define PIO_IFSCDR_P17 PIO_IFSCDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P17_Msk instead */ 3774 #define PIO_IFSCDR_P18_Pos 18 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3775 #define PIO_IFSCDR_P18_Msk (_U_(0x1) << PIO_IFSCDR_P18_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3776 #define PIO_IFSCDR_P18 PIO_IFSCDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P18_Msk instead */ 3777 #define PIO_IFSCDR_P19_Pos 19 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3778 #define PIO_IFSCDR_P19_Msk (_U_(0x1) << PIO_IFSCDR_P19_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3779 #define PIO_IFSCDR_P19 PIO_IFSCDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P19_Msk instead */ 3780 #define PIO_IFSCDR_P20_Pos 20 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3781 #define PIO_IFSCDR_P20_Msk (_U_(0x1) << PIO_IFSCDR_P20_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3782 #define PIO_IFSCDR_P20 PIO_IFSCDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P20_Msk instead */ 3783 #define PIO_IFSCDR_P21_Pos 21 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3784 #define PIO_IFSCDR_P21_Msk (_U_(0x1) << PIO_IFSCDR_P21_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3785 #define PIO_IFSCDR_P21 PIO_IFSCDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P21_Msk instead */ 3786 #define PIO_IFSCDR_P22_Pos 22 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3787 #define PIO_IFSCDR_P22_Msk (_U_(0x1) << PIO_IFSCDR_P22_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3788 #define PIO_IFSCDR_P22 PIO_IFSCDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P22_Msk instead */ 3789 #define PIO_IFSCDR_P23_Pos 23 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3790 #define PIO_IFSCDR_P23_Msk (_U_(0x1) << PIO_IFSCDR_P23_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3791 #define PIO_IFSCDR_P23 PIO_IFSCDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P23_Msk instead */ 3792 #define PIO_IFSCDR_P24_Pos 24 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3793 #define PIO_IFSCDR_P24_Msk (_U_(0x1) << PIO_IFSCDR_P24_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3794 #define PIO_IFSCDR_P24 PIO_IFSCDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P24_Msk instead */ 3795 #define PIO_IFSCDR_P25_Pos 25 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3796 #define PIO_IFSCDR_P25_Msk (_U_(0x1) << PIO_IFSCDR_P25_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3797 #define PIO_IFSCDR_P25 PIO_IFSCDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P25_Msk instead */ 3798 #define PIO_IFSCDR_P26_Pos 26 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3799 #define PIO_IFSCDR_P26_Msk (_U_(0x1) << PIO_IFSCDR_P26_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3800 #define PIO_IFSCDR_P26 PIO_IFSCDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P26_Msk instead */ 3801 #define PIO_IFSCDR_P27_Pos 27 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3802 #define PIO_IFSCDR_P27_Msk (_U_(0x1) << PIO_IFSCDR_P27_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3803 #define PIO_IFSCDR_P27 PIO_IFSCDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P27_Msk instead */ 3804 #define PIO_IFSCDR_P28_Pos 28 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3805 #define PIO_IFSCDR_P28_Msk (_U_(0x1) << PIO_IFSCDR_P28_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3806 #define PIO_IFSCDR_P28 PIO_IFSCDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P28_Msk instead */ 3807 #define PIO_IFSCDR_P29_Pos 29 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3808 #define PIO_IFSCDR_P29_Msk (_U_(0x1) << PIO_IFSCDR_P29_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3809 #define PIO_IFSCDR_P29 PIO_IFSCDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P29_Msk instead */ 3810 #define PIO_IFSCDR_P30_Pos 30 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3811 #define PIO_IFSCDR_P30_Msk (_U_(0x1) << PIO_IFSCDR_P30_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3812 #define PIO_IFSCDR_P30 PIO_IFSCDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P30_Msk instead */ 3813 #define PIO_IFSCDR_P31_Pos 31 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ 3814 #define PIO_IFSCDR_P31_Msk (_U_(0x1) << PIO_IFSCDR_P31_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ 3815 #define PIO_IFSCDR_P31 PIO_IFSCDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P31_Msk instead */ 3816 #define PIO_IFSCDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IFSCDR) Register MASK (Use PIO_IFSCDR_Msk instead) */ 3817 #define PIO_IFSCDR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSCDR) Register Mask */ 3818 3819 #define PIO_IFSCDR_P_Pos 0 /**< (PIO_IFSCDR Position) Peripheral Clock Glitch Filtering Select */ 3820 #define PIO_IFSCDR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSCDR_P_Pos) /**< (PIO_IFSCDR Mask) P */ 3821 #define PIO_IFSCDR_P(value) (PIO_IFSCDR_P_Msk & ((value) << PIO_IFSCDR_P_Pos)) 3822 3823 /* -------- PIO_IFSCER : (PIO Offset: 0x84) (/W 32) Input Filter Slow Clock Enable Register -------- */ 3824 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3825 #if COMPONENT_TYPEDEF_STYLE == 'N' 3826 typedef union { 3827 struct { 3828 uint32_t P0:1; /**< bit: 0 Slow Clock Debouncing Filtering Select */ 3829 uint32_t P1:1; /**< bit: 1 Slow Clock Debouncing Filtering Select */ 3830 uint32_t P2:1; /**< bit: 2 Slow Clock Debouncing Filtering Select */ 3831 uint32_t P3:1; /**< bit: 3 Slow Clock Debouncing Filtering Select */ 3832 uint32_t P4:1; /**< bit: 4 Slow Clock Debouncing Filtering Select */ 3833 uint32_t P5:1; /**< bit: 5 Slow Clock Debouncing Filtering Select */ 3834 uint32_t P6:1; /**< bit: 6 Slow Clock Debouncing Filtering Select */ 3835 uint32_t P7:1; /**< bit: 7 Slow Clock Debouncing Filtering Select */ 3836 uint32_t P8:1; /**< bit: 8 Slow Clock Debouncing Filtering Select */ 3837 uint32_t P9:1; /**< bit: 9 Slow Clock Debouncing Filtering Select */ 3838 uint32_t P10:1; /**< bit: 10 Slow Clock Debouncing Filtering Select */ 3839 uint32_t P11:1; /**< bit: 11 Slow Clock Debouncing Filtering Select */ 3840 uint32_t P12:1; /**< bit: 12 Slow Clock Debouncing Filtering Select */ 3841 uint32_t P13:1; /**< bit: 13 Slow Clock Debouncing Filtering Select */ 3842 uint32_t P14:1; /**< bit: 14 Slow Clock Debouncing Filtering Select */ 3843 uint32_t P15:1; /**< bit: 15 Slow Clock Debouncing Filtering Select */ 3844 uint32_t P16:1; /**< bit: 16 Slow Clock Debouncing Filtering Select */ 3845 uint32_t P17:1; /**< bit: 17 Slow Clock Debouncing Filtering Select */ 3846 uint32_t P18:1; /**< bit: 18 Slow Clock Debouncing Filtering Select */ 3847 uint32_t P19:1; /**< bit: 19 Slow Clock Debouncing Filtering Select */ 3848 uint32_t P20:1; /**< bit: 20 Slow Clock Debouncing Filtering Select */ 3849 uint32_t P21:1; /**< bit: 21 Slow Clock Debouncing Filtering Select */ 3850 uint32_t P22:1; /**< bit: 22 Slow Clock Debouncing Filtering Select */ 3851 uint32_t P23:1; /**< bit: 23 Slow Clock Debouncing Filtering Select */ 3852 uint32_t P24:1; /**< bit: 24 Slow Clock Debouncing Filtering Select */ 3853 uint32_t P25:1; /**< bit: 25 Slow Clock Debouncing Filtering Select */ 3854 uint32_t P26:1; /**< bit: 26 Slow Clock Debouncing Filtering Select */ 3855 uint32_t P27:1; /**< bit: 27 Slow Clock Debouncing Filtering Select */ 3856 uint32_t P28:1; /**< bit: 28 Slow Clock Debouncing Filtering Select */ 3857 uint32_t P29:1; /**< bit: 29 Slow Clock Debouncing Filtering Select */ 3858 uint32_t P30:1; /**< bit: 30 Slow Clock Debouncing Filtering Select */ 3859 uint32_t P31:1; /**< bit: 31 Slow Clock Debouncing Filtering Select */ 3860 } bit; /**< Structure used for bit access */ 3861 struct { 3862 uint32_t P:32; /**< bit: 0..31 Slow Clock Debouncing Filtering Select */ 3863 } vec; /**< Structure used for vec access */ 3864 uint32_t reg; /**< Type used for register access */ 3865 } PIO_IFSCER_Type; 3866 #endif 3867 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3868 3869 #define PIO_IFSCER_OFFSET (0x84) /**< (PIO_IFSCER) Input Filter Slow Clock Enable Register Offset */ 3870 3871 #define PIO_IFSCER_P0_Pos 0 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3872 #define PIO_IFSCER_P0_Msk (_U_(0x1) << PIO_IFSCER_P0_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3873 #define PIO_IFSCER_P0 PIO_IFSCER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P0_Msk instead */ 3874 #define PIO_IFSCER_P1_Pos 1 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3875 #define PIO_IFSCER_P1_Msk (_U_(0x1) << PIO_IFSCER_P1_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3876 #define PIO_IFSCER_P1 PIO_IFSCER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P1_Msk instead */ 3877 #define PIO_IFSCER_P2_Pos 2 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3878 #define PIO_IFSCER_P2_Msk (_U_(0x1) << PIO_IFSCER_P2_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3879 #define PIO_IFSCER_P2 PIO_IFSCER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P2_Msk instead */ 3880 #define PIO_IFSCER_P3_Pos 3 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3881 #define PIO_IFSCER_P3_Msk (_U_(0x1) << PIO_IFSCER_P3_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3882 #define PIO_IFSCER_P3 PIO_IFSCER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P3_Msk instead */ 3883 #define PIO_IFSCER_P4_Pos 4 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3884 #define PIO_IFSCER_P4_Msk (_U_(0x1) << PIO_IFSCER_P4_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3885 #define PIO_IFSCER_P4 PIO_IFSCER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P4_Msk instead */ 3886 #define PIO_IFSCER_P5_Pos 5 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3887 #define PIO_IFSCER_P5_Msk (_U_(0x1) << PIO_IFSCER_P5_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3888 #define PIO_IFSCER_P5 PIO_IFSCER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P5_Msk instead */ 3889 #define PIO_IFSCER_P6_Pos 6 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3890 #define PIO_IFSCER_P6_Msk (_U_(0x1) << PIO_IFSCER_P6_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3891 #define PIO_IFSCER_P6 PIO_IFSCER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P6_Msk instead */ 3892 #define PIO_IFSCER_P7_Pos 7 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3893 #define PIO_IFSCER_P7_Msk (_U_(0x1) << PIO_IFSCER_P7_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3894 #define PIO_IFSCER_P7 PIO_IFSCER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P7_Msk instead */ 3895 #define PIO_IFSCER_P8_Pos 8 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3896 #define PIO_IFSCER_P8_Msk (_U_(0x1) << PIO_IFSCER_P8_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3897 #define PIO_IFSCER_P8 PIO_IFSCER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P8_Msk instead */ 3898 #define PIO_IFSCER_P9_Pos 9 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3899 #define PIO_IFSCER_P9_Msk (_U_(0x1) << PIO_IFSCER_P9_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3900 #define PIO_IFSCER_P9 PIO_IFSCER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P9_Msk instead */ 3901 #define PIO_IFSCER_P10_Pos 10 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3902 #define PIO_IFSCER_P10_Msk (_U_(0x1) << PIO_IFSCER_P10_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3903 #define PIO_IFSCER_P10 PIO_IFSCER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P10_Msk instead */ 3904 #define PIO_IFSCER_P11_Pos 11 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3905 #define PIO_IFSCER_P11_Msk (_U_(0x1) << PIO_IFSCER_P11_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3906 #define PIO_IFSCER_P11 PIO_IFSCER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P11_Msk instead */ 3907 #define PIO_IFSCER_P12_Pos 12 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3908 #define PIO_IFSCER_P12_Msk (_U_(0x1) << PIO_IFSCER_P12_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3909 #define PIO_IFSCER_P12 PIO_IFSCER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P12_Msk instead */ 3910 #define PIO_IFSCER_P13_Pos 13 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3911 #define PIO_IFSCER_P13_Msk (_U_(0x1) << PIO_IFSCER_P13_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3912 #define PIO_IFSCER_P13 PIO_IFSCER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P13_Msk instead */ 3913 #define PIO_IFSCER_P14_Pos 14 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3914 #define PIO_IFSCER_P14_Msk (_U_(0x1) << PIO_IFSCER_P14_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3915 #define PIO_IFSCER_P14 PIO_IFSCER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P14_Msk instead */ 3916 #define PIO_IFSCER_P15_Pos 15 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3917 #define PIO_IFSCER_P15_Msk (_U_(0x1) << PIO_IFSCER_P15_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3918 #define PIO_IFSCER_P15 PIO_IFSCER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P15_Msk instead */ 3919 #define PIO_IFSCER_P16_Pos 16 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3920 #define PIO_IFSCER_P16_Msk (_U_(0x1) << PIO_IFSCER_P16_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3921 #define PIO_IFSCER_P16 PIO_IFSCER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P16_Msk instead */ 3922 #define PIO_IFSCER_P17_Pos 17 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3923 #define PIO_IFSCER_P17_Msk (_U_(0x1) << PIO_IFSCER_P17_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3924 #define PIO_IFSCER_P17 PIO_IFSCER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P17_Msk instead */ 3925 #define PIO_IFSCER_P18_Pos 18 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3926 #define PIO_IFSCER_P18_Msk (_U_(0x1) << PIO_IFSCER_P18_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3927 #define PIO_IFSCER_P18 PIO_IFSCER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P18_Msk instead */ 3928 #define PIO_IFSCER_P19_Pos 19 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3929 #define PIO_IFSCER_P19_Msk (_U_(0x1) << PIO_IFSCER_P19_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3930 #define PIO_IFSCER_P19 PIO_IFSCER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P19_Msk instead */ 3931 #define PIO_IFSCER_P20_Pos 20 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3932 #define PIO_IFSCER_P20_Msk (_U_(0x1) << PIO_IFSCER_P20_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3933 #define PIO_IFSCER_P20 PIO_IFSCER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P20_Msk instead */ 3934 #define PIO_IFSCER_P21_Pos 21 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3935 #define PIO_IFSCER_P21_Msk (_U_(0x1) << PIO_IFSCER_P21_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3936 #define PIO_IFSCER_P21 PIO_IFSCER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P21_Msk instead */ 3937 #define PIO_IFSCER_P22_Pos 22 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3938 #define PIO_IFSCER_P22_Msk (_U_(0x1) << PIO_IFSCER_P22_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3939 #define PIO_IFSCER_P22 PIO_IFSCER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P22_Msk instead */ 3940 #define PIO_IFSCER_P23_Pos 23 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3941 #define PIO_IFSCER_P23_Msk (_U_(0x1) << PIO_IFSCER_P23_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3942 #define PIO_IFSCER_P23 PIO_IFSCER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P23_Msk instead */ 3943 #define PIO_IFSCER_P24_Pos 24 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3944 #define PIO_IFSCER_P24_Msk (_U_(0x1) << PIO_IFSCER_P24_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3945 #define PIO_IFSCER_P24 PIO_IFSCER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P24_Msk instead */ 3946 #define PIO_IFSCER_P25_Pos 25 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3947 #define PIO_IFSCER_P25_Msk (_U_(0x1) << PIO_IFSCER_P25_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3948 #define PIO_IFSCER_P25 PIO_IFSCER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P25_Msk instead */ 3949 #define PIO_IFSCER_P26_Pos 26 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3950 #define PIO_IFSCER_P26_Msk (_U_(0x1) << PIO_IFSCER_P26_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3951 #define PIO_IFSCER_P26 PIO_IFSCER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P26_Msk instead */ 3952 #define PIO_IFSCER_P27_Pos 27 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3953 #define PIO_IFSCER_P27_Msk (_U_(0x1) << PIO_IFSCER_P27_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3954 #define PIO_IFSCER_P27 PIO_IFSCER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P27_Msk instead */ 3955 #define PIO_IFSCER_P28_Pos 28 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3956 #define PIO_IFSCER_P28_Msk (_U_(0x1) << PIO_IFSCER_P28_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3957 #define PIO_IFSCER_P28 PIO_IFSCER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P28_Msk instead */ 3958 #define PIO_IFSCER_P29_Pos 29 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3959 #define PIO_IFSCER_P29_Msk (_U_(0x1) << PIO_IFSCER_P29_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3960 #define PIO_IFSCER_P29 PIO_IFSCER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P29_Msk instead */ 3961 #define PIO_IFSCER_P30_Pos 30 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3962 #define PIO_IFSCER_P30_Msk (_U_(0x1) << PIO_IFSCER_P30_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3963 #define PIO_IFSCER_P30 PIO_IFSCER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P30_Msk instead */ 3964 #define PIO_IFSCER_P31_Pos 31 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ 3965 #define PIO_IFSCER_P31_Msk (_U_(0x1) << PIO_IFSCER_P31_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ 3966 #define PIO_IFSCER_P31 PIO_IFSCER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P31_Msk instead */ 3967 #define PIO_IFSCER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IFSCER) Register MASK (Use PIO_IFSCER_Msk instead) */ 3968 #define PIO_IFSCER_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSCER) Register Mask */ 3969 3970 #define PIO_IFSCER_P_Pos 0 /**< (PIO_IFSCER Position) Slow Clock Debouncing Filtering Select */ 3971 #define PIO_IFSCER_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSCER_P_Pos) /**< (PIO_IFSCER Mask) P */ 3972 #define PIO_IFSCER_P(value) (PIO_IFSCER_P_Msk & ((value) << PIO_IFSCER_P_Pos)) 3973 3974 /* -------- PIO_IFSCSR : (PIO Offset: 0x88) (R/ 32) Input Filter Slow Clock Status Register -------- */ 3975 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3976 #if COMPONENT_TYPEDEF_STYLE == 'N' 3977 typedef union { 3978 struct { 3979 uint32_t P0:1; /**< bit: 0 Glitch or Debouncing Filter Selection Status */ 3980 uint32_t P1:1; /**< bit: 1 Glitch or Debouncing Filter Selection Status */ 3981 uint32_t P2:1; /**< bit: 2 Glitch or Debouncing Filter Selection Status */ 3982 uint32_t P3:1; /**< bit: 3 Glitch or Debouncing Filter Selection Status */ 3983 uint32_t P4:1; /**< bit: 4 Glitch or Debouncing Filter Selection Status */ 3984 uint32_t P5:1; /**< bit: 5 Glitch or Debouncing Filter Selection Status */ 3985 uint32_t P6:1; /**< bit: 6 Glitch or Debouncing Filter Selection Status */ 3986 uint32_t P7:1; /**< bit: 7 Glitch or Debouncing Filter Selection Status */ 3987 uint32_t P8:1; /**< bit: 8 Glitch or Debouncing Filter Selection Status */ 3988 uint32_t P9:1; /**< bit: 9 Glitch or Debouncing Filter Selection Status */ 3989 uint32_t P10:1; /**< bit: 10 Glitch or Debouncing Filter Selection Status */ 3990 uint32_t P11:1; /**< bit: 11 Glitch or Debouncing Filter Selection Status */ 3991 uint32_t P12:1; /**< bit: 12 Glitch or Debouncing Filter Selection Status */ 3992 uint32_t P13:1; /**< bit: 13 Glitch or Debouncing Filter Selection Status */ 3993 uint32_t P14:1; /**< bit: 14 Glitch or Debouncing Filter Selection Status */ 3994 uint32_t P15:1; /**< bit: 15 Glitch or Debouncing Filter Selection Status */ 3995 uint32_t P16:1; /**< bit: 16 Glitch or Debouncing Filter Selection Status */ 3996 uint32_t P17:1; /**< bit: 17 Glitch or Debouncing Filter Selection Status */ 3997 uint32_t P18:1; /**< bit: 18 Glitch or Debouncing Filter Selection Status */ 3998 uint32_t P19:1; /**< bit: 19 Glitch or Debouncing Filter Selection Status */ 3999 uint32_t P20:1; /**< bit: 20 Glitch or Debouncing Filter Selection Status */ 4000 uint32_t P21:1; /**< bit: 21 Glitch or Debouncing Filter Selection Status */ 4001 uint32_t P22:1; /**< bit: 22 Glitch or Debouncing Filter Selection Status */ 4002 uint32_t P23:1; /**< bit: 23 Glitch or Debouncing Filter Selection Status */ 4003 uint32_t P24:1; /**< bit: 24 Glitch or Debouncing Filter Selection Status */ 4004 uint32_t P25:1; /**< bit: 25 Glitch or Debouncing Filter Selection Status */ 4005 uint32_t P26:1; /**< bit: 26 Glitch or Debouncing Filter Selection Status */ 4006 uint32_t P27:1; /**< bit: 27 Glitch or Debouncing Filter Selection Status */ 4007 uint32_t P28:1; /**< bit: 28 Glitch or Debouncing Filter Selection Status */ 4008 uint32_t P29:1; /**< bit: 29 Glitch or Debouncing Filter Selection Status */ 4009 uint32_t P30:1; /**< bit: 30 Glitch or Debouncing Filter Selection Status */ 4010 uint32_t P31:1; /**< bit: 31 Glitch or Debouncing Filter Selection Status */ 4011 } bit; /**< Structure used for bit access */ 4012 struct { 4013 uint32_t P:32; /**< bit: 0..31 Glitch or Debouncing Filter Selection Status */ 4014 } vec; /**< Structure used for vec access */ 4015 uint32_t reg; /**< Type used for register access */ 4016 } PIO_IFSCSR_Type; 4017 #endif 4018 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4019 4020 #define PIO_IFSCSR_OFFSET (0x88) /**< (PIO_IFSCSR) Input Filter Slow Clock Status Register Offset */ 4021 4022 #define PIO_IFSCSR_P0_Pos 0 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4023 #define PIO_IFSCSR_P0_Msk (_U_(0x1) << PIO_IFSCSR_P0_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4024 #define PIO_IFSCSR_P0 PIO_IFSCSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P0_Msk instead */ 4025 #define PIO_IFSCSR_P1_Pos 1 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4026 #define PIO_IFSCSR_P1_Msk (_U_(0x1) << PIO_IFSCSR_P1_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4027 #define PIO_IFSCSR_P1 PIO_IFSCSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P1_Msk instead */ 4028 #define PIO_IFSCSR_P2_Pos 2 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4029 #define PIO_IFSCSR_P2_Msk (_U_(0x1) << PIO_IFSCSR_P2_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4030 #define PIO_IFSCSR_P2 PIO_IFSCSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P2_Msk instead */ 4031 #define PIO_IFSCSR_P3_Pos 3 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4032 #define PIO_IFSCSR_P3_Msk (_U_(0x1) << PIO_IFSCSR_P3_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4033 #define PIO_IFSCSR_P3 PIO_IFSCSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P3_Msk instead */ 4034 #define PIO_IFSCSR_P4_Pos 4 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4035 #define PIO_IFSCSR_P4_Msk (_U_(0x1) << PIO_IFSCSR_P4_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4036 #define PIO_IFSCSR_P4 PIO_IFSCSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P4_Msk instead */ 4037 #define PIO_IFSCSR_P5_Pos 5 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4038 #define PIO_IFSCSR_P5_Msk (_U_(0x1) << PIO_IFSCSR_P5_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4039 #define PIO_IFSCSR_P5 PIO_IFSCSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P5_Msk instead */ 4040 #define PIO_IFSCSR_P6_Pos 6 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4041 #define PIO_IFSCSR_P6_Msk (_U_(0x1) << PIO_IFSCSR_P6_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4042 #define PIO_IFSCSR_P6 PIO_IFSCSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P6_Msk instead */ 4043 #define PIO_IFSCSR_P7_Pos 7 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4044 #define PIO_IFSCSR_P7_Msk (_U_(0x1) << PIO_IFSCSR_P7_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4045 #define PIO_IFSCSR_P7 PIO_IFSCSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P7_Msk instead */ 4046 #define PIO_IFSCSR_P8_Pos 8 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4047 #define PIO_IFSCSR_P8_Msk (_U_(0x1) << PIO_IFSCSR_P8_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4048 #define PIO_IFSCSR_P8 PIO_IFSCSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P8_Msk instead */ 4049 #define PIO_IFSCSR_P9_Pos 9 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4050 #define PIO_IFSCSR_P9_Msk (_U_(0x1) << PIO_IFSCSR_P9_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4051 #define PIO_IFSCSR_P9 PIO_IFSCSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P9_Msk instead */ 4052 #define PIO_IFSCSR_P10_Pos 10 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4053 #define PIO_IFSCSR_P10_Msk (_U_(0x1) << PIO_IFSCSR_P10_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4054 #define PIO_IFSCSR_P10 PIO_IFSCSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P10_Msk instead */ 4055 #define PIO_IFSCSR_P11_Pos 11 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4056 #define PIO_IFSCSR_P11_Msk (_U_(0x1) << PIO_IFSCSR_P11_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4057 #define PIO_IFSCSR_P11 PIO_IFSCSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P11_Msk instead */ 4058 #define PIO_IFSCSR_P12_Pos 12 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4059 #define PIO_IFSCSR_P12_Msk (_U_(0x1) << PIO_IFSCSR_P12_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4060 #define PIO_IFSCSR_P12 PIO_IFSCSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P12_Msk instead */ 4061 #define PIO_IFSCSR_P13_Pos 13 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4062 #define PIO_IFSCSR_P13_Msk (_U_(0x1) << PIO_IFSCSR_P13_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4063 #define PIO_IFSCSR_P13 PIO_IFSCSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P13_Msk instead */ 4064 #define PIO_IFSCSR_P14_Pos 14 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4065 #define PIO_IFSCSR_P14_Msk (_U_(0x1) << PIO_IFSCSR_P14_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4066 #define PIO_IFSCSR_P14 PIO_IFSCSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P14_Msk instead */ 4067 #define PIO_IFSCSR_P15_Pos 15 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4068 #define PIO_IFSCSR_P15_Msk (_U_(0x1) << PIO_IFSCSR_P15_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4069 #define PIO_IFSCSR_P15 PIO_IFSCSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P15_Msk instead */ 4070 #define PIO_IFSCSR_P16_Pos 16 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4071 #define PIO_IFSCSR_P16_Msk (_U_(0x1) << PIO_IFSCSR_P16_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4072 #define PIO_IFSCSR_P16 PIO_IFSCSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P16_Msk instead */ 4073 #define PIO_IFSCSR_P17_Pos 17 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4074 #define PIO_IFSCSR_P17_Msk (_U_(0x1) << PIO_IFSCSR_P17_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4075 #define PIO_IFSCSR_P17 PIO_IFSCSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P17_Msk instead */ 4076 #define PIO_IFSCSR_P18_Pos 18 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4077 #define PIO_IFSCSR_P18_Msk (_U_(0x1) << PIO_IFSCSR_P18_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4078 #define PIO_IFSCSR_P18 PIO_IFSCSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P18_Msk instead */ 4079 #define PIO_IFSCSR_P19_Pos 19 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4080 #define PIO_IFSCSR_P19_Msk (_U_(0x1) << PIO_IFSCSR_P19_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4081 #define PIO_IFSCSR_P19 PIO_IFSCSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P19_Msk instead */ 4082 #define PIO_IFSCSR_P20_Pos 20 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4083 #define PIO_IFSCSR_P20_Msk (_U_(0x1) << PIO_IFSCSR_P20_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4084 #define PIO_IFSCSR_P20 PIO_IFSCSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P20_Msk instead */ 4085 #define PIO_IFSCSR_P21_Pos 21 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4086 #define PIO_IFSCSR_P21_Msk (_U_(0x1) << PIO_IFSCSR_P21_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4087 #define PIO_IFSCSR_P21 PIO_IFSCSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P21_Msk instead */ 4088 #define PIO_IFSCSR_P22_Pos 22 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4089 #define PIO_IFSCSR_P22_Msk (_U_(0x1) << PIO_IFSCSR_P22_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4090 #define PIO_IFSCSR_P22 PIO_IFSCSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P22_Msk instead */ 4091 #define PIO_IFSCSR_P23_Pos 23 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4092 #define PIO_IFSCSR_P23_Msk (_U_(0x1) << PIO_IFSCSR_P23_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4093 #define PIO_IFSCSR_P23 PIO_IFSCSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P23_Msk instead */ 4094 #define PIO_IFSCSR_P24_Pos 24 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4095 #define PIO_IFSCSR_P24_Msk (_U_(0x1) << PIO_IFSCSR_P24_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4096 #define PIO_IFSCSR_P24 PIO_IFSCSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P24_Msk instead */ 4097 #define PIO_IFSCSR_P25_Pos 25 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4098 #define PIO_IFSCSR_P25_Msk (_U_(0x1) << PIO_IFSCSR_P25_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4099 #define PIO_IFSCSR_P25 PIO_IFSCSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P25_Msk instead */ 4100 #define PIO_IFSCSR_P26_Pos 26 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4101 #define PIO_IFSCSR_P26_Msk (_U_(0x1) << PIO_IFSCSR_P26_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4102 #define PIO_IFSCSR_P26 PIO_IFSCSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P26_Msk instead */ 4103 #define PIO_IFSCSR_P27_Pos 27 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4104 #define PIO_IFSCSR_P27_Msk (_U_(0x1) << PIO_IFSCSR_P27_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4105 #define PIO_IFSCSR_P27 PIO_IFSCSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P27_Msk instead */ 4106 #define PIO_IFSCSR_P28_Pos 28 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4107 #define PIO_IFSCSR_P28_Msk (_U_(0x1) << PIO_IFSCSR_P28_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4108 #define PIO_IFSCSR_P28 PIO_IFSCSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P28_Msk instead */ 4109 #define PIO_IFSCSR_P29_Pos 29 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4110 #define PIO_IFSCSR_P29_Msk (_U_(0x1) << PIO_IFSCSR_P29_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4111 #define PIO_IFSCSR_P29 PIO_IFSCSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P29_Msk instead */ 4112 #define PIO_IFSCSR_P30_Pos 30 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4113 #define PIO_IFSCSR_P30_Msk (_U_(0x1) << PIO_IFSCSR_P30_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4114 #define PIO_IFSCSR_P30 PIO_IFSCSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P30_Msk instead */ 4115 #define PIO_IFSCSR_P31_Pos 31 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ 4116 #define PIO_IFSCSR_P31_Msk (_U_(0x1) << PIO_IFSCSR_P31_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ 4117 #define PIO_IFSCSR_P31 PIO_IFSCSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P31_Msk instead */ 4118 #define PIO_IFSCSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IFSCSR) Register MASK (Use PIO_IFSCSR_Msk instead) */ 4119 #define PIO_IFSCSR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSCSR) Register Mask */ 4120 4121 #define PIO_IFSCSR_P_Pos 0 /**< (PIO_IFSCSR Position) Glitch or Debouncing Filter Selection Status */ 4122 #define PIO_IFSCSR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSCSR_P_Pos) /**< (PIO_IFSCSR Mask) P */ 4123 #define PIO_IFSCSR_P(value) (PIO_IFSCSR_P_Msk & ((value) << PIO_IFSCSR_P_Pos)) 4124 4125 /* -------- PIO_SCDR : (PIO Offset: 0x8c) (R/W 32) Slow Clock Divider Debouncing Register -------- */ 4126 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4127 #if COMPONENT_TYPEDEF_STYLE == 'N' 4128 typedef union { 4129 struct { 4130 uint32_t DIV:14; /**< bit: 0..13 Slow Clock Divider Selection for Debouncing */ 4131 uint32_t :18; /**< bit: 14..31 Reserved */ 4132 } bit; /**< Structure used for bit access */ 4133 uint32_t reg; /**< Type used for register access */ 4134 } PIO_SCDR_Type; 4135 #endif 4136 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4137 4138 #define PIO_SCDR_OFFSET (0x8C) /**< (PIO_SCDR) Slow Clock Divider Debouncing Register Offset */ 4139 4140 #define PIO_SCDR_DIV_Pos 0 /**< (PIO_SCDR) Slow Clock Divider Selection for Debouncing Position */ 4141 #define PIO_SCDR_DIV_Msk (_U_(0x3FFF) << PIO_SCDR_DIV_Pos) /**< (PIO_SCDR) Slow Clock Divider Selection for Debouncing Mask */ 4142 #define PIO_SCDR_DIV(value) (PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)) 4143 #define PIO_SCDR_MASK _U_(0x3FFF) /**< \deprecated (PIO_SCDR) Register MASK (Use PIO_SCDR_Msk instead) */ 4144 #define PIO_SCDR_Msk _U_(0x3FFF) /**< (PIO_SCDR) Register Mask */ 4145 4146 4147 /* -------- PIO_PPDDR : (PIO Offset: 0x90) (/W 32) Pad Pull-down Disable Register -------- */ 4148 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4149 #if COMPONENT_TYPEDEF_STYLE == 'N' 4150 typedef union { 4151 struct { 4152 uint32_t P0:1; /**< bit: 0 Pull-Down Disable */ 4153 uint32_t P1:1; /**< bit: 1 Pull-Down Disable */ 4154 uint32_t P2:1; /**< bit: 2 Pull-Down Disable */ 4155 uint32_t P3:1; /**< bit: 3 Pull-Down Disable */ 4156 uint32_t P4:1; /**< bit: 4 Pull-Down Disable */ 4157 uint32_t P5:1; /**< bit: 5 Pull-Down Disable */ 4158 uint32_t P6:1; /**< bit: 6 Pull-Down Disable */ 4159 uint32_t P7:1; /**< bit: 7 Pull-Down Disable */ 4160 uint32_t P8:1; /**< bit: 8 Pull-Down Disable */ 4161 uint32_t P9:1; /**< bit: 9 Pull-Down Disable */ 4162 uint32_t P10:1; /**< bit: 10 Pull-Down Disable */ 4163 uint32_t P11:1; /**< bit: 11 Pull-Down Disable */ 4164 uint32_t P12:1; /**< bit: 12 Pull-Down Disable */ 4165 uint32_t P13:1; /**< bit: 13 Pull-Down Disable */ 4166 uint32_t P14:1; /**< bit: 14 Pull-Down Disable */ 4167 uint32_t P15:1; /**< bit: 15 Pull-Down Disable */ 4168 uint32_t P16:1; /**< bit: 16 Pull-Down Disable */ 4169 uint32_t P17:1; /**< bit: 17 Pull-Down Disable */ 4170 uint32_t P18:1; /**< bit: 18 Pull-Down Disable */ 4171 uint32_t P19:1; /**< bit: 19 Pull-Down Disable */ 4172 uint32_t P20:1; /**< bit: 20 Pull-Down Disable */ 4173 uint32_t P21:1; /**< bit: 21 Pull-Down Disable */ 4174 uint32_t P22:1; /**< bit: 22 Pull-Down Disable */ 4175 uint32_t P23:1; /**< bit: 23 Pull-Down Disable */ 4176 uint32_t P24:1; /**< bit: 24 Pull-Down Disable */ 4177 uint32_t P25:1; /**< bit: 25 Pull-Down Disable */ 4178 uint32_t P26:1; /**< bit: 26 Pull-Down Disable */ 4179 uint32_t P27:1; /**< bit: 27 Pull-Down Disable */ 4180 uint32_t P28:1; /**< bit: 28 Pull-Down Disable */ 4181 uint32_t P29:1; /**< bit: 29 Pull-Down Disable */ 4182 uint32_t P30:1; /**< bit: 30 Pull-Down Disable */ 4183 uint32_t P31:1; /**< bit: 31 Pull-Down Disable */ 4184 } bit; /**< Structure used for bit access */ 4185 struct { 4186 uint32_t P:32; /**< bit: 0..31 Pull-Down Disable */ 4187 } vec; /**< Structure used for vec access */ 4188 uint32_t reg; /**< Type used for register access */ 4189 } PIO_PPDDR_Type; 4190 #endif 4191 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4192 4193 #define PIO_PPDDR_OFFSET (0x90) /**< (PIO_PPDDR) Pad Pull-down Disable Register Offset */ 4194 4195 #define PIO_PPDDR_P0_Pos 0 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4196 #define PIO_PPDDR_P0_Msk (_U_(0x1) << PIO_PPDDR_P0_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4197 #define PIO_PPDDR_P0 PIO_PPDDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P0_Msk instead */ 4198 #define PIO_PPDDR_P1_Pos 1 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4199 #define PIO_PPDDR_P1_Msk (_U_(0x1) << PIO_PPDDR_P1_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4200 #define PIO_PPDDR_P1 PIO_PPDDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P1_Msk instead */ 4201 #define PIO_PPDDR_P2_Pos 2 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4202 #define PIO_PPDDR_P2_Msk (_U_(0x1) << PIO_PPDDR_P2_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4203 #define PIO_PPDDR_P2 PIO_PPDDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P2_Msk instead */ 4204 #define PIO_PPDDR_P3_Pos 3 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4205 #define PIO_PPDDR_P3_Msk (_U_(0x1) << PIO_PPDDR_P3_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4206 #define PIO_PPDDR_P3 PIO_PPDDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P3_Msk instead */ 4207 #define PIO_PPDDR_P4_Pos 4 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4208 #define PIO_PPDDR_P4_Msk (_U_(0x1) << PIO_PPDDR_P4_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4209 #define PIO_PPDDR_P4 PIO_PPDDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P4_Msk instead */ 4210 #define PIO_PPDDR_P5_Pos 5 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4211 #define PIO_PPDDR_P5_Msk (_U_(0x1) << PIO_PPDDR_P5_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4212 #define PIO_PPDDR_P5 PIO_PPDDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P5_Msk instead */ 4213 #define PIO_PPDDR_P6_Pos 6 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4214 #define PIO_PPDDR_P6_Msk (_U_(0x1) << PIO_PPDDR_P6_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4215 #define PIO_PPDDR_P6 PIO_PPDDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P6_Msk instead */ 4216 #define PIO_PPDDR_P7_Pos 7 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4217 #define PIO_PPDDR_P7_Msk (_U_(0x1) << PIO_PPDDR_P7_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4218 #define PIO_PPDDR_P7 PIO_PPDDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P7_Msk instead */ 4219 #define PIO_PPDDR_P8_Pos 8 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4220 #define PIO_PPDDR_P8_Msk (_U_(0x1) << PIO_PPDDR_P8_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4221 #define PIO_PPDDR_P8 PIO_PPDDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P8_Msk instead */ 4222 #define PIO_PPDDR_P9_Pos 9 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4223 #define PIO_PPDDR_P9_Msk (_U_(0x1) << PIO_PPDDR_P9_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4224 #define PIO_PPDDR_P9 PIO_PPDDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P9_Msk instead */ 4225 #define PIO_PPDDR_P10_Pos 10 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4226 #define PIO_PPDDR_P10_Msk (_U_(0x1) << PIO_PPDDR_P10_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4227 #define PIO_PPDDR_P10 PIO_PPDDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P10_Msk instead */ 4228 #define PIO_PPDDR_P11_Pos 11 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4229 #define PIO_PPDDR_P11_Msk (_U_(0x1) << PIO_PPDDR_P11_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4230 #define PIO_PPDDR_P11 PIO_PPDDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P11_Msk instead */ 4231 #define PIO_PPDDR_P12_Pos 12 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4232 #define PIO_PPDDR_P12_Msk (_U_(0x1) << PIO_PPDDR_P12_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4233 #define PIO_PPDDR_P12 PIO_PPDDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P12_Msk instead */ 4234 #define PIO_PPDDR_P13_Pos 13 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4235 #define PIO_PPDDR_P13_Msk (_U_(0x1) << PIO_PPDDR_P13_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4236 #define PIO_PPDDR_P13 PIO_PPDDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P13_Msk instead */ 4237 #define PIO_PPDDR_P14_Pos 14 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4238 #define PIO_PPDDR_P14_Msk (_U_(0x1) << PIO_PPDDR_P14_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4239 #define PIO_PPDDR_P14 PIO_PPDDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P14_Msk instead */ 4240 #define PIO_PPDDR_P15_Pos 15 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4241 #define PIO_PPDDR_P15_Msk (_U_(0x1) << PIO_PPDDR_P15_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4242 #define PIO_PPDDR_P15 PIO_PPDDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P15_Msk instead */ 4243 #define PIO_PPDDR_P16_Pos 16 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4244 #define PIO_PPDDR_P16_Msk (_U_(0x1) << PIO_PPDDR_P16_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4245 #define PIO_PPDDR_P16 PIO_PPDDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P16_Msk instead */ 4246 #define PIO_PPDDR_P17_Pos 17 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4247 #define PIO_PPDDR_P17_Msk (_U_(0x1) << PIO_PPDDR_P17_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4248 #define PIO_PPDDR_P17 PIO_PPDDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P17_Msk instead */ 4249 #define PIO_PPDDR_P18_Pos 18 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4250 #define PIO_PPDDR_P18_Msk (_U_(0x1) << PIO_PPDDR_P18_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4251 #define PIO_PPDDR_P18 PIO_PPDDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P18_Msk instead */ 4252 #define PIO_PPDDR_P19_Pos 19 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4253 #define PIO_PPDDR_P19_Msk (_U_(0x1) << PIO_PPDDR_P19_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4254 #define PIO_PPDDR_P19 PIO_PPDDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P19_Msk instead */ 4255 #define PIO_PPDDR_P20_Pos 20 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4256 #define PIO_PPDDR_P20_Msk (_U_(0x1) << PIO_PPDDR_P20_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4257 #define PIO_PPDDR_P20 PIO_PPDDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P20_Msk instead */ 4258 #define PIO_PPDDR_P21_Pos 21 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4259 #define PIO_PPDDR_P21_Msk (_U_(0x1) << PIO_PPDDR_P21_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4260 #define PIO_PPDDR_P21 PIO_PPDDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P21_Msk instead */ 4261 #define PIO_PPDDR_P22_Pos 22 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4262 #define PIO_PPDDR_P22_Msk (_U_(0x1) << PIO_PPDDR_P22_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4263 #define PIO_PPDDR_P22 PIO_PPDDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P22_Msk instead */ 4264 #define PIO_PPDDR_P23_Pos 23 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4265 #define PIO_PPDDR_P23_Msk (_U_(0x1) << PIO_PPDDR_P23_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4266 #define PIO_PPDDR_P23 PIO_PPDDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P23_Msk instead */ 4267 #define PIO_PPDDR_P24_Pos 24 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4268 #define PIO_PPDDR_P24_Msk (_U_(0x1) << PIO_PPDDR_P24_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4269 #define PIO_PPDDR_P24 PIO_PPDDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P24_Msk instead */ 4270 #define PIO_PPDDR_P25_Pos 25 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4271 #define PIO_PPDDR_P25_Msk (_U_(0x1) << PIO_PPDDR_P25_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4272 #define PIO_PPDDR_P25 PIO_PPDDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P25_Msk instead */ 4273 #define PIO_PPDDR_P26_Pos 26 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4274 #define PIO_PPDDR_P26_Msk (_U_(0x1) << PIO_PPDDR_P26_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4275 #define PIO_PPDDR_P26 PIO_PPDDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P26_Msk instead */ 4276 #define PIO_PPDDR_P27_Pos 27 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4277 #define PIO_PPDDR_P27_Msk (_U_(0x1) << PIO_PPDDR_P27_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4278 #define PIO_PPDDR_P27 PIO_PPDDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P27_Msk instead */ 4279 #define PIO_PPDDR_P28_Pos 28 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4280 #define PIO_PPDDR_P28_Msk (_U_(0x1) << PIO_PPDDR_P28_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4281 #define PIO_PPDDR_P28 PIO_PPDDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P28_Msk instead */ 4282 #define PIO_PPDDR_P29_Pos 29 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4283 #define PIO_PPDDR_P29_Msk (_U_(0x1) << PIO_PPDDR_P29_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4284 #define PIO_PPDDR_P29 PIO_PPDDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P29_Msk instead */ 4285 #define PIO_PPDDR_P30_Pos 30 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4286 #define PIO_PPDDR_P30_Msk (_U_(0x1) << PIO_PPDDR_P30_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4287 #define PIO_PPDDR_P30 PIO_PPDDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P30_Msk instead */ 4288 #define PIO_PPDDR_P31_Pos 31 /**< (PIO_PPDDR) Pull-Down Disable Position */ 4289 #define PIO_PPDDR_P31_Msk (_U_(0x1) << PIO_PPDDR_P31_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ 4290 #define PIO_PPDDR_P31 PIO_PPDDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P31_Msk instead */ 4291 #define PIO_PPDDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PPDDR) Register MASK (Use PIO_PPDDR_Msk instead) */ 4292 #define PIO_PPDDR_Msk _U_(0xFFFFFFFF) /**< (PIO_PPDDR) Register Mask */ 4293 4294 #define PIO_PPDDR_P_Pos 0 /**< (PIO_PPDDR Position) Pull-Down Disable */ 4295 #define PIO_PPDDR_P_Msk (_U_(0xFFFFFFFF) << PIO_PPDDR_P_Pos) /**< (PIO_PPDDR Mask) P */ 4296 #define PIO_PPDDR_P(value) (PIO_PPDDR_P_Msk & ((value) << PIO_PPDDR_P_Pos)) 4297 4298 /* -------- PIO_PPDER : (PIO Offset: 0x94) (/W 32) Pad Pull-down Enable Register -------- */ 4299 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4300 #if COMPONENT_TYPEDEF_STYLE == 'N' 4301 typedef union { 4302 struct { 4303 uint32_t P0:1; /**< bit: 0 Pull-Down Enable */ 4304 uint32_t P1:1; /**< bit: 1 Pull-Down Enable */ 4305 uint32_t P2:1; /**< bit: 2 Pull-Down Enable */ 4306 uint32_t P3:1; /**< bit: 3 Pull-Down Enable */ 4307 uint32_t P4:1; /**< bit: 4 Pull-Down Enable */ 4308 uint32_t P5:1; /**< bit: 5 Pull-Down Enable */ 4309 uint32_t P6:1; /**< bit: 6 Pull-Down Enable */ 4310 uint32_t P7:1; /**< bit: 7 Pull-Down Enable */ 4311 uint32_t P8:1; /**< bit: 8 Pull-Down Enable */ 4312 uint32_t P9:1; /**< bit: 9 Pull-Down Enable */ 4313 uint32_t P10:1; /**< bit: 10 Pull-Down Enable */ 4314 uint32_t P11:1; /**< bit: 11 Pull-Down Enable */ 4315 uint32_t P12:1; /**< bit: 12 Pull-Down Enable */ 4316 uint32_t P13:1; /**< bit: 13 Pull-Down Enable */ 4317 uint32_t P14:1; /**< bit: 14 Pull-Down Enable */ 4318 uint32_t P15:1; /**< bit: 15 Pull-Down Enable */ 4319 uint32_t P16:1; /**< bit: 16 Pull-Down Enable */ 4320 uint32_t P17:1; /**< bit: 17 Pull-Down Enable */ 4321 uint32_t P18:1; /**< bit: 18 Pull-Down Enable */ 4322 uint32_t P19:1; /**< bit: 19 Pull-Down Enable */ 4323 uint32_t P20:1; /**< bit: 20 Pull-Down Enable */ 4324 uint32_t P21:1; /**< bit: 21 Pull-Down Enable */ 4325 uint32_t P22:1; /**< bit: 22 Pull-Down Enable */ 4326 uint32_t P23:1; /**< bit: 23 Pull-Down Enable */ 4327 uint32_t P24:1; /**< bit: 24 Pull-Down Enable */ 4328 uint32_t P25:1; /**< bit: 25 Pull-Down Enable */ 4329 uint32_t P26:1; /**< bit: 26 Pull-Down Enable */ 4330 uint32_t P27:1; /**< bit: 27 Pull-Down Enable */ 4331 uint32_t P28:1; /**< bit: 28 Pull-Down Enable */ 4332 uint32_t P29:1; /**< bit: 29 Pull-Down Enable */ 4333 uint32_t P30:1; /**< bit: 30 Pull-Down Enable */ 4334 uint32_t P31:1; /**< bit: 31 Pull-Down Enable */ 4335 } bit; /**< Structure used for bit access */ 4336 struct { 4337 uint32_t P:32; /**< bit: 0..31 Pull-Down Enable */ 4338 } vec; /**< Structure used for vec access */ 4339 uint32_t reg; /**< Type used for register access */ 4340 } PIO_PPDER_Type; 4341 #endif 4342 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4343 4344 #define PIO_PPDER_OFFSET (0x94) /**< (PIO_PPDER) Pad Pull-down Enable Register Offset */ 4345 4346 #define PIO_PPDER_P0_Pos 0 /**< (PIO_PPDER) Pull-Down Enable Position */ 4347 #define PIO_PPDER_P0_Msk (_U_(0x1) << PIO_PPDER_P0_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4348 #define PIO_PPDER_P0 PIO_PPDER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P0_Msk instead */ 4349 #define PIO_PPDER_P1_Pos 1 /**< (PIO_PPDER) Pull-Down Enable Position */ 4350 #define PIO_PPDER_P1_Msk (_U_(0x1) << PIO_PPDER_P1_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4351 #define PIO_PPDER_P1 PIO_PPDER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P1_Msk instead */ 4352 #define PIO_PPDER_P2_Pos 2 /**< (PIO_PPDER) Pull-Down Enable Position */ 4353 #define PIO_PPDER_P2_Msk (_U_(0x1) << PIO_PPDER_P2_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4354 #define PIO_PPDER_P2 PIO_PPDER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P2_Msk instead */ 4355 #define PIO_PPDER_P3_Pos 3 /**< (PIO_PPDER) Pull-Down Enable Position */ 4356 #define PIO_PPDER_P3_Msk (_U_(0x1) << PIO_PPDER_P3_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4357 #define PIO_PPDER_P3 PIO_PPDER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P3_Msk instead */ 4358 #define PIO_PPDER_P4_Pos 4 /**< (PIO_PPDER) Pull-Down Enable Position */ 4359 #define PIO_PPDER_P4_Msk (_U_(0x1) << PIO_PPDER_P4_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4360 #define PIO_PPDER_P4 PIO_PPDER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P4_Msk instead */ 4361 #define PIO_PPDER_P5_Pos 5 /**< (PIO_PPDER) Pull-Down Enable Position */ 4362 #define PIO_PPDER_P5_Msk (_U_(0x1) << PIO_PPDER_P5_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4363 #define PIO_PPDER_P5 PIO_PPDER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P5_Msk instead */ 4364 #define PIO_PPDER_P6_Pos 6 /**< (PIO_PPDER) Pull-Down Enable Position */ 4365 #define PIO_PPDER_P6_Msk (_U_(0x1) << PIO_PPDER_P6_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4366 #define PIO_PPDER_P6 PIO_PPDER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P6_Msk instead */ 4367 #define PIO_PPDER_P7_Pos 7 /**< (PIO_PPDER) Pull-Down Enable Position */ 4368 #define PIO_PPDER_P7_Msk (_U_(0x1) << PIO_PPDER_P7_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4369 #define PIO_PPDER_P7 PIO_PPDER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P7_Msk instead */ 4370 #define PIO_PPDER_P8_Pos 8 /**< (PIO_PPDER) Pull-Down Enable Position */ 4371 #define PIO_PPDER_P8_Msk (_U_(0x1) << PIO_PPDER_P8_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4372 #define PIO_PPDER_P8 PIO_PPDER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P8_Msk instead */ 4373 #define PIO_PPDER_P9_Pos 9 /**< (PIO_PPDER) Pull-Down Enable Position */ 4374 #define PIO_PPDER_P9_Msk (_U_(0x1) << PIO_PPDER_P9_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4375 #define PIO_PPDER_P9 PIO_PPDER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P9_Msk instead */ 4376 #define PIO_PPDER_P10_Pos 10 /**< (PIO_PPDER) Pull-Down Enable Position */ 4377 #define PIO_PPDER_P10_Msk (_U_(0x1) << PIO_PPDER_P10_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4378 #define PIO_PPDER_P10 PIO_PPDER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P10_Msk instead */ 4379 #define PIO_PPDER_P11_Pos 11 /**< (PIO_PPDER) Pull-Down Enable Position */ 4380 #define PIO_PPDER_P11_Msk (_U_(0x1) << PIO_PPDER_P11_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4381 #define PIO_PPDER_P11 PIO_PPDER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P11_Msk instead */ 4382 #define PIO_PPDER_P12_Pos 12 /**< (PIO_PPDER) Pull-Down Enable Position */ 4383 #define PIO_PPDER_P12_Msk (_U_(0x1) << PIO_PPDER_P12_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4384 #define PIO_PPDER_P12 PIO_PPDER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P12_Msk instead */ 4385 #define PIO_PPDER_P13_Pos 13 /**< (PIO_PPDER) Pull-Down Enable Position */ 4386 #define PIO_PPDER_P13_Msk (_U_(0x1) << PIO_PPDER_P13_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4387 #define PIO_PPDER_P13 PIO_PPDER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P13_Msk instead */ 4388 #define PIO_PPDER_P14_Pos 14 /**< (PIO_PPDER) Pull-Down Enable Position */ 4389 #define PIO_PPDER_P14_Msk (_U_(0x1) << PIO_PPDER_P14_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4390 #define PIO_PPDER_P14 PIO_PPDER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P14_Msk instead */ 4391 #define PIO_PPDER_P15_Pos 15 /**< (PIO_PPDER) Pull-Down Enable Position */ 4392 #define PIO_PPDER_P15_Msk (_U_(0x1) << PIO_PPDER_P15_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4393 #define PIO_PPDER_P15 PIO_PPDER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P15_Msk instead */ 4394 #define PIO_PPDER_P16_Pos 16 /**< (PIO_PPDER) Pull-Down Enable Position */ 4395 #define PIO_PPDER_P16_Msk (_U_(0x1) << PIO_PPDER_P16_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4396 #define PIO_PPDER_P16 PIO_PPDER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P16_Msk instead */ 4397 #define PIO_PPDER_P17_Pos 17 /**< (PIO_PPDER) Pull-Down Enable Position */ 4398 #define PIO_PPDER_P17_Msk (_U_(0x1) << PIO_PPDER_P17_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4399 #define PIO_PPDER_P17 PIO_PPDER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P17_Msk instead */ 4400 #define PIO_PPDER_P18_Pos 18 /**< (PIO_PPDER) Pull-Down Enable Position */ 4401 #define PIO_PPDER_P18_Msk (_U_(0x1) << PIO_PPDER_P18_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4402 #define PIO_PPDER_P18 PIO_PPDER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P18_Msk instead */ 4403 #define PIO_PPDER_P19_Pos 19 /**< (PIO_PPDER) Pull-Down Enable Position */ 4404 #define PIO_PPDER_P19_Msk (_U_(0x1) << PIO_PPDER_P19_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4405 #define PIO_PPDER_P19 PIO_PPDER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P19_Msk instead */ 4406 #define PIO_PPDER_P20_Pos 20 /**< (PIO_PPDER) Pull-Down Enable Position */ 4407 #define PIO_PPDER_P20_Msk (_U_(0x1) << PIO_PPDER_P20_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4408 #define PIO_PPDER_P20 PIO_PPDER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P20_Msk instead */ 4409 #define PIO_PPDER_P21_Pos 21 /**< (PIO_PPDER) Pull-Down Enable Position */ 4410 #define PIO_PPDER_P21_Msk (_U_(0x1) << PIO_PPDER_P21_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4411 #define PIO_PPDER_P21 PIO_PPDER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P21_Msk instead */ 4412 #define PIO_PPDER_P22_Pos 22 /**< (PIO_PPDER) Pull-Down Enable Position */ 4413 #define PIO_PPDER_P22_Msk (_U_(0x1) << PIO_PPDER_P22_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4414 #define PIO_PPDER_P22 PIO_PPDER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P22_Msk instead */ 4415 #define PIO_PPDER_P23_Pos 23 /**< (PIO_PPDER) Pull-Down Enable Position */ 4416 #define PIO_PPDER_P23_Msk (_U_(0x1) << PIO_PPDER_P23_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4417 #define PIO_PPDER_P23 PIO_PPDER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P23_Msk instead */ 4418 #define PIO_PPDER_P24_Pos 24 /**< (PIO_PPDER) Pull-Down Enable Position */ 4419 #define PIO_PPDER_P24_Msk (_U_(0x1) << PIO_PPDER_P24_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4420 #define PIO_PPDER_P24 PIO_PPDER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P24_Msk instead */ 4421 #define PIO_PPDER_P25_Pos 25 /**< (PIO_PPDER) Pull-Down Enable Position */ 4422 #define PIO_PPDER_P25_Msk (_U_(0x1) << PIO_PPDER_P25_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4423 #define PIO_PPDER_P25 PIO_PPDER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P25_Msk instead */ 4424 #define PIO_PPDER_P26_Pos 26 /**< (PIO_PPDER) Pull-Down Enable Position */ 4425 #define PIO_PPDER_P26_Msk (_U_(0x1) << PIO_PPDER_P26_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4426 #define PIO_PPDER_P26 PIO_PPDER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P26_Msk instead */ 4427 #define PIO_PPDER_P27_Pos 27 /**< (PIO_PPDER) Pull-Down Enable Position */ 4428 #define PIO_PPDER_P27_Msk (_U_(0x1) << PIO_PPDER_P27_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4429 #define PIO_PPDER_P27 PIO_PPDER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P27_Msk instead */ 4430 #define PIO_PPDER_P28_Pos 28 /**< (PIO_PPDER) Pull-Down Enable Position */ 4431 #define PIO_PPDER_P28_Msk (_U_(0x1) << PIO_PPDER_P28_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4432 #define PIO_PPDER_P28 PIO_PPDER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P28_Msk instead */ 4433 #define PIO_PPDER_P29_Pos 29 /**< (PIO_PPDER) Pull-Down Enable Position */ 4434 #define PIO_PPDER_P29_Msk (_U_(0x1) << PIO_PPDER_P29_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4435 #define PIO_PPDER_P29 PIO_PPDER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P29_Msk instead */ 4436 #define PIO_PPDER_P30_Pos 30 /**< (PIO_PPDER) Pull-Down Enable Position */ 4437 #define PIO_PPDER_P30_Msk (_U_(0x1) << PIO_PPDER_P30_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4438 #define PIO_PPDER_P30 PIO_PPDER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P30_Msk instead */ 4439 #define PIO_PPDER_P31_Pos 31 /**< (PIO_PPDER) Pull-Down Enable Position */ 4440 #define PIO_PPDER_P31_Msk (_U_(0x1) << PIO_PPDER_P31_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ 4441 #define PIO_PPDER_P31 PIO_PPDER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P31_Msk instead */ 4442 #define PIO_PPDER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PPDER) Register MASK (Use PIO_PPDER_Msk instead) */ 4443 #define PIO_PPDER_Msk _U_(0xFFFFFFFF) /**< (PIO_PPDER) Register Mask */ 4444 4445 #define PIO_PPDER_P_Pos 0 /**< (PIO_PPDER Position) Pull-Down Enable */ 4446 #define PIO_PPDER_P_Msk (_U_(0xFFFFFFFF) << PIO_PPDER_P_Pos) /**< (PIO_PPDER Mask) P */ 4447 #define PIO_PPDER_P(value) (PIO_PPDER_P_Msk & ((value) << PIO_PPDER_P_Pos)) 4448 4449 /* -------- PIO_PPDSR : (PIO Offset: 0x98) (R/ 32) Pad Pull-down Status Register -------- */ 4450 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4451 #if COMPONENT_TYPEDEF_STYLE == 'N' 4452 typedef union { 4453 struct { 4454 uint32_t P0:1; /**< bit: 0 Pull-Down Status */ 4455 uint32_t P1:1; /**< bit: 1 Pull-Down Status */ 4456 uint32_t P2:1; /**< bit: 2 Pull-Down Status */ 4457 uint32_t P3:1; /**< bit: 3 Pull-Down Status */ 4458 uint32_t P4:1; /**< bit: 4 Pull-Down Status */ 4459 uint32_t P5:1; /**< bit: 5 Pull-Down Status */ 4460 uint32_t P6:1; /**< bit: 6 Pull-Down Status */ 4461 uint32_t P7:1; /**< bit: 7 Pull-Down Status */ 4462 uint32_t P8:1; /**< bit: 8 Pull-Down Status */ 4463 uint32_t P9:1; /**< bit: 9 Pull-Down Status */ 4464 uint32_t P10:1; /**< bit: 10 Pull-Down Status */ 4465 uint32_t P11:1; /**< bit: 11 Pull-Down Status */ 4466 uint32_t P12:1; /**< bit: 12 Pull-Down Status */ 4467 uint32_t P13:1; /**< bit: 13 Pull-Down Status */ 4468 uint32_t P14:1; /**< bit: 14 Pull-Down Status */ 4469 uint32_t P15:1; /**< bit: 15 Pull-Down Status */ 4470 uint32_t P16:1; /**< bit: 16 Pull-Down Status */ 4471 uint32_t P17:1; /**< bit: 17 Pull-Down Status */ 4472 uint32_t P18:1; /**< bit: 18 Pull-Down Status */ 4473 uint32_t P19:1; /**< bit: 19 Pull-Down Status */ 4474 uint32_t P20:1; /**< bit: 20 Pull-Down Status */ 4475 uint32_t P21:1; /**< bit: 21 Pull-Down Status */ 4476 uint32_t P22:1; /**< bit: 22 Pull-Down Status */ 4477 uint32_t P23:1; /**< bit: 23 Pull-Down Status */ 4478 uint32_t P24:1; /**< bit: 24 Pull-Down Status */ 4479 uint32_t P25:1; /**< bit: 25 Pull-Down Status */ 4480 uint32_t P26:1; /**< bit: 26 Pull-Down Status */ 4481 uint32_t P27:1; /**< bit: 27 Pull-Down Status */ 4482 uint32_t P28:1; /**< bit: 28 Pull-Down Status */ 4483 uint32_t P29:1; /**< bit: 29 Pull-Down Status */ 4484 uint32_t P30:1; /**< bit: 30 Pull-Down Status */ 4485 uint32_t P31:1; /**< bit: 31 Pull-Down Status */ 4486 } bit; /**< Structure used for bit access */ 4487 struct { 4488 uint32_t P:32; /**< bit: 0..31 Pull-Down Status */ 4489 } vec; /**< Structure used for vec access */ 4490 uint32_t reg; /**< Type used for register access */ 4491 } PIO_PPDSR_Type; 4492 #endif 4493 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4494 4495 #define PIO_PPDSR_OFFSET (0x98) /**< (PIO_PPDSR) Pad Pull-down Status Register Offset */ 4496 4497 #define PIO_PPDSR_P0_Pos 0 /**< (PIO_PPDSR) Pull-Down Status Position */ 4498 #define PIO_PPDSR_P0_Msk (_U_(0x1) << PIO_PPDSR_P0_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4499 #define PIO_PPDSR_P0 PIO_PPDSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P0_Msk instead */ 4500 #define PIO_PPDSR_P1_Pos 1 /**< (PIO_PPDSR) Pull-Down Status Position */ 4501 #define PIO_PPDSR_P1_Msk (_U_(0x1) << PIO_PPDSR_P1_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4502 #define PIO_PPDSR_P1 PIO_PPDSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P1_Msk instead */ 4503 #define PIO_PPDSR_P2_Pos 2 /**< (PIO_PPDSR) Pull-Down Status Position */ 4504 #define PIO_PPDSR_P2_Msk (_U_(0x1) << PIO_PPDSR_P2_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4505 #define PIO_PPDSR_P2 PIO_PPDSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P2_Msk instead */ 4506 #define PIO_PPDSR_P3_Pos 3 /**< (PIO_PPDSR) Pull-Down Status Position */ 4507 #define PIO_PPDSR_P3_Msk (_U_(0x1) << PIO_PPDSR_P3_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4508 #define PIO_PPDSR_P3 PIO_PPDSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P3_Msk instead */ 4509 #define PIO_PPDSR_P4_Pos 4 /**< (PIO_PPDSR) Pull-Down Status Position */ 4510 #define PIO_PPDSR_P4_Msk (_U_(0x1) << PIO_PPDSR_P4_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4511 #define PIO_PPDSR_P4 PIO_PPDSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P4_Msk instead */ 4512 #define PIO_PPDSR_P5_Pos 5 /**< (PIO_PPDSR) Pull-Down Status Position */ 4513 #define PIO_PPDSR_P5_Msk (_U_(0x1) << PIO_PPDSR_P5_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4514 #define PIO_PPDSR_P5 PIO_PPDSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P5_Msk instead */ 4515 #define PIO_PPDSR_P6_Pos 6 /**< (PIO_PPDSR) Pull-Down Status Position */ 4516 #define PIO_PPDSR_P6_Msk (_U_(0x1) << PIO_PPDSR_P6_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4517 #define PIO_PPDSR_P6 PIO_PPDSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P6_Msk instead */ 4518 #define PIO_PPDSR_P7_Pos 7 /**< (PIO_PPDSR) Pull-Down Status Position */ 4519 #define PIO_PPDSR_P7_Msk (_U_(0x1) << PIO_PPDSR_P7_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4520 #define PIO_PPDSR_P7 PIO_PPDSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P7_Msk instead */ 4521 #define PIO_PPDSR_P8_Pos 8 /**< (PIO_PPDSR) Pull-Down Status Position */ 4522 #define PIO_PPDSR_P8_Msk (_U_(0x1) << PIO_PPDSR_P8_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4523 #define PIO_PPDSR_P8 PIO_PPDSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P8_Msk instead */ 4524 #define PIO_PPDSR_P9_Pos 9 /**< (PIO_PPDSR) Pull-Down Status Position */ 4525 #define PIO_PPDSR_P9_Msk (_U_(0x1) << PIO_PPDSR_P9_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4526 #define PIO_PPDSR_P9 PIO_PPDSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P9_Msk instead */ 4527 #define PIO_PPDSR_P10_Pos 10 /**< (PIO_PPDSR) Pull-Down Status Position */ 4528 #define PIO_PPDSR_P10_Msk (_U_(0x1) << PIO_PPDSR_P10_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4529 #define PIO_PPDSR_P10 PIO_PPDSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P10_Msk instead */ 4530 #define PIO_PPDSR_P11_Pos 11 /**< (PIO_PPDSR) Pull-Down Status Position */ 4531 #define PIO_PPDSR_P11_Msk (_U_(0x1) << PIO_PPDSR_P11_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4532 #define PIO_PPDSR_P11 PIO_PPDSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P11_Msk instead */ 4533 #define PIO_PPDSR_P12_Pos 12 /**< (PIO_PPDSR) Pull-Down Status Position */ 4534 #define PIO_PPDSR_P12_Msk (_U_(0x1) << PIO_PPDSR_P12_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4535 #define PIO_PPDSR_P12 PIO_PPDSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P12_Msk instead */ 4536 #define PIO_PPDSR_P13_Pos 13 /**< (PIO_PPDSR) Pull-Down Status Position */ 4537 #define PIO_PPDSR_P13_Msk (_U_(0x1) << PIO_PPDSR_P13_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4538 #define PIO_PPDSR_P13 PIO_PPDSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P13_Msk instead */ 4539 #define PIO_PPDSR_P14_Pos 14 /**< (PIO_PPDSR) Pull-Down Status Position */ 4540 #define PIO_PPDSR_P14_Msk (_U_(0x1) << PIO_PPDSR_P14_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4541 #define PIO_PPDSR_P14 PIO_PPDSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P14_Msk instead */ 4542 #define PIO_PPDSR_P15_Pos 15 /**< (PIO_PPDSR) Pull-Down Status Position */ 4543 #define PIO_PPDSR_P15_Msk (_U_(0x1) << PIO_PPDSR_P15_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4544 #define PIO_PPDSR_P15 PIO_PPDSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P15_Msk instead */ 4545 #define PIO_PPDSR_P16_Pos 16 /**< (PIO_PPDSR) Pull-Down Status Position */ 4546 #define PIO_PPDSR_P16_Msk (_U_(0x1) << PIO_PPDSR_P16_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4547 #define PIO_PPDSR_P16 PIO_PPDSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P16_Msk instead */ 4548 #define PIO_PPDSR_P17_Pos 17 /**< (PIO_PPDSR) Pull-Down Status Position */ 4549 #define PIO_PPDSR_P17_Msk (_U_(0x1) << PIO_PPDSR_P17_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4550 #define PIO_PPDSR_P17 PIO_PPDSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P17_Msk instead */ 4551 #define PIO_PPDSR_P18_Pos 18 /**< (PIO_PPDSR) Pull-Down Status Position */ 4552 #define PIO_PPDSR_P18_Msk (_U_(0x1) << PIO_PPDSR_P18_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4553 #define PIO_PPDSR_P18 PIO_PPDSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P18_Msk instead */ 4554 #define PIO_PPDSR_P19_Pos 19 /**< (PIO_PPDSR) Pull-Down Status Position */ 4555 #define PIO_PPDSR_P19_Msk (_U_(0x1) << PIO_PPDSR_P19_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4556 #define PIO_PPDSR_P19 PIO_PPDSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P19_Msk instead */ 4557 #define PIO_PPDSR_P20_Pos 20 /**< (PIO_PPDSR) Pull-Down Status Position */ 4558 #define PIO_PPDSR_P20_Msk (_U_(0x1) << PIO_PPDSR_P20_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4559 #define PIO_PPDSR_P20 PIO_PPDSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P20_Msk instead */ 4560 #define PIO_PPDSR_P21_Pos 21 /**< (PIO_PPDSR) Pull-Down Status Position */ 4561 #define PIO_PPDSR_P21_Msk (_U_(0x1) << PIO_PPDSR_P21_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4562 #define PIO_PPDSR_P21 PIO_PPDSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P21_Msk instead */ 4563 #define PIO_PPDSR_P22_Pos 22 /**< (PIO_PPDSR) Pull-Down Status Position */ 4564 #define PIO_PPDSR_P22_Msk (_U_(0x1) << PIO_PPDSR_P22_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4565 #define PIO_PPDSR_P22 PIO_PPDSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P22_Msk instead */ 4566 #define PIO_PPDSR_P23_Pos 23 /**< (PIO_PPDSR) Pull-Down Status Position */ 4567 #define PIO_PPDSR_P23_Msk (_U_(0x1) << PIO_PPDSR_P23_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4568 #define PIO_PPDSR_P23 PIO_PPDSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P23_Msk instead */ 4569 #define PIO_PPDSR_P24_Pos 24 /**< (PIO_PPDSR) Pull-Down Status Position */ 4570 #define PIO_PPDSR_P24_Msk (_U_(0x1) << PIO_PPDSR_P24_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4571 #define PIO_PPDSR_P24 PIO_PPDSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P24_Msk instead */ 4572 #define PIO_PPDSR_P25_Pos 25 /**< (PIO_PPDSR) Pull-Down Status Position */ 4573 #define PIO_PPDSR_P25_Msk (_U_(0x1) << PIO_PPDSR_P25_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4574 #define PIO_PPDSR_P25 PIO_PPDSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P25_Msk instead */ 4575 #define PIO_PPDSR_P26_Pos 26 /**< (PIO_PPDSR) Pull-Down Status Position */ 4576 #define PIO_PPDSR_P26_Msk (_U_(0x1) << PIO_PPDSR_P26_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4577 #define PIO_PPDSR_P26 PIO_PPDSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P26_Msk instead */ 4578 #define PIO_PPDSR_P27_Pos 27 /**< (PIO_PPDSR) Pull-Down Status Position */ 4579 #define PIO_PPDSR_P27_Msk (_U_(0x1) << PIO_PPDSR_P27_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4580 #define PIO_PPDSR_P27 PIO_PPDSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P27_Msk instead */ 4581 #define PIO_PPDSR_P28_Pos 28 /**< (PIO_PPDSR) Pull-Down Status Position */ 4582 #define PIO_PPDSR_P28_Msk (_U_(0x1) << PIO_PPDSR_P28_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4583 #define PIO_PPDSR_P28 PIO_PPDSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P28_Msk instead */ 4584 #define PIO_PPDSR_P29_Pos 29 /**< (PIO_PPDSR) Pull-Down Status Position */ 4585 #define PIO_PPDSR_P29_Msk (_U_(0x1) << PIO_PPDSR_P29_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4586 #define PIO_PPDSR_P29 PIO_PPDSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P29_Msk instead */ 4587 #define PIO_PPDSR_P30_Pos 30 /**< (PIO_PPDSR) Pull-Down Status Position */ 4588 #define PIO_PPDSR_P30_Msk (_U_(0x1) << PIO_PPDSR_P30_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4589 #define PIO_PPDSR_P30 PIO_PPDSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P30_Msk instead */ 4590 #define PIO_PPDSR_P31_Pos 31 /**< (PIO_PPDSR) Pull-Down Status Position */ 4591 #define PIO_PPDSR_P31_Msk (_U_(0x1) << PIO_PPDSR_P31_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ 4592 #define PIO_PPDSR_P31 PIO_PPDSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P31_Msk instead */ 4593 #define PIO_PPDSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PPDSR) Register MASK (Use PIO_PPDSR_Msk instead) */ 4594 #define PIO_PPDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PPDSR) Register Mask */ 4595 4596 #define PIO_PPDSR_P_Pos 0 /**< (PIO_PPDSR Position) Pull-Down Status */ 4597 #define PIO_PPDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PPDSR_P_Pos) /**< (PIO_PPDSR Mask) P */ 4598 #define PIO_PPDSR_P(value) (PIO_PPDSR_P_Msk & ((value) << PIO_PPDSR_P_Pos)) 4599 4600 /* -------- PIO_OWER : (PIO Offset: 0xa0) (/W 32) Output Write Enable -------- */ 4601 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4602 #if COMPONENT_TYPEDEF_STYLE == 'N' 4603 typedef union { 4604 struct { 4605 uint32_t P0:1; /**< bit: 0 Output Write Enable */ 4606 uint32_t P1:1; /**< bit: 1 Output Write Enable */ 4607 uint32_t P2:1; /**< bit: 2 Output Write Enable */ 4608 uint32_t P3:1; /**< bit: 3 Output Write Enable */ 4609 uint32_t P4:1; /**< bit: 4 Output Write Enable */ 4610 uint32_t P5:1; /**< bit: 5 Output Write Enable */ 4611 uint32_t P6:1; /**< bit: 6 Output Write Enable */ 4612 uint32_t P7:1; /**< bit: 7 Output Write Enable */ 4613 uint32_t P8:1; /**< bit: 8 Output Write Enable */ 4614 uint32_t P9:1; /**< bit: 9 Output Write Enable */ 4615 uint32_t P10:1; /**< bit: 10 Output Write Enable */ 4616 uint32_t P11:1; /**< bit: 11 Output Write Enable */ 4617 uint32_t P12:1; /**< bit: 12 Output Write Enable */ 4618 uint32_t P13:1; /**< bit: 13 Output Write Enable */ 4619 uint32_t P14:1; /**< bit: 14 Output Write Enable */ 4620 uint32_t P15:1; /**< bit: 15 Output Write Enable */ 4621 uint32_t P16:1; /**< bit: 16 Output Write Enable */ 4622 uint32_t P17:1; /**< bit: 17 Output Write Enable */ 4623 uint32_t P18:1; /**< bit: 18 Output Write Enable */ 4624 uint32_t P19:1; /**< bit: 19 Output Write Enable */ 4625 uint32_t P20:1; /**< bit: 20 Output Write Enable */ 4626 uint32_t P21:1; /**< bit: 21 Output Write Enable */ 4627 uint32_t P22:1; /**< bit: 22 Output Write Enable */ 4628 uint32_t P23:1; /**< bit: 23 Output Write Enable */ 4629 uint32_t P24:1; /**< bit: 24 Output Write Enable */ 4630 uint32_t P25:1; /**< bit: 25 Output Write Enable */ 4631 uint32_t P26:1; /**< bit: 26 Output Write Enable */ 4632 uint32_t P27:1; /**< bit: 27 Output Write Enable */ 4633 uint32_t P28:1; /**< bit: 28 Output Write Enable */ 4634 uint32_t P29:1; /**< bit: 29 Output Write Enable */ 4635 uint32_t P30:1; /**< bit: 30 Output Write Enable */ 4636 uint32_t P31:1; /**< bit: 31 Output Write Enable */ 4637 } bit; /**< Structure used for bit access */ 4638 struct { 4639 uint32_t P:32; /**< bit: 0..31 Output Write Enable */ 4640 } vec; /**< Structure used for vec access */ 4641 uint32_t reg; /**< Type used for register access */ 4642 } PIO_OWER_Type; 4643 #endif 4644 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4645 4646 #define PIO_OWER_OFFSET (0xA0) /**< (PIO_OWER) Output Write Enable Offset */ 4647 4648 #define PIO_OWER_P0_Pos 0 /**< (PIO_OWER) Output Write Enable Position */ 4649 #define PIO_OWER_P0_Msk (_U_(0x1) << PIO_OWER_P0_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4650 #define PIO_OWER_P0 PIO_OWER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P0_Msk instead */ 4651 #define PIO_OWER_P1_Pos 1 /**< (PIO_OWER) Output Write Enable Position */ 4652 #define PIO_OWER_P1_Msk (_U_(0x1) << PIO_OWER_P1_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4653 #define PIO_OWER_P1 PIO_OWER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P1_Msk instead */ 4654 #define PIO_OWER_P2_Pos 2 /**< (PIO_OWER) Output Write Enable Position */ 4655 #define PIO_OWER_P2_Msk (_U_(0x1) << PIO_OWER_P2_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4656 #define PIO_OWER_P2 PIO_OWER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P2_Msk instead */ 4657 #define PIO_OWER_P3_Pos 3 /**< (PIO_OWER) Output Write Enable Position */ 4658 #define PIO_OWER_P3_Msk (_U_(0x1) << PIO_OWER_P3_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4659 #define PIO_OWER_P3 PIO_OWER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P3_Msk instead */ 4660 #define PIO_OWER_P4_Pos 4 /**< (PIO_OWER) Output Write Enable Position */ 4661 #define PIO_OWER_P4_Msk (_U_(0x1) << PIO_OWER_P4_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4662 #define PIO_OWER_P4 PIO_OWER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P4_Msk instead */ 4663 #define PIO_OWER_P5_Pos 5 /**< (PIO_OWER) Output Write Enable Position */ 4664 #define PIO_OWER_P5_Msk (_U_(0x1) << PIO_OWER_P5_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4665 #define PIO_OWER_P5 PIO_OWER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P5_Msk instead */ 4666 #define PIO_OWER_P6_Pos 6 /**< (PIO_OWER) Output Write Enable Position */ 4667 #define PIO_OWER_P6_Msk (_U_(0x1) << PIO_OWER_P6_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4668 #define PIO_OWER_P6 PIO_OWER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P6_Msk instead */ 4669 #define PIO_OWER_P7_Pos 7 /**< (PIO_OWER) Output Write Enable Position */ 4670 #define PIO_OWER_P7_Msk (_U_(0x1) << PIO_OWER_P7_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4671 #define PIO_OWER_P7 PIO_OWER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P7_Msk instead */ 4672 #define PIO_OWER_P8_Pos 8 /**< (PIO_OWER) Output Write Enable Position */ 4673 #define PIO_OWER_P8_Msk (_U_(0x1) << PIO_OWER_P8_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4674 #define PIO_OWER_P8 PIO_OWER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P8_Msk instead */ 4675 #define PIO_OWER_P9_Pos 9 /**< (PIO_OWER) Output Write Enable Position */ 4676 #define PIO_OWER_P9_Msk (_U_(0x1) << PIO_OWER_P9_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4677 #define PIO_OWER_P9 PIO_OWER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P9_Msk instead */ 4678 #define PIO_OWER_P10_Pos 10 /**< (PIO_OWER) Output Write Enable Position */ 4679 #define PIO_OWER_P10_Msk (_U_(0x1) << PIO_OWER_P10_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4680 #define PIO_OWER_P10 PIO_OWER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P10_Msk instead */ 4681 #define PIO_OWER_P11_Pos 11 /**< (PIO_OWER) Output Write Enable Position */ 4682 #define PIO_OWER_P11_Msk (_U_(0x1) << PIO_OWER_P11_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4683 #define PIO_OWER_P11 PIO_OWER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P11_Msk instead */ 4684 #define PIO_OWER_P12_Pos 12 /**< (PIO_OWER) Output Write Enable Position */ 4685 #define PIO_OWER_P12_Msk (_U_(0x1) << PIO_OWER_P12_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4686 #define PIO_OWER_P12 PIO_OWER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P12_Msk instead */ 4687 #define PIO_OWER_P13_Pos 13 /**< (PIO_OWER) Output Write Enable Position */ 4688 #define PIO_OWER_P13_Msk (_U_(0x1) << PIO_OWER_P13_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4689 #define PIO_OWER_P13 PIO_OWER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P13_Msk instead */ 4690 #define PIO_OWER_P14_Pos 14 /**< (PIO_OWER) Output Write Enable Position */ 4691 #define PIO_OWER_P14_Msk (_U_(0x1) << PIO_OWER_P14_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4692 #define PIO_OWER_P14 PIO_OWER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P14_Msk instead */ 4693 #define PIO_OWER_P15_Pos 15 /**< (PIO_OWER) Output Write Enable Position */ 4694 #define PIO_OWER_P15_Msk (_U_(0x1) << PIO_OWER_P15_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4695 #define PIO_OWER_P15 PIO_OWER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P15_Msk instead */ 4696 #define PIO_OWER_P16_Pos 16 /**< (PIO_OWER) Output Write Enable Position */ 4697 #define PIO_OWER_P16_Msk (_U_(0x1) << PIO_OWER_P16_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4698 #define PIO_OWER_P16 PIO_OWER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P16_Msk instead */ 4699 #define PIO_OWER_P17_Pos 17 /**< (PIO_OWER) Output Write Enable Position */ 4700 #define PIO_OWER_P17_Msk (_U_(0x1) << PIO_OWER_P17_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4701 #define PIO_OWER_P17 PIO_OWER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P17_Msk instead */ 4702 #define PIO_OWER_P18_Pos 18 /**< (PIO_OWER) Output Write Enable Position */ 4703 #define PIO_OWER_P18_Msk (_U_(0x1) << PIO_OWER_P18_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4704 #define PIO_OWER_P18 PIO_OWER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P18_Msk instead */ 4705 #define PIO_OWER_P19_Pos 19 /**< (PIO_OWER) Output Write Enable Position */ 4706 #define PIO_OWER_P19_Msk (_U_(0x1) << PIO_OWER_P19_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4707 #define PIO_OWER_P19 PIO_OWER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P19_Msk instead */ 4708 #define PIO_OWER_P20_Pos 20 /**< (PIO_OWER) Output Write Enable Position */ 4709 #define PIO_OWER_P20_Msk (_U_(0x1) << PIO_OWER_P20_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4710 #define PIO_OWER_P20 PIO_OWER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P20_Msk instead */ 4711 #define PIO_OWER_P21_Pos 21 /**< (PIO_OWER) Output Write Enable Position */ 4712 #define PIO_OWER_P21_Msk (_U_(0x1) << PIO_OWER_P21_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4713 #define PIO_OWER_P21 PIO_OWER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P21_Msk instead */ 4714 #define PIO_OWER_P22_Pos 22 /**< (PIO_OWER) Output Write Enable Position */ 4715 #define PIO_OWER_P22_Msk (_U_(0x1) << PIO_OWER_P22_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4716 #define PIO_OWER_P22 PIO_OWER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P22_Msk instead */ 4717 #define PIO_OWER_P23_Pos 23 /**< (PIO_OWER) Output Write Enable Position */ 4718 #define PIO_OWER_P23_Msk (_U_(0x1) << PIO_OWER_P23_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4719 #define PIO_OWER_P23 PIO_OWER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P23_Msk instead */ 4720 #define PIO_OWER_P24_Pos 24 /**< (PIO_OWER) Output Write Enable Position */ 4721 #define PIO_OWER_P24_Msk (_U_(0x1) << PIO_OWER_P24_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4722 #define PIO_OWER_P24 PIO_OWER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P24_Msk instead */ 4723 #define PIO_OWER_P25_Pos 25 /**< (PIO_OWER) Output Write Enable Position */ 4724 #define PIO_OWER_P25_Msk (_U_(0x1) << PIO_OWER_P25_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4725 #define PIO_OWER_P25 PIO_OWER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P25_Msk instead */ 4726 #define PIO_OWER_P26_Pos 26 /**< (PIO_OWER) Output Write Enable Position */ 4727 #define PIO_OWER_P26_Msk (_U_(0x1) << PIO_OWER_P26_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4728 #define PIO_OWER_P26 PIO_OWER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P26_Msk instead */ 4729 #define PIO_OWER_P27_Pos 27 /**< (PIO_OWER) Output Write Enable Position */ 4730 #define PIO_OWER_P27_Msk (_U_(0x1) << PIO_OWER_P27_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4731 #define PIO_OWER_P27 PIO_OWER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P27_Msk instead */ 4732 #define PIO_OWER_P28_Pos 28 /**< (PIO_OWER) Output Write Enable Position */ 4733 #define PIO_OWER_P28_Msk (_U_(0x1) << PIO_OWER_P28_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4734 #define PIO_OWER_P28 PIO_OWER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P28_Msk instead */ 4735 #define PIO_OWER_P29_Pos 29 /**< (PIO_OWER) Output Write Enable Position */ 4736 #define PIO_OWER_P29_Msk (_U_(0x1) << PIO_OWER_P29_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4737 #define PIO_OWER_P29 PIO_OWER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P29_Msk instead */ 4738 #define PIO_OWER_P30_Pos 30 /**< (PIO_OWER) Output Write Enable Position */ 4739 #define PIO_OWER_P30_Msk (_U_(0x1) << PIO_OWER_P30_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4740 #define PIO_OWER_P30 PIO_OWER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P30_Msk instead */ 4741 #define PIO_OWER_P31_Pos 31 /**< (PIO_OWER) Output Write Enable Position */ 4742 #define PIO_OWER_P31_Msk (_U_(0x1) << PIO_OWER_P31_Pos) /**< (PIO_OWER) Output Write Enable Mask */ 4743 #define PIO_OWER_P31 PIO_OWER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P31_Msk instead */ 4744 #define PIO_OWER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_OWER) Register MASK (Use PIO_OWER_Msk instead) */ 4745 #define PIO_OWER_Msk _U_(0xFFFFFFFF) /**< (PIO_OWER) Register Mask */ 4746 4747 #define PIO_OWER_P_Pos 0 /**< (PIO_OWER Position) Output Write Enable */ 4748 #define PIO_OWER_P_Msk (_U_(0xFFFFFFFF) << PIO_OWER_P_Pos) /**< (PIO_OWER Mask) P */ 4749 #define PIO_OWER_P(value) (PIO_OWER_P_Msk & ((value) << PIO_OWER_P_Pos)) 4750 4751 /* -------- PIO_OWDR : (PIO Offset: 0xa4) (/W 32) Output Write Disable -------- */ 4752 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4753 #if COMPONENT_TYPEDEF_STYLE == 'N' 4754 typedef union { 4755 struct { 4756 uint32_t P0:1; /**< bit: 0 Output Write Disable */ 4757 uint32_t P1:1; /**< bit: 1 Output Write Disable */ 4758 uint32_t P2:1; /**< bit: 2 Output Write Disable */ 4759 uint32_t P3:1; /**< bit: 3 Output Write Disable */ 4760 uint32_t P4:1; /**< bit: 4 Output Write Disable */ 4761 uint32_t P5:1; /**< bit: 5 Output Write Disable */ 4762 uint32_t P6:1; /**< bit: 6 Output Write Disable */ 4763 uint32_t P7:1; /**< bit: 7 Output Write Disable */ 4764 uint32_t P8:1; /**< bit: 8 Output Write Disable */ 4765 uint32_t P9:1; /**< bit: 9 Output Write Disable */ 4766 uint32_t P10:1; /**< bit: 10 Output Write Disable */ 4767 uint32_t P11:1; /**< bit: 11 Output Write Disable */ 4768 uint32_t P12:1; /**< bit: 12 Output Write Disable */ 4769 uint32_t P13:1; /**< bit: 13 Output Write Disable */ 4770 uint32_t P14:1; /**< bit: 14 Output Write Disable */ 4771 uint32_t P15:1; /**< bit: 15 Output Write Disable */ 4772 uint32_t P16:1; /**< bit: 16 Output Write Disable */ 4773 uint32_t P17:1; /**< bit: 17 Output Write Disable */ 4774 uint32_t P18:1; /**< bit: 18 Output Write Disable */ 4775 uint32_t P19:1; /**< bit: 19 Output Write Disable */ 4776 uint32_t P20:1; /**< bit: 20 Output Write Disable */ 4777 uint32_t P21:1; /**< bit: 21 Output Write Disable */ 4778 uint32_t P22:1; /**< bit: 22 Output Write Disable */ 4779 uint32_t P23:1; /**< bit: 23 Output Write Disable */ 4780 uint32_t P24:1; /**< bit: 24 Output Write Disable */ 4781 uint32_t P25:1; /**< bit: 25 Output Write Disable */ 4782 uint32_t P26:1; /**< bit: 26 Output Write Disable */ 4783 uint32_t P27:1; /**< bit: 27 Output Write Disable */ 4784 uint32_t P28:1; /**< bit: 28 Output Write Disable */ 4785 uint32_t P29:1; /**< bit: 29 Output Write Disable */ 4786 uint32_t P30:1; /**< bit: 30 Output Write Disable */ 4787 uint32_t P31:1; /**< bit: 31 Output Write Disable */ 4788 } bit; /**< Structure used for bit access */ 4789 struct { 4790 uint32_t P:32; /**< bit: 0..31 Output Write Disable */ 4791 } vec; /**< Structure used for vec access */ 4792 uint32_t reg; /**< Type used for register access */ 4793 } PIO_OWDR_Type; 4794 #endif 4795 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4796 4797 #define PIO_OWDR_OFFSET (0xA4) /**< (PIO_OWDR) Output Write Disable Offset */ 4798 4799 #define PIO_OWDR_P0_Pos 0 /**< (PIO_OWDR) Output Write Disable Position */ 4800 #define PIO_OWDR_P0_Msk (_U_(0x1) << PIO_OWDR_P0_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4801 #define PIO_OWDR_P0 PIO_OWDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P0_Msk instead */ 4802 #define PIO_OWDR_P1_Pos 1 /**< (PIO_OWDR) Output Write Disable Position */ 4803 #define PIO_OWDR_P1_Msk (_U_(0x1) << PIO_OWDR_P1_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4804 #define PIO_OWDR_P1 PIO_OWDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P1_Msk instead */ 4805 #define PIO_OWDR_P2_Pos 2 /**< (PIO_OWDR) Output Write Disable Position */ 4806 #define PIO_OWDR_P2_Msk (_U_(0x1) << PIO_OWDR_P2_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4807 #define PIO_OWDR_P2 PIO_OWDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P2_Msk instead */ 4808 #define PIO_OWDR_P3_Pos 3 /**< (PIO_OWDR) Output Write Disable Position */ 4809 #define PIO_OWDR_P3_Msk (_U_(0x1) << PIO_OWDR_P3_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4810 #define PIO_OWDR_P3 PIO_OWDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P3_Msk instead */ 4811 #define PIO_OWDR_P4_Pos 4 /**< (PIO_OWDR) Output Write Disable Position */ 4812 #define PIO_OWDR_P4_Msk (_U_(0x1) << PIO_OWDR_P4_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4813 #define PIO_OWDR_P4 PIO_OWDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P4_Msk instead */ 4814 #define PIO_OWDR_P5_Pos 5 /**< (PIO_OWDR) Output Write Disable Position */ 4815 #define PIO_OWDR_P5_Msk (_U_(0x1) << PIO_OWDR_P5_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4816 #define PIO_OWDR_P5 PIO_OWDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P5_Msk instead */ 4817 #define PIO_OWDR_P6_Pos 6 /**< (PIO_OWDR) Output Write Disable Position */ 4818 #define PIO_OWDR_P6_Msk (_U_(0x1) << PIO_OWDR_P6_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4819 #define PIO_OWDR_P6 PIO_OWDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P6_Msk instead */ 4820 #define PIO_OWDR_P7_Pos 7 /**< (PIO_OWDR) Output Write Disable Position */ 4821 #define PIO_OWDR_P7_Msk (_U_(0x1) << PIO_OWDR_P7_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4822 #define PIO_OWDR_P7 PIO_OWDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P7_Msk instead */ 4823 #define PIO_OWDR_P8_Pos 8 /**< (PIO_OWDR) Output Write Disable Position */ 4824 #define PIO_OWDR_P8_Msk (_U_(0x1) << PIO_OWDR_P8_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4825 #define PIO_OWDR_P8 PIO_OWDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P8_Msk instead */ 4826 #define PIO_OWDR_P9_Pos 9 /**< (PIO_OWDR) Output Write Disable Position */ 4827 #define PIO_OWDR_P9_Msk (_U_(0x1) << PIO_OWDR_P9_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4828 #define PIO_OWDR_P9 PIO_OWDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P9_Msk instead */ 4829 #define PIO_OWDR_P10_Pos 10 /**< (PIO_OWDR) Output Write Disable Position */ 4830 #define PIO_OWDR_P10_Msk (_U_(0x1) << PIO_OWDR_P10_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4831 #define PIO_OWDR_P10 PIO_OWDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P10_Msk instead */ 4832 #define PIO_OWDR_P11_Pos 11 /**< (PIO_OWDR) Output Write Disable Position */ 4833 #define PIO_OWDR_P11_Msk (_U_(0x1) << PIO_OWDR_P11_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4834 #define PIO_OWDR_P11 PIO_OWDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P11_Msk instead */ 4835 #define PIO_OWDR_P12_Pos 12 /**< (PIO_OWDR) Output Write Disable Position */ 4836 #define PIO_OWDR_P12_Msk (_U_(0x1) << PIO_OWDR_P12_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4837 #define PIO_OWDR_P12 PIO_OWDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P12_Msk instead */ 4838 #define PIO_OWDR_P13_Pos 13 /**< (PIO_OWDR) Output Write Disable Position */ 4839 #define PIO_OWDR_P13_Msk (_U_(0x1) << PIO_OWDR_P13_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4840 #define PIO_OWDR_P13 PIO_OWDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P13_Msk instead */ 4841 #define PIO_OWDR_P14_Pos 14 /**< (PIO_OWDR) Output Write Disable Position */ 4842 #define PIO_OWDR_P14_Msk (_U_(0x1) << PIO_OWDR_P14_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4843 #define PIO_OWDR_P14 PIO_OWDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P14_Msk instead */ 4844 #define PIO_OWDR_P15_Pos 15 /**< (PIO_OWDR) Output Write Disable Position */ 4845 #define PIO_OWDR_P15_Msk (_U_(0x1) << PIO_OWDR_P15_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4846 #define PIO_OWDR_P15 PIO_OWDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P15_Msk instead */ 4847 #define PIO_OWDR_P16_Pos 16 /**< (PIO_OWDR) Output Write Disable Position */ 4848 #define PIO_OWDR_P16_Msk (_U_(0x1) << PIO_OWDR_P16_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4849 #define PIO_OWDR_P16 PIO_OWDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P16_Msk instead */ 4850 #define PIO_OWDR_P17_Pos 17 /**< (PIO_OWDR) Output Write Disable Position */ 4851 #define PIO_OWDR_P17_Msk (_U_(0x1) << PIO_OWDR_P17_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4852 #define PIO_OWDR_P17 PIO_OWDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P17_Msk instead */ 4853 #define PIO_OWDR_P18_Pos 18 /**< (PIO_OWDR) Output Write Disable Position */ 4854 #define PIO_OWDR_P18_Msk (_U_(0x1) << PIO_OWDR_P18_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4855 #define PIO_OWDR_P18 PIO_OWDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P18_Msk instead */ 4856 #define PIO_OWDR_P19_Pos 19 /**< (PIO_OWDR) Output Write Disable Position */ 4857 #define PIO_OWDR_P19_Msk (_U_(0x1) << PIO_OWDR_P19_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4858 #define PIO_OWDR_P19 PIO_OWDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P19_Msk instead */ 4859 #define PIO_OWDR_P20_Pos 20 /**< (PIO_OWDR) Output Write Disable Position */ 4860 #define PIO_OWDR_P20_Msk (_U_(0x1) << PIO_OWDR_P20_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4861 #define PIO_OWDR_P20 PIO_OWDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P20_Msk instead */ 4862 #define PIO_OWDR_P21_Pos 21 /**< (PIO_OWDR) Output Write Disable Position */ 4863 #define PIO_OWDR_P21_Msk (_U_(0x1) << PIO_OWDR_P21_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4864 #define PIO_OWDR_P21 PIO_OWDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P21_Msk instead */ 4865 #define PIO_OWDR_P22_Pos 22 /**< (PIO_OWDR) Output Write Disable Position */ 4866 #define PIO_OWDR_P22_Msk (_U_(0x1) << PIO_OWDR_P22_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4867 #define PIO_OWDR_P22 PIO_OWDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P22_Msk instead */ 4868 #define PIO_OWDR_P23_Pos 23 /**< (PIO_OWDR) Output Write Disable Position */ 4869 #define PIO_OWDR_P23_Msk (_U_(0x1) << PIO_OWDR_P23_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4870 #define PIO_OWDR_P23 PIO_OWDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P23_Msk instead */ 4871 #define PIO_OWDR_P24_Pos 24 /**< (PIO_OWDR) Output Write Disable Position */ 4872 #define PIO_OWDR_P24_Msk (_U_(0x1) << PIO_OWDR_P24_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4873 #define PIO_OWDR_P24 PIO_OWDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P24_Msk instead */ 4874 #define PIO_OWDR_P25_Pos 25 /**< (PIO_OWDR) Output Write Disable Position */ 4875 #define PIO_OWDR_P25_Msk (_U_(0x1) << PIO_OWDR_P25_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4876 #define PIO_OWDR_P25 PIO_OWDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P25_Msk instead */ 4877 #define PIO_OWDR_P26_Pos 26 /**< (PIO_OWDR) Output Write Disable Position */ 4878 #define PIO_OWDR_P26_Msk (_U_(0x1) << PIO_OWDR_P26_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4879 #define PIO_OWDR_P26 PIO_OWDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P26_Msk instead */ 4880 #define PIO_OWDR_P27_Pos 27 /**< (PIO_OWDR) Output Write Disable Position */ 4881 #define PIO_OWDR_P27_Msk (_U_(0x1) << PIO_OWDR_P27_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4882 #define PIO_OWDR_P27 PIO_OWDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P27_Msk instead */ 4883 #define PIO_OWDR_P28_Pos 28 /**< (PIO_OWDR) Output Write Disable Position */ 4884 #define PIO_OWDR_P28_Msk (_U_(0x1) << PIO_OWDR_P28_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4885 #define PIO_OWDR_P28 PIO_OWDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P28_Msk instead */ 4886 #define PIO_OWDR_P29_Pos 29 /**< (PIO_OWDR) Output Write Disable Position */ 4887 #define PIO_OWDR_P29_Msk (_U_(0x1) << PIO_OWDR_P29_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4888 #define PIO_OWDR_P29 PIO_OWDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P29_Msk instead */ 4889 #define PIO_OWDR_P30_Pos 30 /**< (PIO_OWDR) Output Write Disable Position */ 4890 #define PIO_OWDR_P30_Msk (_U_(0x1) << PIO_OWDR_P30_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4891 #define PIO_OWDR_P30 PIO_OWDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P30_Msk instead */ 4892 #define PIO_OWDR_P31_Pos 31 /**< (PIO_OWDR) Output Write Disable Position */ 4893 #define PIO_OWDR_P31_Msk (_U_(0x1) << PIO_OWDR_P31_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ 4894 #define PIO_OWDR_P31 PIO_OWDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P31_Msk instead */ 4895 #define PIO_OWDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_OWDR) Register MASK (Use PIO_OWDR_Msk instead) */ 4896 #define PIO_OWDR_Msk _U_(0xFFFFFFFF) /**< (PIO_OWDR) Register Mask */ 4897 4898 #define PIO_OWDR_P_Pos 0 /**< (PIO_OWDR Position) Output Write Disable */ 4899 #define PIO_OWDR_P_Msk (_U_(0xFFFFFFFF) << PIO_OWDR_P_Pos) /**< (PIO_OWDR Mask) P */ 4900 #define PIO_OWDR_P(value) (PIO_OWDR_P_Msk & ((value) << PIO_OWDR_P_Pos)) 4901 4902 /* -------- PIO_OWSR : (PIO Offset: 0xa8) (R/ 32) Output Write Status Register -------- */ 4903 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4904 #if COMPONENT_TYPEDEF_STYLE == 'N' 4905 typedef union { 4906 struct { 4907 uint32_t P0:1; /**< bit: 0 Output Write Status */ 4908 uint32_t P1:1; /**< bit: 1 Output Write Status */ 4909 uint32_t P2:1; /**< bit: 2 Output Write Status */ 4910 uint32_t P3:1; /**< bit: 3 Output Write Status */ 4911 uint32_t P4:1; /**< bit: 4 Output Write Status */ 4912 uint32_t P5:1; /**< bit: 5 Output Write Status */ 4913 uint32_t P6:1; /**< bit: 6 Output Write Status */ 4914 uint32_t P7:1; /**< bit: 7 Output Write Status */ 4915 uint32_t P8:1; /**< bit: 8 Output Write Status */ 4916 uint32_t P9:1; /**< bit: 9 Output Write Status */ 4917 uint32_t P10:1; /**< bit: 10 Output Write Status */ 4918 uint32_t P11:1; /**< bit: 11 Output Write Status */ 4919 uint32_t P12:1; /**< bit: 12 Output Write Status */ 4920 uint32_t P13:1; /**< bit: 13 Output Write Status */ 4921 uint32_t P14:1; /**< bit: 14 Output Write Status */ 4922 uint32_t P15:1; /**< bit: 15 Output Write Status */ 4923 uint32_t P16:1; /**< bit: 16 Output Write Status */ 4924 uint32_t P17:1; /**< bit: 17 Output Write Status */ 4925 uint32_t P18:1; /**< bit: 18 Output Write Status */ 4926 uint32_t P19:1; /**< bit: 19 Output Write Status */ 4927 uint32_t P20:1; /**< bit: 20 Output Write Status */ 4928 uint32_t P21:1; /**< bit: 21 Output Write Status */ 4929 uint32_t P22:1; /**< bit: 22 Output Write Status */ 4930 uint32_t P23:1; /**< bit: 23 Output Write Status */ 4931 uint32_t P24:1; /**< bit: 24 Output Write Status */ 4932 uint32_t P25:1; /**< bit: 25 Output Write Status */ 4933 uint32_t P26:1; /**< bit: 26 Output Write Status */ 4934 uint32_t P27:1; /**< bit: 27 Output Write Status */ 4935 uint32_t P28:1; /**< bit: 28 Output Write Status */ 4936 uint32_t P29:1; /**< bit: 29 Output Write Status */ 4937 uint32_t P30:1; /**< bit: 30 Output Write Status */ 4938 uint32_t P31:1; /**< bit: 31 Output Write Status */ 4939 } bit; /**< Structure used for bit access */ 4940 struct { 4941 uint32_t P:32; /**< bit: 0..31 Output Write Status */ 4942 } vec; /**< Structure used for vec access */ 4943 uint32_t reg; /**< Type used for register access */ 4944 } PIO_OWSR_Type; 4945 #endif 4946 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4947 4948 #define PIO_OWSR_OFFSET (0xA8) /**< (PIO_OWSR) Output Write Status Register Offset */ 4949 4950 #define PIO_OWSR_P0_Pos 0 /**< (PIO_OWSR) Output Write Status Position */ 4951 #define PIO_OWSR_P0_Msk (_U_(0x1) << PIO_OWSR_P0_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4952 #define PIO_OWSR_P0 PIO_OWSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P0_Msk instead */ 4953 #define PIO_OWSR_P1_Pos 1 /**< (PIO_OWSR) Output Write Status Position */ 4954 #define PIO_OWSR_P1_Msk (_U_(0x1) << PIO_OWSR_P1_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4955 #define PIO_OWSR_P1 PIO_OWSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P1_Msk instead */ 4956 #define PIO_OWSR_P2_Pos 2 /**< (PIO_OWSR) Output Write Status Position */ 4957 #define PIO_OWSR_P2_Msk (_U_(0x1) << PIO_OWSR_P2_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4958 #define PIO_OWSR_P2 PIO_OWSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P2_Msk instead */ 4959 #define PIO_OWSR_P3_Pos 3 /**< (PIO_OWSR) Output Write Status Position */ 4960 #define PIO_OWSR_P3_Msk (_U_(0x1) << PIO_OWSR_P3_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4961 #define PIO_OWSR_P3 PIO_OWSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P3_Msk instead */ 4962 #define PIO_OWSR_P4_Pos 4 /**< (PIO_OWSR) Output Write Status Position */ 4963 #define PIO_OWSR_P4_Msk (_U_(0x1) << PIO_OWSR_P4_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4964 #define PIO_OWSR_P4 PIO_OWSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P4_Msk instead */ 4965 #define PIO_OWSR_P5_Pos 5 /**< (PIO_OWSR) Output Write Status Position */ 4966 #define PIO_OWSR_P5_Msk (_U_(0x1) << PIO_OWSR_P5_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4967 #define PIO_OWSR_P5 PIO_OWSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P5_Msk instead */ 4968 #define PIO_OWSR_P6_Pos 6 /**< (PIO_OWSR) Output Write Status Position */ 4969 #define PIO_OWSR_P6_Msk (_U_(0x1) << PIO_OWSR_P6_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4970 #define PIO_OWSR_P6 PIO_OWSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P6_Msk instead */ 4971 #define PIO_OWSR_P7_Pos 7 /**< (PIO_OWSR) Output Write Status Position */ 4972 #define PIO_OWSR_P7_Msk (_U_(0x1) << PIO_OWSR_P7_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4973 #define PIO_OWSR_P7 PIO_OWSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P7_Msk instead */ 4974 #define PIO_OWSR_P8_Pos 8 /**< (PIO_OWSR) Output Write Status Position */ 4975 #define PIO_OWSR_P8_Msk (_U_(0x1) << PIO_OWSR_P8_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4976 #define PIO_OWSR_P8 PIO_OWSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P8_Msk instead */ 4977 #define PIO_OWSR_P9_Pos 9 /**< (PIO_OWSR) Output Write Status Position */ 4978 #define PIO_OWSR_P9_Msk (_U_(0x1) << PIO_OWSR_P9_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4979 #define PIO_OWSR_P9 PIO_OWSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P9_Msk instead */ 4980 #define PIO_OWSR_P10_Pos 10 /**< (PIO_OWSR) Output Write Status Position */ 4981 #define PIO_OWSR_P10_Msk (_U_(0x1) << PIO_OWSR_P10_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4982 #define PIO_OWSR_P10 PIO_OWSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P10_Msk instead */ 4983 #define PIO_OWSR_P11_Pos 11 /**< (PIO_OWSR) Output Write Status Position */ 4984 #define PIO_OWSR_P11_Msk (_U_(0x1) << PIO_OWSR_P11_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4985 #define PIO_OWSR_P11 PIO_OWSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P11_Msk instead */ 4986 #define PIO_OWSR_P12_Pos 12 /**< (PIO_OWSR) Output Write Status Position */ 4987 #define PIO_OWSR_P12_Msk (_U_(0x1) << PIO_OWSR_P12_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4988 #define PIO_OWSR_P12 PIO_OWSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P12_Msk instead */ 4989 #define PIO_OWSR_P13_Pos 13 /**< (PIO_OWSR) Output Write Status Position */ 4990 #define PIO_OWSR_P13_Msk (_U_(0x1) << PIO_OWSR_P13_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4991 #define PIO_OWSR_P13 PIO_OWSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P13_Msk instead */ 4992 #define PIO_OWSR_P14_Pos 14 /**< (PIO_OWSR) Output Write Status Position */ 4993 #define PIO_OWSR_P14_Msk (_U_(0x1) << PIO_OWSR_P14_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4994 #define PIO_OWSR_P14 PIO_OWSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P14_Msk instead */ 4995 #define PIO_OWSR_P15_Pos 15 /**< (PIO_OWSR) Output Write Status Position */ 4996 #define PIO_OWSR_P15_Msk (_U_(0x1) << PIO_OWSR_P15_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 4997 #define PIO_OWSR_P15 PIO_OWSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P15_Msk instead */ 4998 #define PIO_OWSR_P16_Pos 16 /**< (PIO_OWSR) Output Write Status Position */ 4999 #define PIO_OWSR_P16_Msk (_U_(0x1) << PIO_OWSR_P16_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5000 #define PIO_OWSR_P16 PIO_OWSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P16_Msk instead */ 5001 #define PIO_OWSR_P17_Pos 17 /**< (PIO_OWSR) Output Write Status Position */ 5002 #define PIO_OWSR_P17_Msk (_U_(0x1) << PIO_OWSR_P17_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5003 #define PIO_OWSR_P17 PIO_OWSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P17_Msk instead */ 5004 #define PIO_OWSR_P18_Pos 18 /**< (PIO_OWSR) Output Write Status Position */ 5005 #define PIO_OWSR_P18_Msk (_U_(0x1) << PIO_OWSR_P18_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5006 #define PIO_OWSR_P18 PIO_OWSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P18_Msk instead */ 5007 #define PIO_OWSR_P19_Pos 19 /**< (PIO_OWSR) Output Write Status Position */ 5008 #define PIO_OWSR_P19_Msk (_U_(0x1) << PIO_OWSR_P19_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5009 #define PIO_OWSR_P19 PIO_OWSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P19_Msk instead */ 5010 #define PIO_OWSR_P20_Pos 20 /**< (PIO_OWSR) Output Write Status Position */ 5011 #define PIO_OWSR_P20_Msk (_U_(0x1) << PIO_OWSR_P20_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5012 #define PIO_OWSR_P20 PIO_OWSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P20_Msk instead */ 5013 #define PIO_OWSR_P21_Pos 21 /**< (PIO_OWSR) Output Write Status Position */ 5014 #define PIO_OWSR_P21_Msk (_U_(0x1) << PIO_OWSR_P21_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5015 #define PIO_OWSR_P21 PIO_OWSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P21_Msk instead */ 5016 #define PIO_OWSR_P22_Pos 22 /**< (PIO_OWSR) Output Write Status Position */ 5017 #define PIO_OWSR_P22_Msk (_U_(0x1) << PIO_OWSR_P22_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5018 #define PIO_OWSR_P22 PIO_OWSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P22_Msk instead */ 5019 #define PIO_OWSR_P23_Pos 23 /**< (PIO_OWSR) Output Write Status Position */ 5020 #define PIO_OWSR_P23_Msk (_U_(0x1) << PIO_OWSR_P23_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5021 #define PIO_OWSR_P23 PIO_OWSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P23_Msk instead */ 5022 #define PIO_OWSR_P24_Pos 24 /**< (PIO_OWSR) Output Write Status Position */ 5023 #define PIO_OWSR_P24_Msk (_U_(0x1) << PIO_OWSR_P24_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5024 #define PIO_OWSR_P24 PIO_OWSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P24_Msk instead */ 5025 #define PIO_OWSR_P25_Pos 25 /**< (PIO_OWSR) Output Write Status Position */ 5026 #define PIO_OWSR_P25_Msk (_U_(0x1) << PIO_OWSR_P25_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5027 #define PIO_OWSR_P25 PIO_OWSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P25_Msk instead */ 5028 #define PIO_OWSR_P26_Pos 26 /**< (PIO_OWSR) Output Write Status Position */ 5029 #define PIO_OWSR_P26_Msk (_U_(0x1) << PIO_OWSR_P26_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5030 #define PIO_OWSR_P26 PIO_OWSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P26_Msk instead */ 5031 #define PIO_OWSR_P27_Pos 27 /**< (PIO_OWSR) Output Write Status Position */ 5032 #define PIO_OWSR_P27_Msk (_U_(0x1) << PIO_OWSR_P27_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5033 #define PIO_OWSR_P27 PIO_OWSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P27_Msk instead */ 5034 #define PIO_OWSR_P28_Pos 28 /**< (PIO_OWSR) Output Write Status Position */ 5035 #define PIO_OWSR_P28_Msk (_U_(0x1) << PIO_OWSR_P28_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5036 #define PIO_OWSR_P28 PIO_OWSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P28_Msk instead */ 5037 #define PIO_OWSR_P29_Pos 29 /**< (PIO_OWSR) Output Write Status Position */ 5038 #define PIO_OWSR_P29_Msk (_U_(0x1) << PIO_OWSR_P29_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5039 #define PIO_OWSR_P29 PIO_OWSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P29_Msk instead */ 5040 #define PIO_OWSR_P30_Pos 30 /**< (PIO_OWSR) Output Write Status Position */ 5041 #define PIO_OWSR_P30_Msk (_U_(0x1) << PIO_OWSR_P30_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5042 #define PIO_OWSR_P30 PIO_OWSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P30_Msk instead */ 5043 #define PIO_OWSR_P31_Pos 31 /**< (PIO_OWSR) Output Write Status Position */ 5044 #define PIO_OWSR_P31_Msk (_U_(0x1) << PIO_OWSR_P31_Pos) /**< (PIO_OWSR) Output Write Status Mask */ 5045 #define PIO_OWSR_P31 PIO_OWSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P31_Msk instead */ 5046 #define PIO_OWSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_OWSR) Register MASK (Use PIO_OWSR_Msk instead) */ 5047 #define PIO_OWSR_Msk _U_(0xFFFFFFFF) /**< (PIO_OWSR) Register Mask */ 5048 5049 #define PIO_OWSR_P_Pos 0 /**< (PIO_OWSR Position) Output Write Status */ 5050 #define PIO_OWSR_P_Msk (_U_(0xFFFFFFFF) << PIO_OWSR_P_Pos) /**< (PIO_OWSR Mask) P */ 5051 #define PIO_OWSR_P(value) (PIO_OWSR_P_Msk & ((value) << PIO_OWSR_P_Pos)) 5052 5053 /* -------- PIO_AIMER : (PIO Offset: 0xb0) (/W 32) Additional Interrupt Modes Enable Register -------- */ 5054 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 5055 #if COMPONENT_TYPEDEF_STYLE == 'N' 5056 typedef union { 5057 struct { 5058 uint32_t P0:1; /**< bit: 0 Additional Interrupt Modes Enable */ 5059 uint32_t P1:1; /**< bit: 1 Additional Interrupt Modes Enable */ 5060 uint32_t P2:1; /**< bit: 2 Additional Interrupt Modes Enable */ 5061 uint32_t P3:1; /**< bit: 3 Additional Interrupt Modes Enable */ 5062 uint32_t P4:1; /**< bit: 4 Additional Interrupt Modes Enable */ 5063 uint32_t P5:1; /**< bit: 5 Additional Interrupt Modes Enable */ 5064 uint32_t P6:1; /**< bit: 6 Additional Interrupt Modes Enable */ 5065 uint32_t P7:1; /**< bit: 7 Additional Interrupt Modes Enable */ 5066 uint32_t P8:1; /**< bit: 8 Additional Interrupt Modes Enable */ 5067 uint32_t P9:1; /**< bit: 9 Additional Interrupt Modes Enable */ 5068 uint32_t P10:1; /**< bit: 10 Additional Interrupt Modes Enable */ 5069 uint32_t P11:1; /**< bit: 11 Additional Interrupt Modes Enable */ 5070 uint32_t P12:1; /**< bit: 12 Additional Interrupt Modes Enable */ 5071 uint32_t P13:1; /**< bit: 13 Additional Interrupt Modes Enable */ 5072 uint32_t P14:1; /**< bit: 14 Additional Interrupt Modes Enable */ 5073 uint32_t P15:1; /**< bit: 15 Additional Interrupt Modes Enable */ 5074 uint32_t P16:1; /**< bit: 16 Additional Interrupt Modes Enable */ 5075 uint32_t P17:1; /**< bit: 17 Additional Interrupt Modes Enable */ 5076 uint32_t P18:1; /**< bit: 18 Additional Interrupt Modes Enable */ 5077 uint32_t P19:1; /**< bit: 19 Additional Interrupt Modes Enable */ 5078 uint32_t P20:1; /**< bit: 20 Additional Interrupt Modes Enable */ 5079 uint32_t P21:1; /**< bit: 21 Additional Interrupt Modes Enable */ 5080 uint32_t P22:1; /**< bit: 22 Additional Interrupt Modes Enable */ 5081 uint32_t P23:1; /**< bit: 23 Additional Interrupt Modes Enable */ 5082 uint32_t P24:1; /**< bit: 24 Additional Interrupt Modes Enable */ 5083 uint32_t P25:1; /**< bit: 25 Additional Interrupt Modes Enable */ 5084 uint32_t P26:1; /**< bit: 26 Additional Interrupt Modes Enable */ 5085 uint32_t P27:1; /**< bit: 27 Additional Interrupt Modes Enable */ 5086 uint32_t P28:1; /**< bit: 28 Additional Interrupt Modes Enable */ 5087 uint32_t P29:1; /**< bit: 29 Additional Interrupt Modes Enable */ 5088 uint32_t P30:1; /**< bit: 30 Additional Interrupt Modes Enable */ 5089 uint32_t P31:1; /**< bit: 31 Additional Interrupt Modes Enable */ 5090 } bit; /**< Structure used for bit access */ 5091 struct { 5092 uint32_t P:32; /**< bit: 0..31 Additional Interrupt Modes Enable */ 5093 } vec; /**< Structure used for vec access */ 5094 uint32_t reg; /**< Type used for register access */ 5095 } PIO_AIMER_Type; 5096 #endif 5097 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 5098 5099 #define PIO_AIMER_OFFSET (0xB0) /**< (PIO_AIMER) Additional Interrupt Modes Enable Register Offset */ 5100 5101 #define PIO_AIMER_P0_Pos 0 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5102 #define PIO_AIMER_P0_Msk (_U_(0x1) << PIO_AIMER_P0_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5103 #define PIO_AIMER_P0 PIO_AIMER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P0_Msk instead */ 5104 #define PIO_AIMER_P1_Pos 1 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5105 #define PIO_AIMER_P1_Msk (_U_(0x1) << PIO_AIMER_P1_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5106 #define PIO_AIMER_P1 PIO_AIMER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P1_Msk instead */ 5107 #define PIO_AIMER_P2_Pos 2 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5108 #define PIO_AIMER_P2_Msk (_U_(0x1) << PIO_AIMER_P2_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5109 #define PIO_AIMER_P2 PIO_AIMER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P2_Msk instead */ 5110 #define PIO_AIMER_P3_Pos 3 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5111 #define PIO_AIMER_P3_Msk (_U_(0x1) << PIO_AIMER_P3_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5112 #define PIO_AIMER_P3 PIO_AIMER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P3_Msk instead */ 5113 #define PIO_AIMER_P4_Pos 4 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5114 #define PIO_AIMER_P4_Msk (_U_(0x1) << PIO_AIMER_P4_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5115 #define PIO_AIMER_P4 PIO_AIMER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P4_Msk instead */ 5116 #define PIO_AIMER_P5_Pos 5 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5117 #define PIO_AIMER_P5_Msk (_U_(0x1) << PIO_AIMER_P5_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5118 #define PIO_AIMER_P5 PIO_AIMER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P5_Msk instead */ 5119 #define PIO_AIMER_P6_Pos 6 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5120 #define PIO_AIMER_P6_Msk (_U_(0x1) << PIO_AIMER_P6_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5121 #define PIO_AIMER_P6 PIO_AIMER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P6_Msk instead */ 5122 #define PIO_AIMER_P7_Pos 7 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5123 #define PIO_AIMER_P7_Msk (_U_(0x1) << PIO_AIMER_P7_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5124 #define PIO_AIMER_P7 PIO_AIMER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P7_Msk instead */ 5125 #define PIO_AIMER_P8_Pos 8 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5126 #define PIO_AIMER_P8_Msk (_U_(0x1) << PIO_AIMER_P8_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5127 #define PIO_AIMER_P8 PIO_AIMER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P8_Msk instead */ 5128 #define PIO_AIMER_P9_Pos 9 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5129 #define PIO_AIMER_P9_Msk (_U_(0x1) << PIO_AIMER_P9_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5130 #define PIO_AIMER_P9 PIO_AIMER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P9_Msk instead */ 5131 #define PIO_AIMER_P10_Pos 10 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5132 #define PIO_AIMER_P10_Msk (_U_(0x1) << PIO_AIMER_P10_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5133 #define PIO_AIMER_P10 PIO_AIMER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P10_Msk instead */ 5134 #define PIO_AIMER_P11_Pos 11 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5135 #define PIO_AIMER_P11_Msk (_U_(0x1) << PIO_AIMER_P11_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5136 #define PIO_AIMER_P11 PIO_AIMER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P11_Msk instead */ 5137 #define PIO_AIMER_P12_Pos 12 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5138 #define PIO_AIMER_P12_Msk (_U_(0x1) << PIO_AIMER_P12_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5139 #define PIO_AIMER_P12 PIO_AIMER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P12_Msk instead */ 5140 #define PIO_AIMER_P13_Pos 13 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5141 #define PIO_AIMER_P13_Msk (_U_(0x1) << PIO_AIMER_P13_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5142 #define PIO_AIMER_P13 PIO_AIMER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P13_Msk instead */ 5143 #define PIO_AIMER_P14_Pos 14 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5144 #define PIO_AIMER_P14_Msk (_U_(0x1) << PIO_AIMER_P14_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5145 #define PIO_AIMER_P14 PIO_AIMER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P14_Msk instead */ 5146 #define PIO_AIMER_P15_Pos 15 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5147 #define PIO_AIMER_P15_Msk (_U_(0x1) << PIO_AIMER_P15_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5148 #define PIO_AIMER_P15 PIO_AIMER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P15_Msk instead */ 5149 #define PIO_AIMER_P16_Pos 16 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5150 #define PIO_AIMER_P16_Msk (_U_(0x1) << PIO_AIMER_P16_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5151 #define PIO_AIMER_P16 PIO_AIMER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P16_Msk instead */ 5152 #define PIO_AIMER_P17_Pos 17 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5153 #define PIO_AIMER_P17_Msk (_U_(0x1) << PIO_AIMER_P17_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5154 #define PIO_AIMER_P17 PIO_AIMER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P17_Msk instead */ 5155 #define PIO_AIMER_P18_Pos 18 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5156 #define PIO_AIMER_P18_Msk (_U_(0x1) << PIO_AIMER_P18_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5157 #define PIO_AIMER_P18 PIO_AIMER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P18_Msk instead */ 5158 #define PIO_AIMER_P19_Pos 19 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5159 #define PIO_AIMER_P19_Msk (_U_(0x1) << PIO_AIMER_P19_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5160 #define PIO_AIMER_P19 PIO_AIMER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P19_Msk instead */ 5161 #define PIO_AIMER_P20_Pos 20 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5162 #define PIO_AIMER_P20_Msk (_U_(0x1) << PIO_AIMER_P20_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5163 #define PIO_AIMER_P20 PIO_AIMER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P20_Msk instead */ 5164 #define PIO_AIMER_P21_Pos 21 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5165 #define PIO_AIMER_P21_Msk (_U_(0x1) << PIO_AIMER_P21_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5166 #define PIO_AIMER_P21 PIO_AIMER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P21_Msk instead */ 5167 #define PIO_AIMER_P22_Pos 22 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5168 #define PIO_AIMER_P22_Msk (_U_(0x1) << PIO_AIMER_P22_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5169 #define PIO_AIMER_P22 PIO_AIMER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P22_Msk instead */ 5170 #define PIO_AIMER_P23_Pos 23 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5171 #define PIO_AIMER_P23_Msk (_U_(0x1) << PIO_AIMER_P23_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5172 #define PIO_AIMER_P23 PIO_AIMER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P23_Msk instead */ 5173 #define PIO_AIMER_P24_Pos 24 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5174 #define PIO_AIMER_P24_Msk (_U_(0x1) << PIO_AIMER_P24_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5175 #define PIO_AIMER_P24 PIO_AIMER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P24_Msk instead */ 5176 #define PIO_AIMER_P25_Pos 25 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5177 #define PIO_AIMER_P25_Msk (_U_(0x1) << PIO_AIMER_P25_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5178 #define PIO_AIMER_P25 PIO_AIMER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P25_Msk instead */ 5179 #define PIO_AIMER_P26_Pos 26 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5180 #define PIO_AIMER_P26_Msk (_U_(0x1) << PIO_AIMER_P26_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5181 #define PIO_AIMER_P26 PIO_AIMER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P26_Msk instead */ 5182 #define PIO_AIMER_P27_Pos 27 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5183 #define PIO_AIMER_P27_Msk (_U_(0x1) << PIO_AIMER_P27_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5184 #define PIO_AIMER_P27 PIO_AIMER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P27_Msk instead */ 5185 #define PIO_AIMER_P28_Pos 28 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5186 #define PIO_AIMER_P28_Msk (_U_(0x1) << PIO_AIMER_P28_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5187 #define PIO_AIMER_P28 PIO_AIMER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P28_Msk instead */ 5188 #define PIO_AIMER_P29_Pos 29 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5189 #define PIO_AIMER_P29_Msk (_U_(0x1) << PIO_AIMER_P29_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5190 #define PIO_AIMER_P29 PIO_AIMER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P29_Msk instead */ 5191 #define PIO_AIMER_P30_Pos 30 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5192 #define PIO_AIMER_P30_Msk (_U_(0x1) << PIO_AIMER_P30_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5193 #define PIO_AIMER_P30 PIO_AIMER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P30_Msk instead */ 5194 #define PIO_AIMER_P31_Pos 31 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ 5195 #define PIO_AIMER_P31_Msk (_U_(0x1) << PIO_AIMER_P31_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ 5196 #define PIO_AIMER_P31 PIO_AIMER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P31_Msk instead */ 5197 #define PIO_AIMER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_AIMER) Register MASK (Use PIO_AIMER_Msk instead) */ 5198 #define PIO_AIMER_Msk _U_(0xFFFFFFFF) /**< (PIO_AIMER) Register Mask */ 5199 5200 #define PIO_AIMER_P_Pos 0 /**< (PIO_AIMER Position) Additional Interrupt Modes Enable */ 5201 #define PIO_AIMER_P_Msk (_U_(0xFFFFFFFF) << PIO_AIMER_P_Pos) /**< (PIO_AIMER Mask) P */ 5202 #define PIO_AIMER_P(value) (PIO_AIMER_P_Msk & ((value) << PIO_AIMER_P_Pos)) 5203 5204 /* -------- PIO_AIMDR : (PIO Offset: 0xb4) (/W 32) Additional Interrupt Modes Disable Register -------- */ 5205 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 5206 #if COMPONENT_TYPEDEF_STYLE == 'N' 5207 typedef union { 5208 struct { 5209 uint32_t P0:1; /**< bit: 0 Additional Interrupt Modes Disable */ 5210 uint32_t P1:1; /**< bit: 1 Additional Interrupt Modes Disable */ 5211 uint32_t P2:1; /**< bit: 2 Additional Interrupt Modes Disable */ 5212 uint32_t P3:1; /**< bit: 3 Additional Interrupt Modes Disable */ 5213 uint32_t P4:1; /**< bit: 4 Additional Interrupt Modes Disable */ 5214 uint32_t P5:1; /**< bit: 5 Additional Interrupt Modes Disable */ 5215 uint32_t P6:1; /**< bit: 6 Additional Interrupt Modes Disable */ 5216 uint32_t P7:1; /**< bit: 7 Additional Interrupt Modes Disable */ 5217 uint32_t P8:1; /**< bit: 8 Additional Interrupt Modes Disable */ 5218 uint32_t P9:1; /**< bit: 9 Additional Interrupt Modes Disable */ 5219 uint32_t P10:1; /**< bit: 10 Additional Interrupt Modes Disable */ 5220 uint32_t P11:1; /**< bit: 11 Additional Interrupt Modes Disable */ 5221 uint32_t P12:1; /**< bit: 12 Additional Interrupt Modes Disable */ 5222 uint32_t P13:1; /**< bit: 13 Additional Interrupt Modes Disable */ 5223 uint32_t P14:1; /**< bit: 14 Additional Interrupt Modes Disable */ 5224 uint32_t P15:1; /**< bit: 15 Additional Interrupt Modes Disable */ 5225 uint32_t P16:1; /**< bit: 16 Additional Interrupt Modes Disable */ 5226 uint32_t P17:1; /**< bit: 17 Additional Interrupt Modes Disable */ 5227 uint32_t P18:1; /**< bit: 18 Additional Interrupt Modes Disable */ 5228 uint32_t P19:1; /**< bit: 19 Additional Interrupt Modes Disable */ 5229 uint32_t P20:1; /**< bit: 20 Additional Interrupt Modes Disable */ 5230 uint32_t P21:1; /**< bit: 21 Additional Interrupt Modes Disable */ 5231 uint32_t P22:1; /**< bit: 22 Additional Interrupt Modes Disable */ 5232 uint32_t P23:1; /**< bit: 23 Additional Interrupt Modes Disable */ 5233 uint32_t P24:1; /**< bit: 24 Additional Interrupt Modes Disable */ 5234 uint32_t P25:1; /**< bit: 25 Additional Interrupt Modes Disable */ 5235 uint32_t P26:1; /**< bit: 26 Additional Interrupt Modes Disable */ 5236 uint32_t P27:1; /**< bit: 27 Additional Interrupt Modes Disable */ 5237 uint32_t P28:1; /**< bit: 28 Additional Interrupt Modes Disable */ 5238 uint32_t P29:1; /**< bit: 29 Additional Interrupt Modes Disable */ 5239 uint32_t P30:1; /**< bit: 30 Additional Interrupt Modes Disable */ 5240 uint32_t P31:1; /**< bit: 31 Additional Interrupt Modes Disable */ 5241 } bit; /**< Structure used for bit access */ 5242 struct { 5243 uint32_t P:32; /**< bit: 0..31 Additional Interrupt Modes Disable */ 5244 } vec; /**< Structure used for vec access */ 5245 uint32_t reg; /**< Type used for register access */ 5246 } PIO_AIMDR_Type; 5247 #endif 5248 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 5249 5250 #define PIO_AIMDR_OFFSET (0xB4) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Register Offset */ 5251 5252 #define PIO_AIMDR_P0_Pos 0 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5253 #define PIO_AIMDR_P0_Msk (_U_(0x1) << PIO_AIMDR_P0_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5254 #define PIO_AIMDR_P0 PIO_AIMDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P0_Msk instead */ 5255 #define PIO_AIMDR_P1_Pos 1 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5256 #define PIO_AIMDR_P1_Msk (_U_(0x1) << PIO_AIMDR_P1_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5257 #define PIO_AIMDR_P1 PIO_AIMDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P1_Msk instead */ 5258 #define PIO_AIMDR_P2_Pos 2 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5259 #define PIO_AIMDR_P2_Msk (_U_(0x1) << PIO_AIMDR_P2_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5260 #define PIO_AIMDR_P2 PIO_AIMDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P2_Msk instead */ 5261 #define PIO_AIMDR_P3_Pos 3 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5262 #define PIO_AIMDR_P3_Msk (_U_(0x1) << PIO_AIMDR_P3_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5263 #define PIO_AIMDR_P3 PIO_AIMDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P3_Msk instead */ 5264 #define PIO_AIMDR_P4_Pos 4 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5265 #define PIO_AIMDR_P4_Msk (_U_(0x1) << PIO_AIMDR_P4_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5266 #define PIO_AIMDR_P4 PIO_AIMDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P4_Msk instead */ 5267 #define PIO_AIMDR_P5_Pos 5 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5268 #define PIO_AIMDR_P5_Msk (_U_(0x1) << PIO_AIMDR_P5_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5269 #define PIO_AIMDR_P5 PIO_AIMDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P5_Msk instead */ 5270 #define PIO_AIMDR_P6_Pos 6 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5271 #define PIO_AIMDR_P6_Msk (_U_(0x1) << PIO_AIMDR_P6_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5272 #define PIO_AIMDR_P6 PIO_AIMDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P6_Msk instead */ 5273 #define PIO_AIMDR_P7_Pos 7 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5274 #define PIO_AIMDR_P7_Msk (_U_(0x1) << PIO_AIMDR_P7_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5275 #define PIO_AIMDR_P7 PIO_AIMDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P7_Msk instead */ 5276 #define PIO_AIMDR_P8_Pos 8 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5277 #define PIO_AIMDR_P8_Msk (_U_(0x1) << PIO_AIMDR_P8_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5278 #define PIO_AIMDR_P8 PIO_AIMDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P8_Msk instead */ 5279 #define PIO_AIMDR_P9_Pos 9 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5280 #define PIO_AIMDR_P9_Msk (_U_(0x1) << PIO_AIMDR_P9_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5281 #define PIO_AIMDR_P9 PIO_AIMDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P9_Msk instead */ 5282 #define PIO_AIMDR_P10_Pos 10 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5283 #define PIO_AIMDR_P10_Msk (_U_(0x1) << PIO_AIMDR_P10_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5284 #define PIO_AIMDR_P10 PIO_AIMDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P10_Msk instead */ 5285 #define PIO_AIMDR_P11_Pos 11 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5286 #define PIO_AIMDR_P11_Msk (_U_(0x1) << PIO_AIMDR_P11_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5287 #define PIO_AIMDR_P11 PIO_AIMDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P11_Msk instead */ 5288 #define PIO_AIMDR_P12_Pos 12 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5289 #define PIO_AIMDR_P12_Msk (_U_(0x1) << PIO_AIMDR_P12_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5290 #define PIO_AIMDR_P12 PIO_AIMDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P12_Msk instead */ 5291 #define PIO_AIMDR_P13_Pos 13 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5292 #define PIO_AIMDR_P13_Msk (_U_(0x1) << PIO_AIMDR_P13_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5293 #define PIO_AIMDR_P13 PIO_AIMDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P13_Msk instead */ 5294 #define PIO_AIMDR_P14_Pos 14 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5295 #define PIO_AIMDR_P14_Msk (_U_(0x1) << PIO_AIMDR_P14_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5296 #define PIO_AIMDR_P14 PIO_AIMDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P14_Msk instead */ 5297 #define PIO_AIMDR_P15_Pos 15 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5298 #define PIO_AIMDR_P15_Msk (_U_(0x1) << PIO_AIMDR_P15_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5299 #define PIO_AIMDR_P15 PIO_AIMDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P15_Msk instead */ 5300 #define PIO_AIMDR_P16_Pos 16 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5301 #define PIO_AIMDR_P16_Msk (_U_(0x1) << PIO_AIMDR_P16_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5302 #define PIO_AIMDR_P16 PIO_AIMDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P16_Msk instead */ 5303 #define PIO_AIMDR_P17_Pos 17 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5304 #define PIO_AIMDR_P17_Msk (_U_(0x1) << PIO_AIMDR_P17_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5305 #define PIO_AIMDR_P17 PIO_AIMDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P17_Msk instead */ 5306 #define PIO_AIMDR_P18_Pos 18 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5307 #define PIO_AIMDR_P18_Msk (_U_(0x1) << PIO_AIMDR_P18_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5308 #define PIO_AIMDR_P18 PIO_AIMDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P18_Msk instead */ 5309 #define PIO_AIMDR_P19_Pos 19 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5310 #define PIO_AIMDR_P19_Msk (_U_(0x1) << PIO_AIMDR_P19_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5311 #define PIO_AIMDR_P19 PIO_AIMDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P19_Msk instead */ 5312 #define PIO_AIMDR_P20_Pos 20 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5313 #define PIO_AIMDR_P20_Msk (_U_(0x1) << PIO_AIMDR_P20_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5314 #define PIO_AIMDR_P20 PIO_AIMDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P20_Msk instead */ 5315 #define PIO_AIMDR_P21_Pos 21 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5316 #define PIO_AIMDR_P21_Msk (_U_(0x1) << PIO_AIMDR_P21_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5317 #define PIO_AIMDR_P21 PIO_AIMDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P21_Msk instead */ 5318 #define PIO_AIMDR_P22_Pos 22 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5319 #define PIO_AIMDR_P22_Msk (_U_(0x1) << PIO_AIMDR_P22_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5320 #define PIO_AIMDR_P22 PIO_AIMDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P22_Msk instead */ 5321 #define PIO_AIMDR_P23_Pos 23 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5322 #define PIO_AIMDR_P23_Msk (_U_(0x1) << PIO_AIMDR_P23_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5323 #define PIO_AIMDR_P23 PIO_AIMDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P23_Msk instead */ 5324 #define PIO_AIMDR_P24_Pos 24 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5325 #define PIO_AIMDR_P24_Msk (_U_(0x1) << PIO_AIMDR_P24_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5326 #define PIO_AIMDR_P24 PIO_AIMDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P24_Msk instead */ 5327 #define PIO_AIMDR_P25_Pos 25 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5328 #define PIO_AIMDR_P25_Msk (_U_(0x1) << PIO_AIMDR_P25_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5329 #define PIO_AIMDR_P25 PIO_AIMDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P25_Msk instead */ 5330 #define PIO_AIMDR_P26_Pos 26 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5331 #define PIO_AIMDR_P26_Msk (_U_(0x1) << PIO_AIMDR_P26_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5332 #define PIO_AIMDR_P26 PIO_AIMDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P26_Msk instead */ 5333 #define PIO_AIMDR_P27_Pos 27 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5334 #define PIO_AIMDR_P27_Msk (_U_(0x1) << PIO_AIMDR_P27_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5335 #define PIO_AIMDR_P27 PIO_AIMDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P27_Msk instead */ 5336 #define PIO_AIMDR_P28_Pos 28 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5337 #define PIO_AIMDR_P28_Msk (_U_(0x1) << PIO_AIMDR_P28_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5338 #define PIO_AIMDR_P28 PIO_AIMDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P28_Msk instead */ 5339 #define PIO_AIMDR_P29_Pos 29 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5340 #define PIO_AIMDR_P29_Msk (_U_(0x1) << PIO_AIMDR_P29_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5341 #define PIO_AIMDR_P29 PIO_AIMDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P29_Msk instead */ 5342 #define PIO_AIMDR_P30_Pos 30 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5343 #define PIO_AIMDR_P30_Msk (_U_(0x1) << PIO_AIMDR_P30_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5344 #define PIO_AIMDR_P30 PIO_AIMDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P30_Msk instead */ 5345 #define PIO_AIMDR_P31_Pos 31 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ 5346 #define PIO_AIMDR_P31_Msk (_U_(0x1) << PIO_AIMDR_P31_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ 5347 #define PIO_AIMDR_P31 PIO_AIMDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P31_Msk instead */ 5348 #define PIO_AIMDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_AIMDR) Register MASK (Use PIO_AIMDR_Msk instead) */ 5349 #define PIO_AIMDR_Msk _U_(0xFFFFFFFF) /**< (PIO_AIMDR) Register Mask */ 5350 5351 #define PIO_AIMDR_P_Pos 0 /**< (PIO_AIMDR Position) Additional Interrupt Modes Disable */ 5352 #define PIO_AIMDR_P_Msk (_U_(0xFFFFFFFF) << PIO_AIMDR_P_Pos) /**< (PIO_AIMDR Mask) P */ 5353 #define PIO_AIMDR_P(value) (PIO_AIMDR_P_Msk & ((value) << PIO_AIMDR_P_Pos)) 5354 5355 /* -------- PIO_AIMMR : (PIO Offset: 0xb8) (R/ 32) Additional Interrupt Modes Mask Register -------- */ 5356 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 5357 #if COMPONENT_TYPEDEF_STYLE == 'N' 5358 typedef union { 5359 struct { 5360 uint32_t P0:1; /**< bit: 0 IO Line Index */ 5361 uint32_t P1:1; /**< bit: 1 IO Line Index */ 5362 uint32_t P2:1; /**< bit: 2 IO Line Index */ 5363 uint32_t P3:1; /**< bit: 3 IO Line Index */ 5364 uint32_t P4:1; /**< bit: 4 IO Line Index */ 5365 uint32_t P5:1; /**< bit: 5 IO Line Index */ 5366 uint32_t P6:1; /**< bit: 6 IO Line Index */ 5367 uint32_t P7:1; /**< bit: 7 IO Line Index */ 5368 uint32_t P8:1; /**< bit: 8 IO Line Index */ 5369 uint32_t P9:1; /**< bit: 9 IO Line Index */ 5370 uint32_t P10:1; /**< bit: 10 IO Line Index */ 5371 uint32_t P11:1; /**< bit: 11 IO Line Index */ 5372 uint32_t P12:1; /**< bit: 12 IO Line Index */ 5373 uint32_t P13:1; /**< bit: 13 IO Line Index */ 5374 uint32_t P14:1; /**< bit: 14 IO Line Index */ 5375 uint32_t P15:1; /**< bit: 15 IO Line Index */ 5376 uint32_t P16:1; /**< bit: 16 IO Line Index */ 5377 uint32_t P17:1; /**< bit: 17 IO Line Index */ 5378 uint32_t P18:1; /**< bit: 18 IO Line Index */ 5379 uint32_t P19:1; /**< bit: 19 IO Line Index */ 5380 uint32_t P20:1; /**< bit: 20 IO Line Index */ 5381 uint32_t P21:1; /**< bit: 21 IO Line Index */ 5382 uint32_t P22:1; /**< bit: 22 IO Line Index */ 5383 uint32_t P23:1; /**< bit: 23 IO Line Index */ 5384 uint32_t P24:1; /**< bit: 24 IO Line Index */ 5385 uint32_t P25:1; /**< bit: 25 IO Line Index */ 5386 uint32_t P26:1; /**< bit: 26 IO Line Index */ 5387 uint32_t P27:1; /**< bit: 27 IO Line Index */ 5388 uint32_t P28:1; /**< bit: 28 IO Line Index */ 5389 uint32_t P29:1; /**< bit: 29 IO Line Index */ 5390 uint32_t P30:1; /**< bit: 30 IO Line Index */ 5391 uint32_t P31:1; /**< bit: 31 IO Line Index */ 5392 } bit; /**< Structure used for bit access */ 5393 struct { 5394 uint32_t P:32; /**< bit: 0..31 IO Line Index */ 5395 } vec; /**< Structure used for vec access */ 5396 uint32_t reg; /**< Type used for register access */ 5397 } PIO_AIMMR_Type; 5398 #endif 5399 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 5400 5401 #define PIO_AIMMR_OFFSET (0xB8) /**< (PIO_AIMMR) Additional Interrupt Modes Mask Register Offset */ 5402 5403 #define PIO_AIMMR_P0_Pos 0 /**< (PIO_AIMMR) IO Line Index Position */ 5404 #define PIO_AIMMR_P0_Msk (_U_(0x1) << PIO_AIMMR_P0_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5405 #define PIO_AIMMR_P0 PIO_AIMMR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P0_Msk instead */ 5406 #define PIO_AIMMR_P1_Pos 1 /**< (PIO_AIMMR) IO Line Index Position */ 5407 #define PIO_AIMMR_P1_Msk (_U_(0x1) << PIO_AIMMR_P1_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5408 #define PIO_AIMMR_P1 PIO_AIMMR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P1_Msk instead */ 5409 #define PIO_AIMMR_P2_Pos 2 /**< (PIO_AIMMR) IO Line Index Position */ 5410 #define PIO_AIMMR_P2_Msk (_U_(0x1) << PIO_AIMMR_P2_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5411 #define PIO_AIMMR_P2 PIO_AIMMR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P2_Msk instead */ 5412 #define PIO_AIMMR_P3_Pos 3 /**< (PIO_AIMMR) IO Line Index Position */ 5413 #define PIO_AIMMR_P3_Msk (_U_(0x1) << PIO_AIMMR_P3_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5414 #define PIO_AIMMR_P3 PIO_AIMMR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P3_Msk instead */ 5415 #define PIO_AIMMR_P4_Pos 4 /**< (PIO_AIMMR) IO Line Index Position */ 5416 #define PIO_AIMMR_P4_Msk (_U_(0x1) << PIO_AIMMR_P4_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5417 #define PIO_AIMMR_P4 PIO_AIMMR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P4_Msk instead */ 5418 #define PIO_AIMMR_P5_Pos 5 /**< (PIO_AIMMR) IO Line Index Position */ 5419 #define PIO_AIMMR_P5_Msk (_U_(0x1) << PIO_AIMMR_P5_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5420 #define PIO_AIMMR_P5 PIO_AIMMR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P5_Msk instead */ 5421 #define PIO_AIMMR_P6_Pos 6 /**< (PIO_AIMMR) IO Line Index Position */ 5422 #define PIO_AIMMR_P6_Msk (_U_(0x1) << PIO_AIMMR_P6_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5423 #define PIO_AIMMR_P6 PIO_AIMMR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P6_Msk instead */ 5424 #define PIO_AIMMR_P7_Pos 7 /**< (PIO_AIMMR) IO Line Index Position */ 5425 #define PIO_AIMMR_P7_Msk (_U_(0x1) << PIO_AIMMR_P7_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5426 #define PIO_AIMMR_P7 PIO_AIMMR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P7_Msk instead */ 5427 #define PIO_AIMMR_P8_Pos 8 /**< (PIO_AIMMR) IO Line Index Position */ 5428 #define PIO_AIMMR_P8_Msk (_U_(0x1) << PIO_AIMMR_P8_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5429 #define PIO_AIMMR_P8 PIO_AIMMR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P8_Msk instead */ 5430 #define PIO_AIMMR_P9_Pos 9 /**< (PIO_AIMMR) IO Line Index Position */ 5431 #define PIO_AIMMR_P9_Msk (_U_(0x1) << PIO_AIMMR_P9_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5432 #define PIO_AIMMR_P9 PIO_AIMMR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P9_Msk instead */ 5433 #define PIO_AIMMR_P10_Pos 10 /**< (PIO_AIMMR) IO Line Index Position */ 5434 #define PIO_AIMMR_P10_Msk (_U_(0x1) << PIO_AIMMR_P10_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5435 #define PIO_AIMMR_P10 PIO_AIMMR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P10_Msk instead */ 5436 #define PIO_AIMMR_P11_Pos 11 /**< (PIO_AIMMR) IO Line Index Position */ 5437 #define PIO_AIMMR_P11_Msk (_U_(0x1) << PIO_AIMMR_P11_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5438 #define PIO_AIMMR_P11 PIO_AIMMR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P11_Msk instead */ 5439 #define PIO_AIMMR_P12_Pos 12 /**< (PIO_AIMMR) IO Line Index Position */ 5440 #define PIO_AIMMR_P12_Msk (_U_(0x1) << PIO_AIMMR_P12_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5441 #define PIO_AIMMR_P12 PIO_AIMMR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P12_Msk instead */ 5442 #define PIO_AIMMR_P13_Pos 13 /**< (PIO_AIMMR) IO Line Index Position */ 5443 #define PIO_AIMMR_P13_Msk (_U_(0x1) << PIO_AIMMR_P13_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5444 #define PIO_AIMMR_P13 PIO_AIMMR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P13_Msk instead */ 5445 #define PIO_AIMMR_P14_Pos 14 /**< (PIO_AIMMR) IO Line Index Position */ 5446 #define PIO_AIMMR_P14_Msk (_U_(0x1) << PIO_AIMMR_P14_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5447 #define PIO_AIMMR_P14 PIO_AIMMR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P14_Msk instead */ 5448 #define PIO_AIMMR_P15_Pos 15 /**< (PIO_AIMMR) IO Line Index Position */ 5449 #define PIO_AIMMR_P15_Msk (_U_(0x1) << PIO_AIMMR_P15_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5450 #define PIO_AIMMR_P15 PIO_AIMMR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P15_Msk instead */ 5451 #define PIO_AIMMR_P16_Pos 16 /**< (PIO_AIMMR) IO Line Index Position */ 5452 #define PIO_AIMMR_P16_Msk (_U_(0x1) << PIO_AIMMR_P16_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5453 #define PIO_AIMMR_P16 PIO_AIMMR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P16_Msk instead */ 5454 #define PIO_AIMMR_P17_Pos 17 /**< (PIO_AIMMR) IO Line Index Position */ 5455 #define PIO_AIMMR_P17_Msk (_U_(0x1) << PIO_AIMMR_P17_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5456 #define PIO_AIMMR_P17 PIO_AIMMR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P17_Msk instead */ 5457 #define PIO_AIMMR_P18_Pos 18 /**< (PIO_AIMMR) IO Line Index Position */ 5458 #define PIO_AIMMR_P18_Msk (_U_(0x1) << PIO_AIMMR_P18_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5459 #define PIO_AIMMR_P18 PIO_AIMMR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P18_Msk instead */ 5460 #define PIO_AIMMR_P19_Pos 19 /**< (PIO_AIMMR) IO Line Index Position */ 5461 #define PIO_AIMMR_P19_Msk (_U_(0x1) << PIO_AIMMR_P19_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5462 #define PIO_AIMMR_P19 PIO_AIMMR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P19_Msk instead */ 5463 #define PIO_AIMMR_P20_Pos 20 /**< (PIO_AIMMR) IO Line Index Position */ 5464 #define PIO_AIMMR_P20_Msk (_U_(0x1) << PIO_AIMMR_P20_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5465 #define PIO_AIMMR_P20 PIO_AIMMR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P20_Msk instead */ 5466 #define PIO_AIMMR_P21_Pos 21 /**< (PIO_AIMMR) IO Line Index Position */ 5467 #define PIO_AIMMR_P21_Msk (_U_(0x1) << PIO_AIMMR_P21_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5468 #define PIO_AIMMR_P21 PIO_AIMMR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P21_Msk instead */ 5469 #define PIO_AIMMR_P22_Pos 22 /**< (PIO_AIMMR) IO Line Index Position */ 5470 #define PIO_AIMMR_P22_Msk (_U_(0x1) << PIO_AIMMR_P22_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5471 #define PIO_AIMMR_P22 PIO_AIMMR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P22_Msk instead */ 5472 #define PIO_AIMMR_P23_Pos 23 /**< (PIO_AIMMR) IO Line Index Position */ 5473 #define PIO_AIMMR_P23_Msk (_U_(0x1) << PIO_AIMMR_P23_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5474 #define PIO_AIMMR_P23 PIO_AIMMR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P23_Msk instead */ 5475 #define PIO_AIMMR_P24_Pos 24 /**< (PIO_AIMMR) IO Line Index Position */ 5476 #define PIO_AIMMR_P24_Msk (_U_(0x1) << PIO_AIMMR_P24_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5477 #define PIO_AIMMR_P24 PIO_AIMMR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P24_Msk instead */ 5478 #define PIO_AIMMR_P25_Pos 25 /**< (PIO_AIMMR) IO Line Index Position */ 5479 #define PIO_AIMMR_P25_Msk (_U_(0x1) << PIO_AIMMR_P25_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5480 #define PIO_AIMMR_P25 PIO_AIMMR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P25_Msk instead */ 5481 #define PIO_AIMMR_P26_Pos 26 /**< (PIO_AIMMR) IO Line Index Position */ 5482 #define PIO_AIMMR_P26_Msk (_U_(0x1) << PIO_AIMMR_P26_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5483 #define PIO_AIMMR_P26 PIO_AIMMR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P26_Msk instead */ 5484 #define PIO_AIMMR_P27_Pos 27 /**< (PIO_AIMMR) IO Line Index Position */ 5485 #define PIO_AIMMR_P27_Msk (_U_(0x1) << PIO_AIMMR_P27_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5486 #define PIO_AIMMR_P27 PIO_AIMMR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P27_Msk instead */ 5487 #define PIO_AIMMR_P28_Pos 28 /**< (PIO_AIMMR) IO Line Index Position */ 5488 #define PIO_AIMMR_P28_Msk (_U_(0x1) << PIO_AIMMR_P28_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5489 #define PIO_AIMMR_P28 PIO_AIMMR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P28_Msk instead */ 5490 #define PIO_AIMMR_P29_Pos 29 /**< (PIO_AIMMR) IO Line Index Position */ 5491 #define PIO_AIMMR_P29_Msk (_U_(0x1) << PIO_AIMMR_P29_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5492 #define PIO_AIMMR_P29 PIO_AIMMR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P29_Msk instead */ 5493 #define PIO_AIMMR_P30_Pos 30 /**< (PIO_AIMMR) IO Line Index Position */ 5494 #define PIO_AIMMR_P30_Msk (_U_(0x1) << PIO_AIMMR_P30_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5495 #define PIO_AIMMR_P30 PIO_AIMMR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P30_Msk instead */ 5496 #define PIO_AIMMR_P31_Pos 31 /**< (PIO_AIMMR) IO Line Index Position */ 5497 #define PIO_AIMMR_P31_Msk (_U_(0x1) << PIO_AIMMR_P31_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ 5498 #define PIO_AIMMR_P31 PIO_AIMMR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P31_Msk instead */ 5499 #define PIO_AIMMR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_AIMMR) Register MASK (Use PIO_AIMMR_Msk instead) */ 5500 #define PIO_AIMMR_Msk _U_(0xFFFFFFFF) /**< (PIO_AIMMR) Register Mask */ 5501 5502 #define PIO_AIMMR_P_Pos 0 /**< (PIO_AIMMR Position) IO Line Index */ 5503 #define PIO_AIMMR_P_Msk (_U_(0xFFFFFFFF) << PIO_AIMMR_P_Pos) /**< (PIO_AIMMR Mask) P */ 5504 #define PIO_AIMMR_P(value) (PIO_AIMMR_P_Msk & ((value) << PIO_AIMMR_P_Pos)) 5505 5506 /* -------- PIO_ESR : (PIO Offset: 0xc0) (/W 32) Edge Select Register -------- */ 5507 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 5508 #if COMPONENT_TYPEDEF_STYLE == 'N' 5509 typedef union { 5510 struct { 5511 uint32_t P0:1; /**< bit: 0 Edge Interrupt Selection */ 5512 uint32_t P1:1; /**< bit: 1 Edge Interrupt Selection */ 5513 uint32_t P2:1; /**< bit: 2 Edge Interrupt Selection */ 5514 uint32_t P3:1; /**< bit: 3 Edge Interrupt Selection */ 5515 uint32_t P4:1; /**< bit: 4 Edge Interrupt Selection */ 5516 uint32_t P5:1; /**< bit: 5 Edge Interrupt Selection */ 5517 uint32_t P6:1; /**< bit: 6 Edge Interrupt Selection */ 5518 uint32_t P7:1; /**< bit: 7 Edge Interrupt Selection */ 5519 uint32_t P8:1; /**< bit: 8 Edge Interrupt Selection */ 5520 uint32_t P9:1; /**< bit: 9 Edge Interrupt Selection */ 5521 uint32_t P10:1; /**< bit: 10 Edge Interrupt Selection */ 5522 uint32_t P11:1; /**< bit: 11 Edge Interrupt Selection */ 5523 uint32_t P12:1; /**< bit: 12 Edge Interrupt Selection */ 5524 uint32_t P13:1; /**< bit: 13 Edge Interrupt Selection */ 5525 uint32_t P14:1; /**< bit: 14 Edge Interrupt Selection */ 5526 uint32_t P15:1; /**< bit: 15 Edge Interrupt Selection */ 5527 uint32_t P16:1; /**< bit: 16 Edge Interrupt Selection */ 5528 uint32_t P17:1; /**< bit: 17 Edge Interrupt Selection */ 5529 uint32_t P18:1; /**< bit: 18 Edge Interrupt Selection */ 5530 uint32_t P19:1; /**< bit: 19 Edge Interrupt Selection */ 5531 uint32_t P20:1; /**< bit: 20 Edge Interrupt Selection */ 5532 uint32_t P21:1; /**< bit: 21 Edge Interrupt Selection */ 5533 uint32_t P22:1; /**< bit: 22 Edge Interrupt Selection */ 5534 uint32_t P23:1; /**< bit: 23 Edge Interrupt Selection */ 5535 uint32_t P24:1; /**< bit: 24 Edge Interrupt Selection */ 5536 uint32_t P25:1; /**< bit: 25 Edge Interrupt Selection */ 5537 uint32_t P26:1; /**< bit: 26 Edge Interrupt Selection */ 5538 uint32_t P27:1; /**< bit: 27 Edge Interrupt Selection */ 5539 uint32_t P28:1; /**< bit: 28 Edge Interrupt Selection */ 5540 uint32_t P29:1; /**< bit: 29 Edge Interrupt Selection */ 5541 uint32_t P30:1; /**< bit: 30 Edge Interrupt Selection */ 5542 uint32_t P31:1; /**< bit: 31 Edge Interrupt Selection */ 5543 } bit; /**< Structure used for bit access */ 5544 struct { 5545 uint32_t P:32; /**< bit: 0..31 Edge Interrupt Selection */ 5546 } vec; /**< Structure used for vec access */ 5547 uint32_t reg; /**< Type used for register access */ 5548 } PIO_ESR_Type; 5549 #endif 5550 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 5551 5552 #define PIO_ESR_OFFSET (0xC0) /**< (PIO_ESR) Edge Select Register Offset */ 5553 5554 #define PIO_ESR_P0_Pos 0 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5555 #define PIO_ESR_P0_Msk (_U_(0x1) << PIO_ESR_P0_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5556 #define PIO_ESR_P0 PIO_ESR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P0_Msk instead */ 5557 #define PIO_ESR_P1_Pos 1 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5558 #define PIO_ESR_P1_Msk (_U_(0x1) << PIO_ESR_P1_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5559 #define PIO_ESR_P1 PIO_ESR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P1_Msk instead */ 5560 #define PIO_ESR_P2_Pos 2 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5561 #define PIO_ESR_P2_Msk (_U_(0x1) << PIO_ESR_P2_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5562 #define PIO_ESR_P2 PIO_ESR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P2_Msk instead */ 5563 #define PIO_ESR_P3_Pos 3 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5564 #define PIO_ESR_P3_Msk (_U_(0x1) << PIO_ESR_P3_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5565 #define PIO_ESR_P3 PIO_ESR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P3_Msk instead */ 5566 #define PIO_ESR_P4_Pos 4 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5567 #define PIO_ESR_P4_Msk (_U_(0x1) << PIO_ESR_P4_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5568 #define PIO_ESR_P4 PIO_ESR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P4_Msk instead */ 5569 #define PIO_ESR_P5_Pos 5 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5570 #define PIO_ESR_P5_Msk (_U_(0x1) << PIO_ESR_P5_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5571 #define PIO_ESR_P5 PIO_ESR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P5_Msk instead */ 5572 #define PIO_ESR_P6_Pos 6 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5573 #define PIO_ESR_P6_Msk (_U_(0x1) << PIO_ESR_P6_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5574 #define PIO_ESR_P6 PIO_ESR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P6_Msk instead */ 5575 #define PIO_ESR_P7_Pos 7 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5576 #define PIO_ESR_P7_Msk (_U_(0x1) << PIO_ESR_P7_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5577 #define PIO_ESR_P7 PIO_ESR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P7_Msk instead */ 5578 #define PIO_ESR_P8_Pos 8 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5579 #define PIO_ESR_P8_Msk (_U_(0x1) << PIO_ESR_P8_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5580 #define PIO_ESR_P8 PIO_ESR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P8_Msk instead */ 5581 #define PIO_ESR_P9_Pos 9 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5582 #define PIO_ESR_P9_Msk (_U_(0x1) << PIO_ESR_P9_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5583 #define PIO_ESR_P9 PIO_ESR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P9_Msk instead */ 5584 #define PIO_ESR_P10_Pos 10 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5585 #define PIO_ESR_P10_Msk (_U_(0x1) << PIO_ESR_P10_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5586 #define PIO_ESR_P10 PIO_ESR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P10_Msk instead */ 5587 #define PIO_ESR_P11_Pos 11 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5588 #define PIO_ESR_P11_Msk (_U_(0x1) << PIO_ESR_P11_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5589 #define PIO_ESR_P11 PIO_ESR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P11_Msk instead */ 5590 #define PIO_ESR_P12_Pos 12 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5591 #define PIO_ESR_P12_Msk (_U_(0x1) << PIO_ESR_P12_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5592 #define PIO_ESR_P12 PIO_ESR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P12_Msk instead */ 5593 #define PIO_ESR_P13_Pos 13 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5594 #define PIO_ESR_P13_Msk (_U_(0x1) << PIO_ESR_P13_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5595 #define PIO_ESR_P13 PIO_ESR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P13_Msk instead */ 5596 #define PIO_ESR_P14_Pos 14 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5597 #define PIO_ESR_P14_Msk (_U_(0x1) << PIO_ESR_P14_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5598 #define PIO_ESR_P14 PIO_ESR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P14_Msk instead */ 5599 #define PIO_ESR_P15_Pos 15 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5600 #define PIO_ESR_P15_Msk (_U_(0x1) << PIO_ESR_P15_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5601 #define PIO_ESR_P15 PIO_ESR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P15_Msk instead */ 5602 #define PIO_ESR_P16_Pos 16 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5603 #define PIO_ESR_P16_Msk (_U_(0x1) << PIO_ESR_P16_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5604 #define PIO_ESR_P16 PIO_ESR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P16_Msk instead */ 5605 #define PIO_ESR_P17_Pos 17 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5606 #define PIO_ESR_P17_Msk (_U_(0x1) << PIO_ESR_P17_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5607 #define PIO_ESR_P17 PIO_ESR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P17_Msk instead */ 5608 #define PIO_ESR_P18_Pos 18 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5609 #define PIO_ESR_P18_Msk (_U_(0x1) << PIO_ESR_P18_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5610 #define PIO_ESR_P18 PIO_ESR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P18_Msk instead */ 5611 #define PIO_ESR_P19_Pos 19 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5612 #define PIO_ESR_P19_Msk (_U_(0x1) << PIO_ESR_P19_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5613 #define PIO_ESR_P19 PIO_ESR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P19_Msk instead */ 5614 #define PIO_ESR_P20_Pos 20 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5615 #define PIO_ESR_P20_Msk (_U_(0x1) << PIO_ESR_P20_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5616 #define PIO_ESR_P20 PIO_ESR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P20_Msk instead */ 5617 #define PIO_ESR_P21_Pos 21 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5618 #define PIO_ESR_P21_Msk (_U_(0x1) << PIO_ESR_P21_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5619 #define PIO_ESR_P21 PIO_ESR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P21_Msk instead */ 5620 #define PIO_ESR_P22_Pos 22 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5621 #define PIO_ESR_P22_Msk (_U_(0x1) << PIO_ESR_P22_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5622 #define PIO_ESR_P22 PIO_ESR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P22_Msk instead */ 5623 #define PIO_ESR_P23_Pos 23 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5624 #define PIO_ESR_P23_Msk (_U_(0x1) << PIO_ESR_P23_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5625 #define PIO_ESR_P23 PIO_ESR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P23_Msk instead */ 5626 #define PIO_ESR_P24_Pos 24 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5627 #define PIO_ESR_P24_Msk (_U_(0x1) << PIO_ESR_P24_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5628 #define PIO_ESR_P24 PIO_ESR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P24_Msk instead */ 5629 #define PIO_ESR_P25_Pos 25 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5630 #define PIO_ESR_P25_Msk (_U_(0x1) << PIO_ESR_P25_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5631 #define PIO_ESR_P25 PIO_ESR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P25_Msk instead */ 5632 #define PIO_ESR_P26_Pos 26 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5633 #define PIO_ESR_P26_Msk (_U_(0x1) << PIO_ESR_P26_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5634 #define PIO_ESR_P26 PIO_ESR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P26_Msk instead */ 5635 #define PIO_ESR_P27_Pos 27 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5636 #define PIO_ESR_P27_Msk (_U_(0x1) << PIO_ESR_P27_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5637 #define PIO_ESR_P27 PIO_ESR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P27_Msk instead */ 5638 #define PIO_ESR_P28_Pos 28 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5639 #define PIO_ESR_P28_Msk (_U_(0x1) << PIO_ESR_P28_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5640 #define PIO_ESR_P28 PIO_ESR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P28_Msk instead */ 5641 #define PIO_ESR_P29_Pos 29 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5642 #define PIO_ESR_P29_Msk (_U_(0x1) << PIO_ESR_P29_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5643 #define PIO_ESR_P29 PIO_ESR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P29_Msk instead */ 5644 #define PIO_ESR_P30_Pos 30 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5645 #define PIO_ESR_P30_Msk (_U_(0x1) << PIO_ESR_P30_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5646 #define PIO_ESR_P30 PIO_ESR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P30_Msk instead */ 5647 #define PIO_ESR_P31_Pos 31 /**< (PIO_ESR) Edge Interrupt Selection Position */ 5648 #define PIO_ESR_P31_Msk (_U_(0x1) << PIO_ESR_P31_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ 5649 #define PIO_ESR_P31 PIO_ESR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P31_Msk instead */ 5650 #define PIO_ESR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_ESR) Register MASK (Use PIO_ESR_Msk instead) */ 5651 #define PIO_ESR_Msk _U_(0xFFFFFFFF) /**< (PIO_ESR) Register Mask */ 5652 5653 #define PIO_ESR_P_Pos 0 /**< (PIO_ESR Position) Edge Interrupt Selection */ 5654 #define PIO_ESR_P_Msk (_U_(0xFFFFFFFF) << PIO_ESR_P_Pos) /**< (PIO_ESR Mask) P */ 5655 #define PIO_ESR_P(value) (PIO_ESR_P_Msk & ((value) << PIO_ESR_P_Pos)) 5656 5657 /* -------- PIO_LSR : (PIO Offset: 0xc4) (/W 32) Level Select Register -------- */ 5658 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 5659 #if COMPONENT_TYPEDEF_STYLE == 'N' 5660 typedef union { 5661 struct { 5662 uint32_t P0:1; /**< bit: 0 Level Interrupt Selection */ 5663 uint32_t P1:1; /**< bit: 1 Level Interrupt Selection */ 5664 uint32_t P2:1; /**< bit: 2 Level Interrupt Selection */ 5665 uint32_t P3:1; /**< bit: 3 Level Interrupt Selection */ 5666 uint32_t P4:1; /**< bit: 4 Level Interrupt Selection */ 5667 uint32_t P5:1; /**< bit: 5 Level Interrupt Selection */ 5668 uint32_t P6:1; /**< bit: 6 Level Interrupt Selection */ 5669 uint32_t P7:1; /**< bit: 7 Level Interrupt Selection */ 5670 uint32_t P8:1; /**< bit: 8 Level Interrupt Selection */ 5671 uint32_t P9:1; /**< bit: 9 Level Interrupt Selection */ 5672 uint32_t P10:1; /**< bit: 10 Level Interrupt Selection */ 5673 uint32_t P11:1; /**< bit: 11 Level Interrupt Selection */ 5674 uint32_t P12:1; /**< bit: 12 Level Interrupt Selection */ 5675 uint32_t P13:1; /**< bit: 13 Level Interrupt Selection */ 5676 uint32_t P14:1; /**< bit: 14 Level Interrupt Selection */ 5677 uint32_t P15:1; /**< bit: 15 Level Interrupt Selection */ 5678 uint32_t P16:1; /**< bit: 16 Level Interrupt Selection */ 5679 uint32_t P17:1; /**< bit: 17 Level Interrupt Selection */ 5680 uint32_t P18:1; /**< bit: 18 Level Interrupt Selection */ 5681 uint32_t P19:1; /**< bit: 19 Level Interrupt Selection */ 5682 uint32_t P20:1; /**< bit: 20 Level Interrupt Selection */ 5683 uint32_t P21:1; /**< bit: 21 Level Interrupt Selection */ 5684 uint32_t P22:1; /**< bit: 22 Level Interrupt Selection */ 5685 uint32_t P23:1; /**< bit: 23 Level Interrupt Selection */ 5686 uint32_t P24:1; /**< bit: 24 Level Interrupt Selection */ 5687 uint32_t P25:1; /**< bit: 25 Level Interrupt Selection */ 5688 uint32_t P26:1; /**< bit: 26 Level Interrupt Selection */ 5689 uint32_t P27:1; /**< bit: 27 Level Interrupt Selection */ 5690 uint32_t P28:1; /**< bit: 28 Level Interrupt Selection */ 5691 uint32_t P29:1; /**< bit: 29 Level Interrupt Selection */ 5692 uint32_t P30:1; /**< bit: 30 Level Interrupt Selection */ 5693 uint32_t P31:1; /**< bit: 31 Level Interrupt Selection */ 5694 } bit; /**< Structure used for bit access */ 5695 struct { 5696 uint32_t P:32; /**< bit: 0..31 Level Interrupt Selection */ 5697 } vec; /**< Structure used for vec access */ 5698 uint32_t reg; /**< Type used for register access */ 5699 } PIO_LSR_Type; 5700 #endif 5701 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 5702 5703 #define PIO_LSR_OFFSET (0xC4) /**< (PIO_LSR) Level Select Register Offset */ 5704 5705 #define PIO_LSR_P0_Pos 0 /**< (PIO_LSR) Level Interrupt Selection Position */ 5706 #define PIO_LSR_P0_Msk (_U_(0x1) << PIO_LSR_P0_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5707 #define PIO_LSR_P0 PIO_LSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P0_Msk instead */ 5708 #define PIO_LSR_P1_Pos 1 /**< (PIO_LSR) Level Interrupt Selection Position */ 5709 #define PIO_LSR_P1_Msk (_U_(0x1) << PIO_LSR_P1_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5710 #define PIO_LSR_P1 PIO_LSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P1_Msk instead */ 5711 #define PIO_LSR_P2_Pos 2 /**< (PIO_LSR) Level Interrupt Selection Position */ 5712 #define PIO_LSR_P2_Msk (_U_(0x1) << PIO_LSR_P2_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5713 #define PIO_LSR_P2 PIO_LSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P2_Msk instead */ 5714 #define PIO_LSR_P3_Pos 3 /**< (PIO_LSR) Level Interrupt Selection Position */ 5715 #define PIO_LSR_P3_Msk (_U_(0x1) << PIO_LSR_P3_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5716 #define PIO_LSR_P3 PIO_LSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P3_Msk instead */ 5717 #define PIO_LSR_P4_Pos 4 /**< (PIO_LSR) Level Interrupt Selection Position */ 5718 #define PIO_LSR_P4_Msk (_U_(0x1) << PIO_LSR_P4_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5719 #define PIO_LSR_P4 PIO_LSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P4_Msk instead */ 5720 #define PIO_LSR_P5_Pos 5 /**< (PIO_LSR) Level Interrupt Selection Position */ 5721 #define PIO_LSR_P5_Msk (_U_(0x1) << PIO_LSR_P5_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5722 #define PIO_LSR_P5 PIO_LSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P5_Msk instead */ 5723 #define PIO_LSR_P6_Pos 6 /**< (PIO_LSR) Level Interrupt Selection Position */ 5724 #define PIO_LSR_P6_Msk (_U_(0x1) << PIO_LSR_P6_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5725 #define PIO_LSR_P6 PIO_LSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P6_Msk instead */ 5726 #define PIO_LSR_P7_Pos 7 /**< (PIO_LSR) Level Interrupt Selection Position */ 5727 #define PIO_LSR_P7_Msk (_U_(0x1) << PIO_LSR_P7_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5728 #define PIO_LSR_P7 PIO_LSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P7_Msk instead */ 5729 #define PIO_LSR_P8_Pos 8 /**< (PIO_LSR) Level Interrupt Selection Position */ 5730 #define PIO_LSR_P8_Msk (_U_(0x1) << PIO_LSR_P8_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5731 #define PIO_LSR_P8 PIO_LSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P8_Msk instead */ 5732 #define PIO_LSR_P9_Pos 9 /**< (PIO_LSR) Level Interrupt Selection Position */ 5733 #define PIO_LSR_P9_Msk (_U_(0x1) << PIO_LSR_P9_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5734 #define PIO_LSR_P9 PIO_LSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P9_Msk instead */ 5735 #define PIO_LSR_P10_Pos 10 /**< (PIO_LSR) Level Interrupt Selection Position */ 5736 #define PIO_LSR_P10_Msk (_U_(0x1) << PIO_LSR_P10_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5737 #define PIO_LSR_P10 PIO_LSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P10_Msk instead */ 5738 #define PIO_LSR_P11_Pos 11 /**< (PIO_LSR) Level Interrupt Selection Position */ 5739 #define PIO_LSR_P11_Msk (_U_(0x1) << PIO_LSR_P11_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5740 #define PIO_LSR_P11 PIO_LSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P11_Msk instead */ 5741 #define PIO_LSR_P12_Pos 12 /**< (PIO_LSR) Level Interrupt Selection Position */ 5742 #define PIO_LSR_P12_Msk (_U_(0x1) << PIO_LSR_P12_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5743 #define PIO_LSR_P12 PIO_LSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P12_Msk instead */ 5744 #define PIO_LSR_P13_Pos 13 /**< (PIO_LSR) Level Interrupt Selection Position */ 5745 #define PIO_LSR_P13_Msk (_U_(0x1) << PIO_LSR_P13_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5746 #define PIO_LSR_P13 PIO_LSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P13_Msk instead */ 5747 #define PIO_LSR_P14_Pos 14 /**< (PIO_LSR) Level Interrupt Selection Position */ 5748 #define PIO_LSR_P14_Msk (_U_(0x1) << PIO_LSR_P14_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5749 #define PIO_LSR_P14 PIO_LSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P14_Msk instead */ 5750 #define PIO_LSR_P15_Pos 15 /**< (PIO_LSR) Level Interrupt Selection Position */ 5751 #define PIO_LSR_P15_Msk (_U_(0x1) << PIO_LSR_P15_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5752 #define PIO_LSR_P15 PIO_LSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P15_Msk instead */ 5753 #define PIO_LSR_P16_Pos 16 /**< (PIO_LSR) Level Interrupt Selection Position */ 5754 #define PIO_LSR_P16_Msk (_U_(0x1) << PIO_LSR_P16_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5755 #define PIO_LSR_P16 PIO_LSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P16_Msk instead */ 5756 #define PIO_LSR_P17_Pos 17 /**< (PIO_LSR) Level Interrupt Selection Position */ 5757 #define PIO_LSR_P17_Msk (_U_(0x1) << PIO_LSR_P17_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5758 #define PIO_LSR_P17 PIO_LSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P17_Msk instead */ 5759 #define PIO_LSR_P18_Pos 18 /**< (PIO_LSR) Level Interrupt Selection Position */ 5760 #define PIO_LSR_P18_Msk (_U_(0x1) << PIO_LSR_P18_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5761 #define PIO_LSR_P18 PIO_LSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P18_Msk instead */ 5762 #define PIO_LSR_P19_Pos 19 /**< (PIO_LSR) Level Interrupt Selection Position */ 5763 #define PIO_LSR_P19_Msk (_U_(0x1) << PIO_LSR_P19_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5764 #define PIO_LSR_P19 PIO_LSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P19_Msk instead */ 5765 #define PIO_LSR_P20_Pos 20 /**< (PIO_LSR) Level Interrupt Selection Position */ 5766 #define PIO_LSR_P20_Msk (_U_(0x1) << PIO_LSR_P20_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5767 #define PIO_LSR_P20 PIO_LSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P20_Msk instead */ 5768 #define PIO_LSR_P21_Pos 21 /**< (PIO_LSR) Level Interrupt Selection Position */ 5769 #define PIO_LSR_P21_Msk (_U_(0x1) << PIO_LSR_P21_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5770 #define PIO_LSR_P21 PIO_LSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P21_Msk instead */ 5771 #define PIO_LSR_P22_Pos 22 /**< (PIO_LSR) Level Interrupt Selection Position */ 5772 #define PIO_LSR_P22_Msk (_U_(0x1) << PIO_LSR_P22_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5773 #define PIO_LSR_P22 PIO_LSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P22_Msk instead */ 5774 #define PIO_LSR_P23_Pos 23 /**< (PIO_LSR) Level Interrupt Selection Position */ 5775 #define PIO_LSR_P23_Msk (_U_(0x1) << PIO_LSR_P23_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5776 #define PIO_LSR_P23 PIO_LSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P23_Msk instead */ 5777 #define PIO_LSR_P24_Pos 24 /**< (PIO_LSR) Level Interrupt Selection Position */ 5778 #define PIO_LSR_P24_Msk (_U_(0x1) << PIO_LSR_P24_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5779 #define PIO_LSR_P24 PIO_LSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P24_Msk instead */ 5780 #define PIO_LSR_P25_Pos 25 /**< (PIO_LSR) Level Interrupt Selection Position */ 5781 #define PIO_LSR_P25_Msk (_U_(0x1) << PIO_LSR_P25_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5782 #define PIO_LSR_P25 PIO_LSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P25_Msk instead */ 5783 #define PIO_LSR_P26_Pos 26 /**< (PIO_LSR) Level Interrupt Selection Position */ 5784 #define PIO_LSR_P26_Msk (_U_(0x1) << PIO_LSR_P26_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5785 #define PIO_LSR_P26 PIO_LSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P26_Msk instead */ 5786 #define PIO_LSR_P27_Pos 27 /**< (PIO_LSR) Level Interrupt Selection Position */ 5787 #define PIO_LSR_P27_Msk (_U_(0x1) << PIO_LSR_P27_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5788 #define PIO_LSR_P27 PIO_LSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P27_Msk instead */ 5789 #define PIO_LSR_P28_Pos 28 /**< (PIO_LSR) Level Interrupt Selection Position */ 5790 #define PIO_LSR_P28_Msk (_U_(0x1) << PIO_LSR_P28_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5791 #define PIO_LSR_P28 PIO_LSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P28_Msk instead */ 5792 #define PIO_LSR_P29_Pos 29 /**< (PIO_LSR) Level Interrupt Selection Position */ 5793 #define PIO_LSR_P29_Msk (_U_(0x1) << PIO_LSR_P29_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5794 #define PIO_LSR_P29 PIO_LSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P29_Msk instead */ 5795 #define PIO_LSR_P30_Pos 30 /**< (PIO_LSR) Level Interrupt Selection Position */ 5796 #define PIO_LSR_P30_Msk (_U_(0x1) << PIO_LSR_P30_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5797 #define PIO_LSR_P30 PIO_LSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P30_Msk instead */ 5798 #define PIO_LSR_P31_Pos 31 /**< (PIO_LSR) Level Interrupt Selection Position */ 5799 #define PIO_LSR_P31_Msk (_U_(0x1) << PIO_LSR_P31_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ 5800 #define PIO_LSR_P31 PIO_LSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P31_Msk instead */ 5801 #define PIO_LSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_LSR) Register MASK (Use PIO_LSR_Msk instead) */ 5802 #define PIO_LSR_Msk _U_(0xFFFFFFFF) /**< (PIO_LSR) Register Mask */ 5803 5804 #define PIO_LSR_P_Pos 0 /**< (PIO_LSR Position) Level Interrupt Selection */ 5805 #define PIO_LSR_P_Msk (_U_(0xFFFFFFFF) << PIO_LSR_P_Pos) /**< (PIO_LSR Mask) P */ 5806 #define PIO_LSR_P(value) (PIO_LSR_P_Msk & ((value) << PIO_LSR_P_Pos)) 5807 5808 /* -------- PIO_ELSR : (PIO Offset: 0xc8) (R/ 32) Edge/Level Status Register -------- */ 5809 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 5810 #if COMPONENT_TYPEDEF_STYLE == 'N' 5811 typedef union { 5812 struct { 5813 uint32_t P0:1; /**< bit: 0 Edge/Level Interrupt Source Selection */ 5814 uint32_t P1:1; /**< bit: 1 Edge/Level Interrupt Source Selection */ 5815 uint32_t P2:1; /**< bit: 2 Edge/Level Interrupt Source Selection */ 5816 uint32_t P3:1; /**< bit: 3 Edge/Level Interrupt Source Selection */ 5817 uint32_t P4:1; /**< bit: 4 Edge/Level Interrupt Source Selection */ 5818 uint32_t P5:1; /**< bit: 5 Edge/Level Interrupt Source Selection */ 5819 uint32_t P6:1; /**< bit: 6 Edge/Level Interrupt Source Selection */ 5820 uint32_t P7:1; /**< bit: 7 Edge/Level Interrupt Source Selection */ 5821 uint32_t P8:1; /**< bit: 8 Edge/Level Interrupt Source Selection */ 5822 uint32_t P9:1; /**< bit: 9 Edge/Level Interrupt Source Selection */ 5823 uint32_t P10:1; /**< bit: 10 Edge/Level Interrupt Source Selection */ 5824 uint32_t P11:1; /**< bit: 11 Edge/Level Interrupt Source Selection */ 5825 uint32_t P12:1; /**< bit: 12 Edge/Level Interrupt Source Selection */ 5826 uint32_t P13:1; /**< bit: 13 Edge/Level Interrupt Source Selection */ 5827 uint32_t P14:1; /**< bit: 14 Edge/Level Interrupt Source Selection */ 5828 uint32_t P15:1; /**< bit: 15 Edge/Level Interrupt Source Selection */ 5829 uint32_t P16:1; /**< bit: 16 Edge/Level Interrupt Source Selection */ 5830 uint32_t P17:1; /**< bit: 17 Edge/Level Interrupt Source Selection */ 5831 uint32_t P18:1; /**< bit: 18 Edge/Level Interrupt Source Selection */ 5832 uint32_t P19:1; /**< bit: 19 Edge/Level Interrupt Source Selection */ 5833 uint32_t P20:1; /**< bit: 20 Edge/Level Interrupt Source Selection */ 5834 uint32_t P21:1; /**< bit: 21 Edge/Level Interrupt Source Selection */ 5835 uint32_t P22:1; /**< bit: 22 Edge/Level Interrupt Source Selection */ 5836 uint32_t P23:1; /**< bit: 23 Edge/Level Interrupt Source Selection */ 5837 uint32_t P24:1; /**< bit: 24 Edge/Level Interrupt Source Selection */ 5838 uint32_t P25:1; /**< bit: 25 Edge/Level Interrupt Source Selection */ 5839 uint32_t P26:1; /**< bit: 26 Edge/Level Interrupt Source Selection */ 5840 uint32_t P27:1; /**< bit: 27 Edge/Level Interrupt Source Selection */ 5841 uint32_t P28:1; /**< bit: 28 Edge/Level Interrupt Source Selection */ 5842 uint32_t P29:1; /**< bit: 29 Edge/Level Interrupt Source Selection */ 5843 uint32_t P30:1; /**< bit: 30 Edge/Level Interrupt Source Selection */ 5844 uint32_t P31:1; /**< bit: 31 Edge/Level Interrupt Source Selection */ 5845 } bit; /**< Structure used for bit access */ 5846 struct { 5847 uint32_t P:32; /**< bit: 0..31 Edge/Level Interrupt Source Selection */ 5848 } vec; /**< Structure used for vec access */ 5849 uint32_t reg; /**< Type used for register access */ 5850 } PIO_ELSR_Type; 5851 #endif 5852 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 5853 5854 #define PIO_ELSR_OFFSET (0xC8) /**< (PIO_ELSR) Edge/Level Status Register Offset */ 5855 5856 #define PIO_ELSR_P0_Pos 0 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5857 #define PIO_ELSR_P0_Msk (_U_(0x1) << PIO_ELSR_P0_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5858 #define PIO_ELSR_P0 PIO_ELSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P0_Msk instead */ 5859 #define PIO_ELSR_P1_Pos 1 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5860 #define PIO_ELSR_P1_Msk (_U_(0x1) << PIO_ELSR_P1_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5861 #define PIO_ELSR_P1 PIO_ELSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P1_Msk instead */ 5862 #define PIO_ELSR_P2_Pos 2 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5863 #define PIO_ELSR_P2_Msk (_U_(0x1) << PIO_ELSR_P2_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5864 #define PIO_ELSR_P2 PIO_ELSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P2_Msk instead */ 5865 #define PIO_ELSR_P3_Pos 3 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5866 #define PIO_ELSR_P3_Msk (_U_(0x1) << PIO_ELSR_P3_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5867 #define PIO_ELSR_P3 PIO_ELSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P3_Msk instead */ 5868 #define PIO_ELSR_P4_Pos 4 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5869 #define PIO_ELSR_P4_Msk (_U_(0x1) << PIO_ELSR_P4_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5870 #define PIO_ELSR_P4 PIO_ELSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P4_Msk instead */ 5871 #define PIO_ELSR_P5_Pos 5 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5872 #define PIO_ELSR_P5_Msk (_U_(0x1) << PIO_ELSR_P5_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5873 #define PIO_ELSR_P5 PIO_ELSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P5_Msk instead */ 5874 #define PIO_ELSR_P6_Pos 6 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5875 #define PIO_ELSR_P6_Msk (_U_(0x1) << PIO_ELSR_P6_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5876 #define PIO_ELSR_P6 PIO_ELSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P6_Msk instead */ 5877 #define PIO_ELSR_P7_Pos 7 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5878 #define PIO_ELSR_P7_Msk (_U_(0x1) << PIO_ELSR_P7_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5879 #define PIO_ELSR_P7 PIO_ELSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P7_Msk instead */ 5880 #define PIO_ELSR_P8_Pos 8 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5881 #define PIO_ELSR_P8_Msk (_U_(0x1) << PIO_ELSR_P8_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5882 #define PIO_ELSR_P8 PIO_ELSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P8_Msk instead */ 5883 #define PIO_ELSR_P9_Pos 9 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5884 #define PIO_ELSR_P9_Msk (_U_(0x1) << PIO_ELSR_P9_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5885 #define PIO_ELSR_P9 PIO_ELSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P9_Msk instead */ 5886 #define PIO_ELSR_P10_Pos 10 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5887 #define PIO_ELSR_P10_Msk (_U_(0x1) << PIO_ELSR_P10_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5888 #define PIO_ELSR_P10 PIO_ELSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P10_Msk instead */ 5889 #define PIO_ELSR_P11_Pos 11 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5890 #define PIO_ELSR_P11_Msk (_U_(0x1) << PIO_ELSR_P11_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5891 #define PIO_ELSR_P11 PIO_ELSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P11_Msk instead */ 5892 #define PIO_ELSR_P12_Pos 12 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5893 #define PIO_ELSR_P12_Msk (_U_(0x1) << PIO_ELSR_P12_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5894 #define PIO_ELSR_P12 PIO_ELSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P12_Msk instead */ 5895 #define PIO_ELSR_P13_Pos 13 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5896 #define PIO_ELSR_P13_Msk (_U_(0x1) << PIO_ELSR_P13_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5897 #define PIO_ELSR_P13 PIO_ELSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P13_Msk instead */ 5898 #define PIO_ELSR_P14_Pos 14 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5899 #define PIO_ELSR_P14_Msk (_U_(0x1) << PIO_ELSR_P14_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5900 #define PIO_ELSR_P14 PIO_ELSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P14_Msk instead */ 5901 #define PIO_ELSR_P15_Pos 15 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5902 #define PIO_ELSR_P15_Msk (_U_(0x1) << PIO_ELSR_P15_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5903 #define PIO_ELSR_P15 PIO_ELSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P15_Msk instead */ 5904 #define PIO_ELSR_P16_Pos 16 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5905 #define PIO_ELSR_P16_Msk (_U_(0x1) << PIO_ELSR_P16_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5906 #define PIO_ELSR_P16 PIO_ELSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P16_Msk instead */ 5907 #define PIO_ELSR_P17_Pos 17 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5908 #define PIO_ELSR_P17_Msk (_U_(0x1) << PIO_ELSR_P17_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5909 #define PIO_ELSR_P17 PIO_ELSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P17_Msk instead */ 5910 #define PIO_ELSR_P18_Pos 18 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5911 #define PIO_ELSR_P18_Msk (_U_(0x1) << PIO_ELSR_P18_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5912 #define PIO_ELSR_P18 PIO_ELSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P18_Msk instead */ 5913 #define PIO_ELSR_P19_Pos 19 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5914 #define PIO_ELSR_P19_Msk (_U_(0x1) << PIO_ELSR_P19_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5915 #define PIO_ELSR_P19 PIO_ELSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P19_Msk instead */ 5916 #define PIO_ELSR_P20_Pos 20 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5917 #define PIO_ELSR_P20_Msk (_U_(0x1) << PIO_ELSR_P20_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5918 #define PIO_ELSR_P20 PIO_ELSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P20_Msk instead */ 5919 #define PIO_ELSR_P21_Pos 21 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5920 #define PIO_ELSR_P21_Msk (_U_(0x1) << PIO_ELSR_P21_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5921 #define PIO_ELSR_P21 PIO_ELSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P21_Msk instead */ 5922 #define PIO_ELSR_P22_Pos 22 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5923 #define PIO_ELSR_P22_Msk (_U_(0x1) << PIO_ELSR_P22_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5924 #define PIO_ELSR_P22 PIO_ELSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P22_Msk instead */ 5925 #define PIO_ELSR_P23_Pos 23 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5926 #define PIO_ELSR_P23_Msk (_U_(0x1) << PIO_ELSR_P23_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5927 #define PIO_ELSR_P23 PIO_ELSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P23_Msk instead */ 5928 #define PIO_ELSR_P24_Pos 24 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5929 #define PIO_ELSR_P24_Msk (_U_(0x1) << PIO_ELSR_P24_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5930 #define PIO_ELSR_P24 PIO_ELSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P24_Msk instead */ 5931 #define PIO_ELSR_P25_Pos 25 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5932 #define PIO_ELSR_P25_Msk (_U_(0x1) << PIO_ELSR_P25_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5933 #define PIO_ELSR_P25 PIO_ELSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P25_Msk instead */ 5934 #define PIO_ELSR_P26_Pos 26 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5935 #define PIO_ELSR_P26_Msk (_U_(0x1) << PIO_ELSR_P26_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5936 #define PIO_ELSR_P26 PIO_ELSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P26_Msk instead */ 5937 #define PIO_ELSR_P27_Pos 27 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5938 #define PIO_ELSR_P27_Msk (_U_(0x1) << PIO_ELSR_P27_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5939 #define PIO_ELSR_P27 PIO_ELSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P27_Msk instead */ 5940 #define PIO_ELSR_P28_Pos 28 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5941 #define PIO_ELSR_P28_Msk (_U_(0x1) << PIO_ELSR_P28_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5942 #define PIO_ELSR_P28 PIO_ELSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P28_Msk instead */ 5943 #define PIO_ELSR_P29_Pos 29 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5944 #define PIO_ELSR_P29_Msk (_U_(0x1) << PIO_ELSR_P29_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5945 #define PIO_ELSR_P29 PIO_ELSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P29_Msk instead */ 5946 #define PIO_ELSR_P30_Pos 30 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5947 #define PIO_ELSR_P30_Msk (_U_(0x1) << PIO_ELSR_P30_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5948 #define PIO_ELSR_P30 PIO_ELSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P30_Msk instead */ 5949 #define PIO_ELSR_P31_Pos 31 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ 5950 #define PIO_ELSR_P31_Msk (_U_(0x1) << PIO_ELSR_P31_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ 5951 #define PIO_ELSR_P31 PIO_ELSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P31_Msk instead */ 5952 #define PIO_ELSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_ELSR) Register MASK (Use PIO_ELSR_Msk instead) */ 5953 #define PIO_ELSR_Msk _U_(0xFFFFFFFF) /**< (PIO_ELSR) Register Mask */ 5954 5955 #define PIO_ELSR_P_Pos 0 /**< (PIO_ELSR Position) Edge/Level Interrupt Source Selection */ 5956 #define PIO_ELSR_P_Msk (_U_(0xFFFFFFFF) << PIO_ELSR_P_Pos) /**< (PIO_ELSR Mask) P */ 5957 #define PIO_ELSR_P(value) (PIO_ELSR_P_Msk & ((value) << PIO_ELSR_P_Pos)) 5958 5959 /* -------- PIO_FELLSR : (PIO Offset: 0xd0) (/W 32) Falling Edge/Low-Level Select Register -------- */ 5960 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 5961 #if COMPONENT_TYPEDEF_STYLE == 'N' 5962 typedef union { 5963 struct { 5964 uint32_t P0:1; /**< bit: 0 Falling Edge/Low-Level Interrupt Selection */ 5965 uint32_t P1:1; /**< bit: 1 Falling Edge/Low-Level Interrupt Selection */ 5966 uint32_t P2:1; /**< bit: 2 Falling Edge/Low-Level Interrupt Selection */ 5967 uint32_t P3:1; /**< bit: 3 Falling Edge/Low-Level Interrupt Selection */ 5968 uint32_t P4:1; /**< bit: 4 Falling Edge/Low-Level Interrupt Selection */ 5969 uint32_t P5:1; /**< bit: 5 Falling Edge/Low-Level Interrupt Selection */ 5970 uint32_t P6:1; /**< bit: 6 Falling Edge/Low-Level Interrupt Selection */ 5971 uint32_t P7:1; /**< bit: 7 Falling Edge/Low-Level Interrupt Selection */ 5972 uint32_t P8:1; /**< bit: 8 Falling Edge/Low-Level Interrupt Selection */ 5973 uint32_t P9:1; /**< bit: 9 Falling Edge/Low-Level Interrupt Selection */ 5974 uint32_t P10:1; /**< bit: 10 Falling Edge/Low-Level Interrupt Selection */ 5975 uint32_t P11:1; /**< bit: 11 Falling Edge/Low-Level Interrupt Selection */ 5976 uint32_t P12:1; /**< bit: 12 Falling Edge/Low-Level Interrupt Selection */ 5977 uint32_t P13:1; /**< bit: 13 Falling Edge/Low-Level Interrupt Selection */ 5978 uint32_t P14:1; /**< bit: 14 Falling Edge/Low-Level Interrupt Selection */ 5979 uint32_t P15:1; /**< bit: 15 Falling Edge/Low-Level Interrupt Selection */ 5980 uint32_t P16:1; /**< bit: 16 Falling Edge/Low-Level Interrupt Selection */ 5981 uint32_t P17:1; /**< bit: 17 Falling Edge/Low-Level Interrupt Selection */ 5982 uint32_t P18:1; /**< bit: 18 Falling Edge/Low-Level Interrupt Selection */ 5983 uint32_t P19:1; /**< bit: 19 Falling Edge/Low-Level Interrupt Selection */ 5984 uint32_t P20:1; /**< bit: 20 Falling Edge/Low-Level Interrupt Selection */ 5985 uint32_t P21:1; /**< bit: 21 Falling Edge/Low-Level Interrupt Selection */ 5986 uint32_t P22:1; /**< bit: 22 Falling Edge/Low-Level Interrupt Selection */ 5987 uint32_t P23:1; /**< bit: 23 Falling Edge/Low-Level Interrupt Selection */ 5988 uint32_t P24:1; /**< bit: 24 Falling Edge/Low-Level Interrupt Selection */ 5989 uint32_t P25:1; /**< bit: 25 Falling Edge/Low-Level Interrupt Selection */ 5990 uint32_t P26:1; /**< bit: 26 Falling Edge/Low-Level Interrupt Selection */ 5991 uint32_t P27:1; /**< bit: 27 Falling Edge/Low-Level Interrupt Selection */ 5992 uint32_t P28:1; /**< bit: 28 Falling Edge/Low-Level Interrupt Selection */ 5993 uint32_t P29:1; /**< bit: 29 Falling Edge/Low-Level Interrupt Selection */ 5994 uint32_t P30:1; /**< bit: 30 Falling Edge/Low-Level Interrupt Selection */ 5995 uint32_t P31:1; /**< bit: 31 Falling Edge/Low-Level Interrupt Selection */ 5996 } bit; /**< Structure used for bit access */ 5997 struct { 5998 uint32_t P:32; /**< bit: 0..31 Falling Edge/Low-Level Interrupt Selection */ 5999 } vec; /**< Structure used for vec access */ 6000 uint32_t reg; /**< Type used for register access */ 6001 } PIO_FELLSR_Type; 6002 #endif 6003 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 6004 6005 #define PIO_FELLSR_OFFSET (0xD0) /**< (PIO_FELLSR) Falling Edge/Low-Level Select Register Offset */ 6006 6007 #define PIO_FELLSR_P0_Pos 0 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6008 #define PIO_FELLSR_P0_Msk (_U_(0x1) << PIO_FELLSR_P0_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6009 #define PIO_FELLSR_P0 PIO_FELLSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P0_Msk instead */ 6010 #define PIO_FELLSR_P1_Pos 1 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6011 #define PIO_FELLSR_P1_Msk (_U_(0x1) << PIO_FELLSR_P1_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6012 #define PIO_FELLSR_P1 PIO_FELLSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P1_Msk instead */ 6013 #define PIO_FELLSR_P2_Pos 2 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6014 #define PIO_FELLSR_P2_Msk (_U_(0x1) << PIO_FELLSR_P2_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6015 #define PIO_FELLSR_P2 PIO_FELLSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P2_Msk instead */ 6016 #define PIO_FELLSR_P3_Pos 3 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6017 #define PIO_FELLSR_P3_Msk (_U_(0x1) << PIO_FELLSR_P3_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6018 #define PIO_FELLSR_P3 PIO_FELLSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P3_Msk instead */ 6019 #define PIO_FELLSR_P4_Pos 4 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6020 #define PIO_FELLSR_P4_Msk (_U_(0x1) << PIO_FELLSR_P4_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6021 #define PIO_FELLSR_P4 PIO_FELLSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P4_Msk instead */ 6022 #define PIO_FELLSR_P5_Pos 5 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6023 #define PIO_FELLSR_P5_Msk (_U_(0x1) << PIO_FELLSR_P5_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6024 #define PIO_FELLSR_P5 PIO_FELLSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P5_Msk instead */ 6025 #define PIO_FELLSR_P6_Pos 6 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6026 #define PIO_FELLSR_P6_Msk (_U_(0x1) << PIO_FELLSR_P6_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6027 #define PIO_FELLSR_P6 PIO_FELLSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P6_Msk instead */ 6028 #define PIO_FELLSR_P7_Pos 7 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6029 #define PIO_FELLSR_P7_Msk (_U_(0x1) << PIO_FELLSR_P7_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6030 #define PIO_FELLSR_P7 PIO_FELLSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P7_Msk instead */ 6031 #define PIO_FELLSR_P8_Pos 8 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6032 #define PIO_FELLSR_P8_Msk (_U_(0x1) << PIO_FELLSR_P8_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6033 #define PIO_FELLSR_P8 PIO_FELLSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P8_Msk instead */ 6034 #define PIO_FELLSR_P9_Pos 9 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6035 #define PIO_FELLSR_P9_Msk (_U_(0x1) << PIO_FELLSR_P9_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6036 #define PIO_FELLSR_P9 PIO_FELLSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P9_Msk instead */ 6037 #define PIO_FELLSR_P10_Pos 10 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6038 #define PIO_FELLSR_P10_Msk (_U_(0x1) << PIO_FELLSR_P10_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6039 #define PIO_FELLSR_P10 PIO_FELLSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P10_Msk instead */ 6040 #define PIO_FELLSR_P11_Pos 11 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6041 #define PIO_FELLSR_P11_Msk (_U_(0x1) << PIO_FELLSR_P11_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6042 #define PIO_FELLSR_P11 PIO_FELLSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P11_Msk instead */ 6043 #define PIO_FELLSR_P12_Pos 12 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6044 #define PIO_FELLSR_P12_Msk (_U_(0x1) << PIO_FELLSR_P12_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6045 #define PIO_FELLSR_P12 PIO_FELLSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P12_Msk instead */ 6046 #define PIO_FELLSR_P13_Pos 13 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6047 #define PIO_FELLSR_P13_Msk (_U_(0x1) << PIO_FELLSR_P13_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6048 #define PIO_FELLSR_P13 PIO_FELLSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P13_Msk instead */ 6049 #define PIO_FELLSR_P14_Pos 14 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6050 #define PIO_FELLSR_P14_Msk (_U_(0x1) << PIO_FELLSR_P14_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6051 #define PIO_FELLSR_P14 PIO_FELLSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P14_Msk instead */ 6052 #define PIO_FELLSR_P15_Pos 15 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6053 #define PIO_FELLSR_P15_Msk (_U_(0x1) << PIO_FELLSR_P15_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6054 #define PIO_FELLSR_P15 PIO_FELLSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P15_Msk instead */ 6055 #define PIO_FELLSR_P16_Pos 16 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6056 #define PIO_FELLSR_P16_Msk (_U_(0x1) << PIO_FELLSR_P16_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6057 #define PIO_FELLSR_P16 PIO_FELLSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P16_Msk instead */ 6058 #define PIO_FELLSR_P17_Pos 17 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6059 #define PIO_FELLSR_P17_Msk (_U_(0x1) << PIO_FELLSR_P17_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6060 #define PIO_FELLSR_P17 PIO_FELLSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P17_Msk instead */ 6061 #define PIO_FELLSR_P18_Pos 18 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6062 #define PIO_FELLSR_P18_Msk (_U_(0x1) << PIO_FELLSR_P18_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6063 #define PIO_FELLSR_P18 PIO_FELLSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P18_Msk instead */ 6064 #define PIO_FELLSR_P19_Pos 19 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6065 #define PIO_FELLSR_P19_Msk (_U_(0x1) << PIO_FELLSR_P19_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6066 #define PIO_FELLSR_P19 PIO_FELLSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P19_Msk instead */ 6067 #define PIO_FELLSR_P20_Pos 20 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6068 #define PIO_FELLSR_P20_Msk (_U_(0x1) << PIO_FELLSR_P20_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6069 #define PIO_FELLSR_P20 PIO_FELLSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P20_Msk instead */ 6070 #define PIO_FELLSR_P21_Pos 21 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6071 #define PIO_FELLSR_P21_Msk (_U_(0x1) << PIO_FELLSR_P21_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6072 #define PIO_FELLSR_P21 PIO_FELLSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P21_Msk instead */ 6073 #define PIO_FELLSR_P22_Pos 22 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6074 #define PIO_FELLSR_P22_Msk (_U_(0x1) << PIO_FELLSR_P22_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6075 #define PIO_FELLSR_P22 PIO_FELLSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P22_Msk instead */ 6076 #define PIO_FELLSR_P23_Pos 23 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6077 #define PIO_FELLSR_P23_Msk (_U_(0x1) << PIO_FELLSR_P23_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6078 #define PIO_FELLSR_P23 PIO_FELLSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P23_Msk instead */ 6079 #define PIO_FELLSR_P24_Pos 24 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6080 #define PIO_FELLSR_P24_Msk (_U_(0x1) << PIO_FELLSR_P24_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6081 #define PIO_FELLSR_P24 PIO_FELLSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P24_Msk instead */ 6082 #define PIO_FELLSR_P25_Pos 25 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6083 #define PIO_FELLSR_P25_Msk (_U_(0x1) << PIO_FELLSR_P25_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6084 #define PIO_FELLSR_P25 PIO_FELLSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P25_Msk instead */ 6085 #define PIO_FELLSR_P26_Pos 26 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6086 #define PIO_FELLSR_P26_Msk (_U_(0x1) << PIO_FELLSR_P26_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6087 #define PIO_FELLSR_P26 PIO_FELLSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P26_Msk instead */ 6088 #define PIO_FELLSR_P27_Pos 27 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6089 #define PIO_FELLSR_P27_Msk (_U_(0x1) << PIO_FELLSR_P27_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6090 #define PIO_FELLSR_P27 PIO_FELLSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P27_Msk instead */ 6091 #define PIO_FELLSR_P28_Pos 28 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6092 #define PIO_FELLSR_P28_Msk (_U_(0x1) << PIO_FELLSR_P28_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6093 #define PIO_FELLSR_P28 PIO_FELLSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P28_Msk instead */ 6094 #define PIO_FELLSR_P29_Pos 29 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6095 #define PIO_FELLSR_P29_Msk (_U_(0x1) << PIO_FELLSR_P29_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6096 #define PIO_FELLSR_P29 PIO_FELLSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P29_Msk instead */ 6097 #define PIO_FELLSR_P30_Pos 30 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6098 #define PIO_FELLSR_P30_Msk (_U_(0x1) << PIO_FELLSR_P30_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6099 #define PIO_FELLSR_P30 PIO_FELLSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P30_Msk instead */ 6100 #define PIO_FELLSR_P31_Pos 31 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ 6101 #define PIO_FELLSR_P31_Msk (_U_(0x1) << PIO_FELLSR_P31_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ 6102 #define PIO_FELLSR_P31 PIO_FELLSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P31_Msk instead */ 6103 #define PIO_FELLSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_FELLSR) Register MASK (Use PIO_FELLSR_Msk instead) */ 6104 #define PIO_FELLSR_Msk _U_(0xFFFFFFFF) /**< (PIO_FELLSR) Register Mask */ 6105 6106 #define PIO_FELLSR_P_Pos 0 /**< (PIO_FELLSR Position) Falling Edge/Low-Level Interrupt Selection */ 6107 #define PIO_FELLSR_P_Msk (_U_(0xFFFFFFFF) << PIO_FELLSR_P_Pos) /**< (PIO_FELLSR Mask) P */ 6108 #define PIO_FELLSR_P(value) (PIO_FELLSR_P_Msk & ((value) << PIO_FELLSR_P_Pos)) 6109 6110 /* -------- PIO_REHLSR : (PIO Offset: 0xd4) (/W 32) Rising Edge/High-Level Select Register -------- */ 6111 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 6112 #if COMPONENT_TYPEDEF_STYLE == 'N' 6113 typedef union { 6114 struct { 6115 uint32_t P0:1; /**< bit: 0 Rising Edge/High-Level Interrupt Selection */ 6116 uint32_t P1:1; /**< bit: 1 Rising Edge/High-Level Interrupt Selection */ 6117 uint32_t P2:1; /**< bit: 2 Rising Edge/High-Level Interrupt Selection */ 6118 uint32_t P3:1; /**< bit: 3 Rising Edge/High-Level Interrupt Selection */ 6119 uint32_t P4:1; /**< bit: 4 Rising Edge/High-Level Interrupt Selection */ 6120 uint32_t P5:1; /**< bit: 5 Rising Edge/High-Level Interrupt Selection */ 6121 uint32_t P6:1; /**< bit: 6 Rising Edge/High-Level Interrupt Selection */ 6122 uint32_t P7:1; /**< bit: 7 Rising Edge/High-Level Interrupt Selection */ 6123 uint32_t P8:1; /**< bit: 8 Rising Edge/High-Level Interrupt Selection */ 6124 uint32_t P9:1; /**< bit: 9 Rising Edge/High-Level Interrupt Selection */ 6125 uint32_t P10:1; /**< bit: 10 Rising Edge/High-Level Interrupt Selection */ 6126 uint32_t P11:1; /**< bit: 11 Rising Edge/High-Level Interrupt Selection */ 6127 uint32_t P12:1; /**< bit: 12 Rising Edge/High-Level Interrupt Selection */ 6128 uint32_t P13:1; /**< bit: 13 Rising Edge/High-Level Interrupt Selection */ 6129 uint32_t P14:1; /**< bit: 14 Rising Edge/High-Level Interrupt Selection */ 6130 uint32_t P15:1; /**< bit: 15 Rising Edge/High-Level Interrupt Selection */ 6131 uint32_t P16:1; /**< bit: 16 Rising Edge/High-Level Interrupt Selection */ 6132 uint32_t P17:1; /**< bit: 17 Rising Edge/High-Level Interrupt Selection */ 6133 uint32_t P18:1; /**< bit: 18 Rising Edge/High-Level Interrupt Selection */ 6134 uint32_t P19:1; /**< bit: 19 Rising Edge/High-Level Interrupt Selection */ 6135 uint32_t P20:1; /**< bit: 20 Rising Edge/High-Level Interrupt Selection */ 6136 uint32_t P21:1; /**< bit: 21 Rising Edge/High-Level Interrupt Selection */ 6137 uint32_t P22:1; /**< bit: 22 Rising Edge/High-Level Interrupt Selection */ 6138 uint32_t P23:1; /**< bit: 23 Rising Edge/High-Level Interrupt Selection */ 6139 uint32_t P24:1; /**< bit: 24 Rising Edge/High-Level Interrupt Selection */ 6140 uint32_t P25:1; /**< bit: 25 Rising Edge/High-Level Interrupt Selection */ 6141 uint32_t P26:1; /**< bit: 26 Rising Edge/High-Level Interrupt Selection */ 6142 uint32_t P27:1; /**< bit: 27 Rising Edge/High-Level Interrupt Selection */ 6143 uint32_t P28:1; /**< bit: 28 Rising Edge/High-Level Interrupt Selection */ 6144 uint32_t P29:1; /**< bit: 29 Rising Edge/High-Level Interrupt Selection */ 6145 uint32_t P30:1; /**< bit: 30 Rising Edge/High-Level Interrupt Selection */ 6146 uint32_t P31:1; /**< bit: 31 Rising Edge/High-Level Interrupt Selection */ 6147 } bit; /**< Structure used for bit access */ 6148 struct { 6149 uint32_t P:32; /**< bit: 0..31 Rising Edge/High-Level Interrupt Selection */ 6150 } vec; /**< Structure used for vec access */ 6151 uint32_t reg; /**< Type used for register access */ 6152 } PIO_REHLSR_Type; 6153 #endif 6154 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 6155 6156 #define PIO_REHLSR_OFFSET (0xD4) /**< (PIO_REHLSR) Rising Edge/High-Level Select Register Offset */ 6157 6158 #define PIO_REHLSR_P0_Pos 0 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6159 #define PIO_REHLSR_P0_Msk (_U_(0x1) << PIO_REHLSR_P0_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6160 #define PIO_REHLSR_P0 PIO_REHLSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P0_Msk instead */ 6161 #define PIO_REHLSR_P1_Pos 1 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6162 #define PIO_REHLSR_P1_Msk (_U_(0x1) << PIO_REHLSR_P1_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6163 #define PIO_REHLSR_P1 PIO_REHLSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P1_Msk instead */ 6164 #define PIO_REHLSR_P2_Pos 2 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6165 #define PIO_REHLSR_P2_Msk (_U_(0x1) << PIO_REHLSR_P2_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6166 #define PIO_REHLSR_P2 PIO_REHLSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P2_Msk instead */ 6167 #define PIO_REHLSR_P3_Pos 3 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6168 #define PIO_REHLSR_P3_Msk (_U_(0x1) << PIO_REHLSR_P3_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6169 #define PIO_REHLSR_P3 PIO_REHLSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P3_Msk instead */ 6170 #define PIO_REHLSR_P4_Pos 4 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6171 #define PIO_REHLSR_P4_Msk (_U_(0x1) << PIO_REHLSR_P4_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6172 #define PIO_REHLSR_P4 PIO_REHLSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P4_Msk instead */ 6173 #define PIO_REHLSR_P5_Pos 5 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6174 #define PIO_REHLSR_P5_Msk (_U_(0x1) << PIO_REHLSR_P5_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6175 #define PIO_REHLSR_P5 PIO_REHLSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P5_Msk instead */ 6176 #define PIO_REHLSR_P6_Pos 6 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6177 #define PIO_REHLSR_P6_Msk (_U_(0x1) << PIO_REHLSR_P6_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6178 #define PIO_REHLSR_P6 PIO_REHLSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P6_Msk instead */ 6179 #define PIO_REHLSR_P7_Pos 7 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6180 #define PIO_REHLSR_P7_Msk (_U_(0x1) << PIO_REHLSR_P7_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6181 #define PIO_REHLSR_P7 PIO_REHLSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P7_Msk instead */ 6182 #define PIO_REHLSR_P8_Pos 8 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6183 #define PIO_REHLSR_P8_Msk (_U_(0x1) << PIO_REHLSR_P8_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6184 #define PIO_REHLSR_P8 PIO_REHLSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P8_Msk instead */ 6185 #define PIO_REHLSR_P9_Pos 9 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6186 #define PIO_REHLSR_P9_Msk (_U_(0x1) << PIO_REHLSR_P9_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6187 #define PIO_REHLSR_P9 PIO_REHLSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P9_Msk instead */ 6188 #define PIO_REHLSR_P10_Pos 10 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6189 #define PIO_REHLSR_P10_Msk (_U_(0x1) << PIO_REHLSR_P10_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6190 #define PIO_REHLSR_P10 PIO_REHLSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P10_Msk instead */ 6191 #define PIO_REHLSR_P11_Pos 11 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6192 #define PIO_REHLSR_P11_Msk (_U_(0x1) << PIO_REHLSR_P11_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6193 #define PIO_REHLSR_P11 PIO_REHLSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P11_Msk instead */ 6194 #define PIO_REHLSR_P12_Pos 12 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6195 #define PIO_REHLSR_P12_Msk (_U_(0x1) << PIO_REHLSR_P12_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6196 #define PIO_REHLSR_P12 PIO_REHLSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P12_Msk instead */ 6197 #define PIO_REHLSR_P13_Pos 13 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6198 #define PIO_REHLSR_P13_Msk (_U_(0x1) << PIO_REHLSR_P13_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6199 #define PIO_REHLSR_P13 PIO_REHLSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P13_Msk instead */ 6200 #define PIO_REHLSR_P14_Pos 14 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6201 #define PIO_REHLSR_P14_Msk (_U_(0x1) << PIO_REHLSR_P14_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6202 #define PIO_REHLSR_P14 PIO_REHLSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P14_Msk instead */ 6203 #define PIO_REHLSR_P15_Pos 15 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6204 #define PIO_REHLSR_P15_Msk (_U_(0x1) << PIO_REHLSR_P15_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6205 #define PIO_REHLSR_P15 PIO_REHLSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P15_Msk instead */ 6206 #define PIO_REHLSR_P16_Pos 16 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6207 #define PIO_REHLSR_P16_Msk (_U_(0x1) << PIO_REHLSR_P16_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6208 #define PIO_REHLSR_P16 PIO_REHLSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P16_Msk instead */ 6209 #define PIO_REHLSR_P17_Pos 17 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6210 #define PIO_REHLSR_P17_Msk (_U_(0x1) << PIO_REHLSR_P17_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6211 #define PIO_REHLSR_P17 PIO_REHLSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P17_Msk instead */ 6212 #define PIO_REHLSR_P18_Pos 18 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6213 #define PIO_REHLSR_P18_Msk (_U_(0x1) << PIO_REHLSR_P18_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6214 #define PIO_REHLSR_P18 PIO_REHLSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P18_Msk instead */ 6215 #define PIO_REHLSR_P19_Pos 19 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6216 #define PIO_REHLSR_P19_Msk (_U_(0x1) << PIO_REHLSR_P19_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6217 #define PIO_REHLSR_P19 PIO_REHLSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P19_Msk instead */ 6218 #define PIO_REHLSR_P20_Pos 20 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6219 #define PIO_REHLSR_P20_Msk (_U_(0x1) << PIO_REHLSR_P20_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6220 #define PIO_REHLSR_P20 PIO_REHLSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P20_Msk instead */ 6221 #define PIO_REHLSR_P21_Pos 21 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6222 #define PIO_REHLSR_P21_Msk (_U_(0x1) << PIO_REHLSR_P21_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6223 #define PIO_REHLSR_P21 PIO_REHLSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P21_Msk instead */ 6224 #define PIO_REHLSR_P22_Pos 22 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6225 #define PIO_REHLSR_P22_Msk (_U_(0x1) << PIO_REHLSR_P22_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6226 #define PIO_REHLSR_P22 PIO_REHLSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P22_Msk instead */ 6227 #define PIO_REHLSR_P23_Pos 23 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6228 #define PIO_REHLSR_P23_Msk (_U_(0x1) << PIO_REHLSR_P23_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6229 #define PIO_REHLSR_P23 PIO_REHLSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P23_Msk instead */ 6230 #define PIO_REHLSR_P24_Pos 24 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6231 #define PIO_REHLSR_P24_Msk (_U_(0x1) << PIO_REHLSR_P24_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6232 #define PIO_REHLSR_P24 PIO_REHLSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P24_Msk instead */ 6233 #define PIO_REHLSR_P25_Pos 25 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6234 #define PIO_REHLSR_P25_Msk (_U_(0x1) << PIO_REHLSR_P25_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6235 #define PIO_REHLSR_P25 PIO_REHLSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P25_Msk instead */ 6236 #define PIO_REHLSR_P26_Pos 26 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6237 #define PIO_REHLSR_P26_Msk (_U_(0x1) << PIO_REHLSR_P26_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6238 #define PIO_REHLSR_P26 PIO_REHLSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P26_Msk instead */ 6239 #define PIO_REHLSR_P27_Pos 27 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6240 #define PIO_REHLSR_P27_Msk (_U_(0x1) << PIO_REHLSR_P27_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6241 #define PIO_REHLSR_P27 PIO_REHLSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P27_Msk instead */ 6242 #define PIO_REHLSR_P28_Pos 28 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6243 #define PIO_REHLSR_P28_Msk (_U_(0x1) << PIO_REHLSR_P28_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6244 #define PIO_REHLSR_P28 PIO_REHLSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P28_Msk instead */ 6245 #define PIO_REHLSR_P29_Pos 29 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6246 #define PIO_REHLSR_P29_Msk (_U_(0x1) << PIO_REHLSR_P29_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6247 #define PIO_REHLSR_P29 PIO_REHLSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P29_Msk instead */ 6248 #define PIO_REHLSR_P30_Pos 30 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6249 #define PIO_REHLSR_P30_Msk (_U_(0x1) << PIO_REHLSR_P30_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6250 #define PIO_REHLSR_P30 PIO_REHLSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P30_Msk instead */ 6251 #define PIO_REHLSR_P31_Pos 31 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ 6252 #define PIO_REHLSR_P31_Msk (_U_(0x1) << PIO_REHLSR_P31_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ 6253 #define PIO_REHLSR_P31 PIO_REHLSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P31_Msk instead */ 6254 #define PIO_REHLSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_REHLSR) Register MASK (Use PIO_REHLSR_Msk instead) */ 6255 #define PIO_REHLSR_Msk _U_(0xFFFFFFFF) /**< (PIO_REHLSR) Register Mask */ 6256 6257 #define PIO_REHLSR_P_Pos 0 /**< (PIO_REHLSR Position) Rising Edge/High-Level Interrupt Selection */ 6258 #define PIO_REHLSR_P_Msk (_U_(0xFFFFFFFF) << PIO_REHLSR_P_Pos) /**< (PIO_REHLSR Mask) P */ 6259 #define PIO_REHLSR_P(value) (PIO_REHLSR_P_Msk & ((value) << PIO_REHLSR_P_Pos)) 6260 6261 /* -------- PIO_FRLHSR : (PIO Offset: 0xd8) (R/ 32) Fall/Rise - Low/High Status Register -------- */ 6262 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 6263 #if COMPONENT_TYPEDEF_STYLE == 'N' 6264 typedef union { 6265 struct { 6266 uint32_t P0:1; /**< bit: 0 Edge/Level Interrupt Source Selection */ 6267 uint32_t P1:1; /**< bit: 1 Edge/Level Interrupt Source Selection */ 6268 uint32_t P2:1; /**< bit: 2 Edge/Level Interrupt Source Selection */ 6269 uint32_t P3:1; /**< bit: 3 Edge/Level Interrupt Source Selection */ 6270 uint32_t P4:1; /**< bit: 4 Edge/Level Interrupt Source Selection */ 6271 uint32_t P5:1; /**< bit: 5 Edge/Level Interrupt Source Selection */ 6272 uint32_t P6:1; /**< bit: 6 Edge/Level Interrupt Source Selection */ 6273 uint32_t P7:1; /**< bit: 7 Edge/Level Interrupt Source Selection */ 6274 uint32_t P8:1; /**< bit: 8 Edge/Level Interrupt Source Selection */ 6275 uint32_t P9:1; /**< bit: 9 Edge/Level Interrupt Source Selection */ 6276 uint32_t P10:1; /**< bit: 10 Edge/Level Interrupt Source Selection */ 6277 uint32_t P11:1; /**< bit: 11 Edge/Level Interrupt Source Selection */ 6278 uint32_t P12:1; /**< bit: 12 Edge/Level Interrupt Source Selection */ 6279 uint32_t P13:1; /**< bit: 13 Edge/Level Interrupt Source Selection */ 6280 uint32_t P14:1; /**< bit: 14 Edge/Level Interrupt Source Selection */ 6281 uint32_t P15:1; /**< bit: 15 Edge/Level Interrupt Source Selection */ 6282 uint32_t P16:1; /**< bit: 16 Edge/Level Interrupt Source Selection */ 6283 uint32_t P17:1; /**< bit: 17 Edge/Level Interrupt Source Selection */ 6284 uint32_t P18:1; /**< bit: 18 Edge/Level Interrupt Source Selection */ 6285 uint32_t P19:1; /**< bit: 19 Edge/Level Interrupt Source Selection */ 6286 uint32_t P20:1; /**< bit: 20 Edge/Level Interrupt Source Selection */ 6287 uint32_t P21:1; /**< bit: 21 Edge/Level Interrupt Source Selection */ 6288 uint32_t P22:1; /**< bit: 22 Edge/Level Interrupt Source Selection */ 6289 uint32_t P23:1; /**< bit: 23 Edge/Level Interrupt Source Selection */ 6290 uint32_t P24:1; /**< bit: 24 Edge/Level Interrupt Source Selection */ 6291 uint32_t P25:1; /**< bit: 25 Edge/Level Interrupt Source Selection */ 6292 uint32_t P26:1; /**< bit: 26 Edge/Level Interrupt Source Selection */ 6293 uint32_t P27:1; /**< bit: 27 Edge/Level Interrupt Source Selection */ 6294 uint32_t P28:1; /**< bit: 28 Edge/Level Interrupt Source Selection */ 6295 uint32_t P29:1; /**< bit: 29 Edge/Level Interrupt Source Selection */ 6296 uint32_t P30:1; /**< bit: 30 Edge/Level Interrupt Source Selection */ 6297 uint32_t P31:1; /**< bit: 31 Edge/Level Interrupt Source Selection */ 6298 } bit; /**< Structure used for bit access */ 6299 struct { 6300 uint32_t P:32; /**< bit: 0..31 Edge/Level Interrupt Source Selection */ 6301 } vec; /**< Structure used for vec access */ 6302 uint32_t reg; /**< Type used for register access */ 6303 } PIO_FRLHSR_Type; 6304 #endif 6305 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 6306 6307 #define PIO_FRLHSR_OFFSET (0xD8) /**< (PIO_FRLHSR) Fall/Rise - Low/High Status Register Offset */ 6308 6309 #define PIO_FRLHSR_P0_Pos 0 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6310 #define PIO_FRLHSR_P0_Msk (_U_(0x1) << PIO_FRLHSR_P0_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6311 #define PIO_FRLHSR_P0 PIO_FRLHSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P0_Msk instead */ 6312 #define PIO_FRLHSR_P1_Pos 1 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6313 #define PIO_FRLHSR_P1_Msk (_U_(0x1) << PIO_FRLHSR_P1_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6314 #define PIO_FRLHSR_P1 PIO_FRLHSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P1_Msk instead */ 6315 #define PIO_FRLHSR_P2_Pos 2 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6316 #define PIO_FRLHSR_P2_Msk (_U_(0x1) << PIO_FRLHSR_P2_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6317 #define PIO_FRLHSR_P2 PIO_FRLHSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P2_Msk instead */ 6318 #define PIO_FRLHSR_P3_Pos 3 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6319 #define PIO_FRLHSR_P3_Msk (_U_(0x1) << PIO_FRLHSR_P3_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6320 #define PIO_FRLHSR_P3 PIO_FRLHSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P3_Msk instead */ 6321 #define PIO_FRLHSR_P4_Pos 4 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6322 #define PIO_FRLHSR_P4_Msk (_U_(0x1) << PIO_FRLHSR_P4_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6323 #define PIO_FRLHSR_P4 PIO_FRLHSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P4_Msk instead */ 6324 #define PIO_FRLHSR_P5_Pos 5 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6325 #define PIO_FRLHSR_P5_Msk (_U_(0x1) << PIO_FRLHSR_P5_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6326 #define PIO_FRLHSR_P5 PIO_FRLHSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P5_Msk instead */ 6327 #define PIO_FRLHSR_P6_Pos 6 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6328 #define PIO_FRLHSR_P6_Msk (_U_(0x1) << PIO_FRLHSR_P6_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6329 #define PIO_FRLHSR_P6 PIO_FRLHSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P6_Msk instead */ 6330 #define PIO_FRLHSR_P7_Pos 7 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6331 #define PIO_FRLHSR_P7_Msk (_U_(0x1) << PIO_FRLHSR_P7_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6332 #define PIO_FRLHSR_P7 PIO_FRLHSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P7_Msk instead */ 6333 #define PIO_FRLHSR_P8_Pos 8 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6334 #define PIO_FRLHSR_P8_Msk (_U_(0x1) << PIO_FRLHSR_P8_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6335 #define PIO_FRLHSR_P8 PIO_FRLHSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P8_Msk instead */ 6336 #define PIO_FRLHSR_P9_Pos 9 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6337 #define PIO_FRLHSR_P9_Msk (_U_(0x1) << PIO_FRLHSR_P9_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6338 #define PIO_FRLHSR_P9 PIO_FRLHSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P9_Msk instead */ 6339 #define PIO_FRLHSR_P10_Pos 10 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6340 #define PIO_FRLHSR_P10_Msk (_U_(0x1) << PIO_FRLHSR_P10_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6341 #define PIO_FRLHSR_P10 PIO_FRLHSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P10_Msk instead */ 6342 #define PIO_FRLHSR_P11_Pos 11 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6343 #define PIO_FRLHSR_P11_Msk (_U_(0x1) << PIO_FRLHSR_P11_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6344 #define PIO_FRLHSR_P11 PIO_FRLHSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P11_Msk instead */ 6345 #define PIO_FRLHSR_P12_Pos 12 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6346 #define PIO_FRLHSR_P12_Msk (_U_(0x1) << PIO_FRLHSR_P12_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6347 #define PIO_FRLHSR_P12 PIO_FRLHSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P12_Msk instead */ 6348 #define PIO_FRLHSR_P13_Pos 13 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6349 #define PIO_FRLHSR_P13_Msk (_U_(0x1) << PIO_FRLHSR_P13_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6350 #define PIO_FRLHSR_P13 PIO_FRLHSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P13_Msk instead */ 6351 #define PIO_FRLHSR_P14_Pos 14 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6352 #define PIO_FRLHSR_P14_Msk (_U_(0x1) << PIO_FRLHSR_P14_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6353 #define PIO_FRLHSR_P14 PIO_FRLHSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P14_Msk instead */ 6354 #define PIO_FRLHSR_P15_Pos 15 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6355 #define PIO_FRLHSR_P15_Msk (_U_(0x1) << PIO_FRLHSR_P15_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6356 #define PIO_FRLHSR_P15 PIO_FRLHSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P15_Msk instead */ 6357 #define PIO_FRLHSR_P16_Pos 16 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6358 #define PIO_FRLHSR_P16_Msk (_U_(0x1) << PIO_FRLHSR_P16_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6359 #define PIO_FRLHSR_P16 PIO_FRLHSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P16_Msk instead */ 6360 #define PIO_FRLHSR_P17_Pos 17 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6361 #define PIO_FRLHSR_P17_Msk (_U_(0x1) << PIO_FRLHSR_P17_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6362 #define PIO_FRLHSR_P17 PIO_FRLHSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P17_Msk instead */ 6363 #define PIO_FRLHSR_P18_Pos 18 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6364 #define PIO_FRLHSR_P18_Msk (_U_(0x1) << PIO_FRLHSR_P18_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6365 #define PIO_FRLHSR_P18 PIO_FRLHSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P18_Msk instead */ 6366 #define PIO_FRLHSR_P19_Pos 19 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6367 #define PIO_FRLHSR_P19_Msk (_U_(0x1) << PIO_FRLHSR_P19_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6368 #define PIO_FRLHSR_P19 PIO_FRLHSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P19_Msk instead */ 6369 #define PIO_FRLHSR_P20_Pos 20 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6370 #define PIO_FRLHSR_P20_Msk (_U_(0x1) << PIO_FRLHSR_P20_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6371 #define PIO_FRLHSR_P20 PIO_FRLHSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P20_Msk instead */ 6372 #define PIO_FRLHSR_P21_Pos 21 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6373 #define PIO_FRLHSR_P21_Msk (_U_(0x1) << PIO_FRLHSR_P21_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6374 #define PIO_FRLHSR_P21 PIO_FRLHSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P21_Msk instead */ 6375 #define PIO_FRLHSR_P22_Pos 22 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6376 #define PIO_FRLHSR_P22_Msk (_U_(0x1) << PIO_FRLHSR_P22_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6377 #define PIO_FRLHSR_P22 PIO_FRLHSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P22_Msk instead */ 6378 #define PIO_FRLHSR_P23_Pos 23 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6379 #define PIO_FRLHSR_P23_Msk (_U_(0x1) << PIO_FRLHSR_P23_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6380 #define PIO_FRLHSR_P23 PIO_FRLHSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P23_Msk instead */ 6381 #define PIO_FRLHSR_P24_Pos 24 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6382 #define PIO_FRLHSR_P24_Msk (_U_(0x1) << PIO_FRLHSR_P24_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6383 #define PIO_FRLHSR_P24 PIO_FRLHSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P24_Msk instead */ 6384 #define PIO_FRLHSR_P25_Pos 25 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6385 #define PIO_FRLHSR_P25_Msk (_U_(0x1) << PIO_FRLHSR_P25_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6386 #define PIO_FRLHSR_P25 PIO_FRLHSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P25_Msk instead */ 6387 #define PIO_FRLHSR_P26_Pos 26 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6388 #define PIO_FRLHSR_P26_Msk (_U_(0x1) << PIO_FRLHSR_P26_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6389 #define PIO_FRLHSR_P26 PIO_FRLHSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P26_Msk instead */ 6390 #define PIO_FRLHSR_P27_Pos 27 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6391 #define PIO_FRLHSR_P27_Msk (_U_(0x1) << PIO_FRLHSR_P27_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6392 #define PIO_FRLHSR_P27 PIO_FRLHSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P27_Msk instead */ 6393 #define PIO_FRLHSR_P28_Pos 28 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6394 #define PIO_FRLHSR_P28_Msk (_U_(0x1) << PIO_FRLHSR_P28_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6395 #define PIO_FRLHSR_P28 PIO_FRLHSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P28_Msk instead */ 6396 #define PIO_FRLHSR_P29_Pos 29 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6397 #define PIO_FRLHSR_P29_Msk (_U_(0x1) << PIO_FRLHSR_P29_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6398 #define PIO_FRLHSR_P29 PIO_FRLHSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P29_Msk instead */ 6399 #define PIO_FRLHSR_P30_Pos 30 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6400 #define PIO_FRLHSR_P30_Msk (_U_(0x1) << PIO_FRLHSR_P30_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6401 #define PIO_FRLHSR_P30 PIO_FRLHSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P30_Msk instead */ 6402 #define PIO_FRLHSR_P31_Pos 31 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ 6403 #define PIO_FRLHSR_P31_Msk (_U_(0x1) << PIO_FRLHSR_P31_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ 6404 #define PIO_FRLHSR_P31 PIO_FRLHSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P31_Msk instead */ 6405 #define PIO_FRLHSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_FRLHSR) Register MASK (Use PIO_FRLHSR_Msk instead) */ 6406 #define PIO_FRLHSR_Msk _U_(0xFFFFFFFF) /**< (PIO_FRLHSR) Register Mask */ 6407 6408 #define PIO_FRLHSR_P_Pos 0 /**< (PIO_FRLHSR Position) Edge/Level Interrupt Source Selection */ 6409 #define PIO_FRLHSR_P_Msk (_U_(0xFFFFFFFF) << PIO_FRLHSR_P_Pos) /**< (PIO_FRLHSR Mask) P */ 6410 #define PIO_FRLHSR_P(value) (PIO_FRLHSR_P_Msk & ((value) << PIO_FRLHSR_P_Pos)) 6411 6412 /* -------- PIO_LOCKSR : (PIO Offset: 0xe0) (R/ 32) Lock Status -------- */ 6413 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 6414 #if COMPONENT_TYPEDEF_STYLE == 'N' 6415 typedef union { 6416 struct { 6417 uint32_t P0:1; /**< bit: 0 Lock Status */ 6418 uint32_t P1:1; /**< bit: 1 Lock Status */ 6419 uint32_t P2:1; /**< bit: 2 Lock Status */ 6420 uint32_t P3:1; /**< bit: 3 Lock Status */ 6421 uint32_t P4:1; /**< bit: 4 Lock Status */ 6422 uint32_t P5:1; /**< bit: 5 Lock Status */ 6423 uint32_t P6:1; /**< bit: 6 Lock Status */ 6424 uint32_t P7:1; /**< bit: 7 Lock Status */ 6425 uint32_t P8:1; /**< bit: 8 Lock Status */ 6426 uint32_t P9:1; /**< bit: 9 Lock Status */ 6427 uint32_t P10:1; /**< bit: 10 Lock Status */ 6428 uint32_t P11:1; /**< bit: 11 Lock Status */ 6429 uint32_t P12:1; /**< bit: 12 Lock Status */ 6430 uint32_t P13:1; /**< bit: 13 Lock Status */ 6431 uint32_t P14:1; /**< bit: 14 Lock Status */ 6432 uint32_t P15:1; /**< bit: 15 Lock Status */ 6433 uint32_t P16:1; /**< bit: 16 Lock Status */ 6434 uint32_t P17:1; /**< bit: 17 Lock Status */ 6435 uint32_t P18:1; /**< bit: 18 Lock Status */ 6436 uint32_t P19:1; /**< bit: 19 Lock Status */ 6437 uint32_t P20:1; /**< bit: 20 Lock Status */ 6438 uint32_t P21:1; /**< bit: 21 Lock Status */ 6439 uint32_t P22:1; /**< bit: 22 Lock Status */ 6440 uint32_t P23:1; /**< bit: 23 Lock Status */ 6441 uint32_t P24:1; /**< bit: 24 Lock Status */ 6442 uint32_t P25:1; /**< bit: 25 Lock Status */ 6443 uint32_t P26:1; /**< bit: 26 Lock Status */ 6444 uint32_t P27:1; /**< bit: 27 Lock Status */ 6445 uint32_t P28:1; /**< bit: 28 Lock Status */ 6446 uint32_t P29:1; /**< bit: 29 Lock Status */ 6447 uint32_t P30:1; /**< bit: 30 Lock Status */ 6448 uint32_t P31:1; /**< bit: 31 Lock Status */ 6449 } bit; /**< Structure used for bit access */ 6450 struct { 6451 uint32_t P:32; /**< bit: 0..31 Lock Status */ 6452 } vec; /**< Structure used for vec access */ 6453 uint32_t reg; /**< Type used for register access */ 6454 } PIO_LOCKSR_Type; 6455 #endif 6456 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 6457 6458 #define PIO_LOCKSR_OFFSET (0xE0) /**< (PIO_LOCKSR) Lock Status Offset */ 6459 6460 #define PIO_LOCKSR_P0_Pos 0 /**< (PIO_LOCKSR) Lock Status Position */ 6461 #define PIO_LOCKSR_P0_Msk (_U_(0x1) << PIO_LOCKSR_P0_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6462 #define PIO_LOCKSR_P0 PIO_LOCKSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P0_Msk instead */ 6463 #define PIO_LOCKSR_P1_Pos 1 /**< (PIO_LOCKSR) Lock Status Position */ 6464 #define PIO_LOCKSR_P1_Msk (_U_(0x1) << PIO_LOCKSR_P1_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6465 #define PIO_LOCKSR_P1 PIO_LOCKSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P1_Msk instead */ 6466 #define PIO_LOCKSR_P2_Pos 2 /**< (PIO_LOCKSR) Lock Status Position */ 6467 #define PIO_LOCKSR_P2_Msk (_U_(0x1) << PIO_LOCKSR_P2_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6468 #define PIO_LOCKSR_P2 PIO_LOCKSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P2_Msk instead */ 6469 #define PIO_LOCKSR_P3_Pos 3 /**< (PIO_LOCKSR) Lock Status Position */ 6470 #define PIO_LOCKSR_P3_Msk (_U_(0x1) << PIO_LOCKSR_P3_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6471 #define PIO_LOCKSR_P3 PIO_LOCKSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P3_Msk instead */ 6472 #define PIO_LOCKSR_P4_Pos 4 /**< (PIO_LOCKSR) Lock Status Position */ 6473 #define PIO_LOCKSR_P4_Msk (_U_(0x1) << PIO_LOCKSR_P4_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6474 #define PIO_LOCKSR_P4 PIO_LOCKSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P4_Msk instead */ 6475 #define PIO_LOCKSR_P5_Pos 5 /**< (PIO_LOCKSR) Lock Status Position */ 6476 #define PIO_LOCKSR_P5_Msk (_U_(0x1) << PIO_LOCKSR_P5_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6477 #define PIO_LOCKSR_P5 PIO_LOCKSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P5_Msk instead */ 6478 #define PIO_LOCKSR_P6_Pos 6 /**< (PIO_LOCKSR) Lock Status Position */ 6479 #define PIO_LOCKSR_P6_Msk (_U_(0x1) << PIO_LOCKSR_P6_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6480 #define PIO_LOCKSR_P6 PIO_LOCKSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P6_Msk instead */ 6481 #define PIO_LOCKSR_P7_Pos 7 /**< (PIO_LOCKSR) Lock Status Position */ 6482 #define PIO_LOCKSR_P7_Msk (_U_(0x1) << PIO_LOCKSR_P7_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6483 #define PIO_LOCKSR_P7 PIO_LOCKSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P7_Msk instead */ 6484 #define PIO_LOCKSR_P8_Pos 8 /**< (PIO_LOCKSR) Lock Status Position */ 6485 #define PIO_LOCKSR_P8_Msk (_U_(0x1) << PIO_LOCKSR_P8_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6486 #define PIO_LOCKSR_P8 PIO_LOCKSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P8_Msk instead */ 6487 #define PIO_LOCKSR_P9_Pos 9 /**< (PIO_LOCKSR) Lock Status Position */ 6488 #define PIO_LOCKSR_P9_Msk (_U_(0x1) << PIO_LOCKSR_P9_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6489 #define PIO_LOCKSR_P9 PIO_LOCKSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P9_Msk instead */ 6490 #define PIO_LOCKSR_P10_Pos 10 /**< (PIO_LOCKSR) Lock Status Position */ 6491 #define PIO_LOCKSR_P10_Msk (_U_(0x1) << PIO_LOCKSR_P10_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6492 #define PIO_LOCKSR_P10 PIO_LOCKSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P10_Msk instead */ 6493 #define PIO_LOCKSR_P11_Pos 11 /**< (PIO_LOCKSR) Lock Status Position */ 6494 #define PIO_LOCKSR_P11_Msk (_U_(0x1) << PIO_LOCKSR_P11_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6495 #define PIO_LOCKSR_P11 PIO_LOCKSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P11_Msk instead */ 6496 #define PIO_LOCKSR_P12_Pos 12 /**< (PIO_LOCKSR) Lock Status Position */ 6497 #define PIO_LOCKSR_P12_Msk (_U_(0x1) << PIO_LOCKSR_P12_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6498 #define PIO_LOCKSR_P12 PIO_LOCKSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P12_Msk instead */ 6499 #define PIO_LOCKSR_P13_Pos 13 /**< (PIO_LOCKSR) Lock Status Position */ 6500 #define PIO_LOCKSR_P13_Msk (_U_(0x1) << PIO_LOCKSR_P13_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6501 #define PIO_LOCKSR_P13 PIO_LOCKSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P13_Msk instead */ 6502 #define PIO_LOCKSR_P14_Pos 14 /**< (PIO_LOCKSR) Lock Status Position */ 6503 #define PIO_LOCKSR_P14_Msk (_U_(0x1) << PIO_LOCKSR_P14_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6504 #define PIO_LOCKSR_P14 PIO_LOCKSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P14_Msk instead */ 6505 #define PIO_LOCKSR_P15_Pos 15 /**< (PIO_LOCKSR) Lock Status Position */ 6506 #define PIO_LOCKSR_P15_Msk (_U_(0x1) << PIO_LOCKSR_P15_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6507 #define PIO_LOCKSR_P15 PIO_LOCKSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P15_Msk instead */ 6508 #define PIO_LOCKSR_P16_Pos 16 /**< (PIO_LOCKSR) Lock Status Position */ 6509 #define PIO_LOCKSR_P16_Msk (_U_(0x1) << PIO_LOCKSR_P16_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6510 #define PIO_LOCKSR_P16 PIO_LOCKSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P16_Msk instead */ 6511 #define PIO_LOCKSR_P17_Pos 17 /**< (PIO_LOCKSR) Lock Status Position */ 6512 #define PIO_LOCKSR_P17_Msk (_U_(0x1) << PIO_LOCKSR_P17_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6513 #define PIO_LOCKSR_P17 PIO_LOCKSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P17_Msk instead */ 6514 #define PIO_LOCKSR_P18_Pos 18 /**< (PIO_LOCKSR) Lock Status Position */ 6515 #define PIO_LOCKSR_P18_Msk (_U_(0x1) << PIO_LOCKSR_P18_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6516 #define PIO_LOCKSR_P18 PIO_LOCKSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P18_Msk instead */ 6517 #define PIO_LOCKSR_P19_Pos 19 /**< (PIO_LOCKSR) Lock Status Position */ 6518 #define PIO_LOCKSR_P19_Msk (_U_(0x1) << PIO_LOCKSR_P19_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6519 #define PIO_LOCKSR_P19 PIO_LOCKSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P19_Msk instead */ 6520 #define PIO_LOCKSR_P20_Pos 20 /**< (PIO_LOCKSR) Lock Status Position */ 6521 #define PIO_LOCKSR_P20_Msk (_U_(0x1) << PIO_LOCKSR_P20_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6522 #define PIO_LOCKSR_P20 PIO_LOCKSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P20_Msk instead */ 6523 #define PIO_LOCKSR_P21_Pos 21 /**< (PIO_LOCKSR) Lock Status Position */ 6524 #define PIO_LOCKSR_P21_Msk (_U_(0x1) << PIO_LOCKSR_P21_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6525 #define PIO_LOCKSR_P21 PIO_LOCKSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P21_Msk instead */ 6526 #define PIO_LOCKSR_P22_Pos 22 /**< (PIO_LOCKSR) Lock Status Position */ 6527 #define PIO_LOCKSR_P22_Msk (_U_(0x1) << PIO_LOCKSR_P22_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6528 #define PIO_LOCKSR_P22 PIO_LOCKSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P22_Msk instead */ 6529 #define PIO_LOCKSR_P23_Pos 23 /**< (PIO_LOCKSR) Lock Status Position */ 6530 #define PIO_LOCKSR_P23_Msk (_U_(0x1) << PIO_LOCKSR_P23_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6531 #define PIO_LOCKSR_P23 PIO_LOCKSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P23_Msk instead */ 6532 #define PIO_LOCKSR_P24_Pos 24 /**< (PIO_LOCKSR) Lock Status Position */ 6533 #define PIO_LOCKSR_P24_Msk (_U_(0x1) << PIO_LOCKSR_P24_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6534 #define PIO_LOCKSR_P24 PIO_LOCKSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P24_Msk instead */ 6535 #define PIO_LOCKSR_P25_Pos 25 /**< (PIO_LOCKSR) Lock Status Position */ 6536 #define PIO_LOCKSR_P25_Msk (_U_(0x1) << PIO_LOCKSR_P25_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6537 #define PIO_LOCKSR_P25 PIO_LOCKSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P25_Msk instead */ 6538 #define PIO_LOCKSR_P26_Pos 26 /**< (PIO_LOCKSR) Lock Status Position */ 6539 #define PIO_LOCKSR_P26_Msk (_U_(0x1) << PIO_LOCKSR_P26_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6540 #define PIO_LOCKSR_P26 PIO_LOCKSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P26_Msk instead */ 6541 #define PIO_LOCKSR_P27_Pos 27 /**< (PIO_LOCKSR) Lock Status Position */ 6542 #define PIO_LOCKSR_P27_Msk (_U_(0x1) << PIO_LOCKSR_P27_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6543 #define PIO_LOCKSR_P27 PIO_LOCKSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P27_Msk instead */ 6544 #define PIO_LOCKSR_P28_Pos 28 /**< (PIO_LOCKSR) Lock Status Position */ 6545 #define PIO_LOCKSR_P28_Msk (_U_(0x1) << PIO_LOCKSR_P28_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6546 #define PIO_LOCKSR_P28 PIO_LOCKSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P28_Msk instead */ 6547 #define PIO_LOCKSR_P29_Pos 29 /**< (PIO_LOCKSR) Lock Status Position */ 6548 #define PIO_LOCKSR_P29_Msk (_U_(0x1) << PIO_LOCKSR_P29_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6549 #define PIO_LOCKSR_P29 PIO_LOCKSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P29_Msk instead */ 6550 #define PIO_LOCKSR_P30_Pos 30 /**< (PIO_LOCKSR) Lock Status Position */ 6551 #define PIO_LOCKSR_P30_Msk (_U_(0x1) << PIO_LOCKSR_P30_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6552 #define PIO_LOCKSR_P30 PIO_LOCKSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P30_Msk instead */ 6553 #define PIO_LOCKSR_P31_Pos 31 /**< (PIO_LOCKSR) Lock Status Position */ 6554 #define PIO_LOCKSR_P31_Msk (_U_(0x1) << PIO_LOCKSR_P31_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ 6555 #define PIO_LOCKSR_P31 PIO_LOCKSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P31_Msk instead */ 6556 #define PIO_LOCKSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_LOCKSR) Register MASK (Use PIO_LOCKSR_Msk instead) */ 6557 #define PIO_LOCKSR_Msk _U_(0xFFFFFFFF) /**< (PIO_LOCKSR) Register Mask */ 6558 6559 #define PIO_LOCKSR_P_Pos 0 /**< (PIO_LOCKSR Position) Lock Status */ 6560 #define PIO_LOCKSR_P_Msk (_U_(0xFFFFFFFF) << PIO_LOCKSR_P_Pos) /**< (PIO_LOCKSR Mask) P */ 6561 #define PIO_LOCKSR_P(value) (PIO_LOCKSR_P_Msk & ((value) << PIO_LOCKSR_P_Pos)) 6562 6563 /* -------- PIO_WPMR : (PIO Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 6564 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 6565 #if COMPONENT_TYPEDEF_STYLE == 'N' 6566 typedef union { 6567 struct { 6568 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 6569 uint32_t :7; /**< bit: 1..7 Reserved */ 6570 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 6571 } bit; /**< Structure used for bit access */ 6572 uint32_t reg; /**< Type used for register access */ 6573 } PIO_WPMR_Type; 6574 #endif 6575 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 6576 6577 #define PIO_WPMR_OFFSET (0xE4) /**< (PIO_WPMR) Write Protection Mode Register Offset */ 6578 6579 #define PIO_WPMR_WPEN_Pos 0 /**< (PIO_WPMR) Write Protection Enable Position */ 6580 #define PIO_WPMR_WPEN_Msk (_U_(0x1) << PIO_WPMR_WPEN_Pos) /**< (PIO_WPMR) Write Protection Enable Mask */ 6581 #define PIO_WPMR_WPEN PIO_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_WPMR_WPEN_Msk instead */ 6582 #define PIO_WPMR_WPKEY_Pos 8 /**< (PIO_WPMR) Write Protection Key Position */ 6583 #define PIO_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PIO_WPMR_WPKEY_Pos) /**< (PIO_WPMR) Write Protection Key Mask */ 6584 #define PIO_WPMR_WPKEY(value) (PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)) 6585 #define PIO_WPMR_WPKEY_PASSWD_Val _U_(0x50494F) /**< (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 6586 #define PIO_WPMR_WPKEY_PASSWD (PIO_WPMR_WPKEY_PASSWD_Val << PIO_WPMR_WPKEY_Pos) /**< (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ 6587 #define PIO_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (PIO_WPMR) Register MASK (Use PIO_WPMR_Msk instead) */ 6588 #define PIO_WPMR_Msk _U_(0xFFFFFF01) /**< (PIO_WPMR) Register Mask */ 6589 6590 6591 /* -------- PIO_WPSR : (PIO Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ 6592 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 6593 #if COMPONENT_TYPEDEF_STYLE == 'N' 6594 typedef union { 6595 struct { 6596 uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ 6597 uint32_t :7; /**< bit: 1..7 Reserved */ 6598 uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ 6599 uint32_t :8; /**< bit: 24..31 Reserved */ 6600 } bit; /**< Structure used for bit access */ 6601 uint32_t reg; /**< Type used for register access */ 6602 } PIO_WPSR_Type; 6603 #endif 6604 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 6605 6606 #define PIO_WPSR_OFFSET (0xE8) /**< (PIO_WPSR) Write Protection Status Register Offset */ 6607 6608 #define PIO_WPSR_WPVS_Pos 0 /**< (PIO_WPSR) Write Protection Violation Status Position */ 6609 #define PIO_WPSR_WPVS_Msk (_U_(0x1) << PIO_WPSR_WPVS_Pos) /**< (PIO_WPSR) Write Protection Violation Status Mask */ 6610 #define PIO_WPSR_WPVS PIO_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_WPSR_WPVS_Msk instead */ 6611 #define PIO_WPSR_WPVSRC_Pos 8 /**< (PIO_WPSR) Write Protection Violation Source Position */ 6612 #define PIO_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PIO_WPSR_WPVSRC_Pos) /**< (PIO_WPSR) Write Protection Violation Source Mask */ 6613 #define PIO_WPSR_WPVSRC(value) (PIO_WPSR_WPVSRC_Msk & ((value) << PIO_WPSR_WPVSRC_Pos)) 6614 #define PIO_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (PIO_WPSR) Register MASK (Use PIO_WPSR_Msk instead) */ 6615 #define PIO_WPSR_Msk _U_(0xFFFF01) /**< (PIO_WPSR) Register Mask */ 6616 6617 6618 /* -------- PIO_SCHMITT : (PIO Offset: 0x100) (R/W 32) Schmitt Trigger Register -------- */ 6619 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 6620 #if COMPONENT_TYPEDEF_STYLE == 'N' 6621 typedef union { 6622 struct { 6623 uint32_t SCHMITT0:1; /**< bit: 0 Schmitt Trigger Control */ 6624 uint32_t SCHMITT1:1; /**< bit: 1 Schmitt Trigger Control */ 6625 uint32_t SCHMITT2:1; /**< bit: 2 Schmitt Trigger Control */ 6626 uint32_t SCHMITT3:1; /**< bit: 3 Schmitt Trigger Control */ 6627 uint32_t SCHMITT4:1; /**< bit: 4 Schmitt Trigger Control */ 6628 uint32_t SCHMITT5:1; /**< bit: 5 Schmitt Trigger Control */ 6629 uint32_t SCHMITT6:1; /**< bit: 6 Schmitt Trigger Control */ 6630 uint32_t SCHMITT7:1; /**< bit: 7 Schmitt Trigger Control */ 6631 uint32_t SCHMITT8:1; /**< bit: 8 Schmitt Trigger Control */ 6632 uint32_t SCHMITT9:1; /**< bit: 9 Schmitt Trigger Control */ 6633 uint32_t SCHMITT10:1; /**< bit: 10 Schmitt Trigger Control */ 6634 uint32_t SCHMITT11:1; /**< bit: 11 Schmitt Trigger Control */ 6635 uint32_t SCHMITT12:1; /**< bit: 12 Schmitt Trigger Control */ 6636 uint32_t SCHMITT13:1; /**< bit: 13 Schmitt Trigger Control */ 6637 uint32_t SCHMITT14:1; /**< bit: 14 Schmitt Trigger Control */ 6638 uint32_t SCHMITT15:1; /**< bit: 15 Schmitt Trigger Control */ 6639 uint32_t SCHMITT16:1; /**< bit: 16 Schmitt Trigger Control */ 6640 uint32_t SCHMITT17:1; /**< bit: 17 Schmitt Trigger Control */ 6641 uint32_t SCHMITT18:1; /**< bit: 18 Schmitt Trigger Control */ 6642 uint32_t SCHMITT19:1; /**< bit: 19 Schmitt Trigger Control */ 6643 uint32_t SCHMITT20:1; /**< bit: 20 Schmitt Trigger Control */ 6644 uint32_t SCHMITT21:1; /**< bit: 21 Schmitt Trigger Control */ 6645 uint32_t SCHMITT22:1; /**< bit: 22 Schmitt Trigger Control */ 6646 uint32_t SCHMITT23:1; /**< bit: 23 Schmitt Trigger Control */ 6647 uint32_t SCHMITT24:1; /**< bit: 24 Schmitt Trigger Control */ 6648 uint32_t SCHMITT25:1; /**< bit: 25 Schmitt Trigger Control */ 6649 uint32_t SCHMITT26:1; /**< bit: 26 Schmitt Trigger Control */ 6650 uint32_t SCHMITT27:1; /**< bit: 27 Schmitt Trigger Control */ 6651 uint32_t SCHMITT28:1; /**< bit: 28 Schmitt Trigger Control */ 6652 uint32_t SCHMITT29:1; /**< bit: 29 Schmitt Trigger Control */ 6653 uint32_t SCHMITT30:1; /**< bit: 30 Schmitt Trigger Control */ 6654 uint32_t SCHMITT31:1; /**< bit: 31 Schmitt Trigger Control */ 6655 } bit; /**< Structure used for bit access */ 6656 struct { 6657 uint32_t SCHMITT:32; /**< bit: 0..31 Schmitt Trigger Control */ 6658 } vec; /**< Structure used for vec access */ 6659 uint32_t reg; /**< Type used for register access */ 6660 } PIO_SCHMITT_Type; 6661 #endif 6662 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 6663 6664 #define PIO_SCHMITT_OFFSET (0x100) /**< (PIO_SCHMITT) Schmitt Trigger Register Offset */ 6665 6666 #define PIO_SCHMITT_SCHMITT0_Pos 0 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6667 #define PIO_SCHMITT_SCHMITT0_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT0_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6668 #define PIO_SCHMITT_SCHMITT0 PIO_SCHMITT_SCHMITT0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT0_Msk instead */ 6669 #define PIO_SCHMITT_SCHMITT1_Pos 1 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6670 #define PIO_SCHMITT_SCHMITT1_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT1_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6671 #define PIO_SCHMITT_SCHMITT1 PIO_SCHMITT_SCHMITT1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT1_Msk instead */ 6672 #define PIO_SCHMITT_SCHMITT2_Pos 2 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6673 #define PIO_SCHMITT_SCHMITT2_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT2_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6674 #define PIO_SCHMITT_SCHMITT2 PIO_SCHMITT_SCHMITT2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT2_Msk instead */ 6675 #define PIO_SCHMITT_SCHMITT3_Pos 3 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6676 #define PIO_SCHMITT_SCHMITT3_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT3_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6677 #define PIO_SCHMITT_SCHMITT3 PIO_SCHMITT_SCHMITT3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT3_Msk instead */ 6678 #define PIO_SCHMITT_SCHMITT4_Pos 4 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6679 #define PIO_SCHMITT_SCHMITT4_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT4_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6680 #define PIO_SCHMITT_SCHMITT4 PIO_SCHMITT_SCHMITT4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT4_Msk instead */ 6681 #define PIO_SCHMITT_SCHMITT5_Pos 5 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6682 #define PIO_SCHMITT_SCHMITT5_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT5_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6683 #define PIO_SCHMITT_SCHMITT5 PIO_SCHMITT_SCHMITT5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT5_Msk instead */ 6684 #define PIO_SCHMITT_SCHMITT6_Pos 6 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6685 #define PIO_SCHMITT_SCHMITT6_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT6_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6686 #define PIO_SCHMITT_SCHMITT6 PIO_SCHMITT_SCHMITT6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT6_Msk instead */ 6687 #define PIO_SCHMITT_SCHMITT7_Pos 7 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6688 #define PIO_SCHMITT_SCHMITT7_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT7_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6689 #define PIO_SCHMITT_SCHMITT7 PIO_SCHMITT_SCHMITT7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT7_Msk instead */ 6690 #define PIO_SCHMITT_SCHMITT8_Pos 8 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6691 #define PIO_SCHMITT_SCHMITT8_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT8_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6692 #define PIO_SCHMITT_SCHMITT8 PIO_SCHMITT_SCHMITT8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT8_Msk instead */ 6693 #define PIO_SCHMITT_SCHMITT9_Pos 9 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6694 #define PIO_SCHMITT_SCHMITT9_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT9_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6695 #define PIO_SCHMITT_SCHMITT9 PIO_SCHMITT_SCHMITT9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT9_Msk instead */ 6696 #define PIO_SCHMITT_SCHMITT10_Pos 10 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6697 #define PIO_SCHMITT_SCHMITT10_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT10_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6698 #define PIO_SCHMITT_SCHMITT10 PIO_SCHMITT_SCHMITT10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT10_Msk instead */ 6699 #define PIO_SCHMITT_SCHMITT11_Pos 11 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6700 #define PIO_SCHMITT_SCHMITT11_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT11_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6701 #define PIO_SCHMITT_SCHMITT11 PIO_SCHMITT_SCHMITT11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT11_Msk instead */ 6702 #define PIO_SCHMITT_SCHMITT12_Pos 12 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6703 #define PIO_SCHMITT_SCHMITT12_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT12_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6704 #define PIO_SCHMITT_SCHMITT12 PIO_SCHMITT_SCHMITT12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT12_Msk instead */ 6705 #define PIO_SCHMITT_SCHMITT13_Pos 13 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6706 #define PIO_SCHMITT_SCHMITT13_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT13_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6707 #define PIO_SCHMITT_SCHMITT13 PIO_SCHMITT_SCHMITT13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT13_Msk instead */ 6708 #define PIO_SCHMITT_SCHMITT14_Pos 14 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6709 #define PIO_SCHMITT_SCHMITT14_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT14_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6710 #define PIO_SCHMITT_SCHMITT14 PIO_SCHMITT_SCHMITT14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT14_Msk instead */ 6711 #define PIO_SCHMITT_SCHMITT15_Pos 15 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6712 #define PIO_SCHMITT_SCHMITT15_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT15_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6713 #define PIO_SCHMITT_SCHMITT15 PIO_SCHMITT_SCHMITT15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT15_Msk instead */ 6714 #define PIO_SCHMITT_SCHMITT16_Pos 16 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6715 #define PIO_SCHMITT_SCHMITT16_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT16_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6716 #define PIO_SCHMITT_SCHMITT16 PIO_SCHMITT_SCHMITT16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT16_Msk instead */ 6717 #define PIO_SCHMITT_SCHMITT17_Pos 17 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6718 #define PIO_SCHMITT_SCHMITT17_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT17_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6719 #define PIO_SCHMITT_SCHMITT17 PIO_SCHMITT_SCHMITT17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT17_Msk instead */ 6720 #define PIO_SCHMITT_SCHMITT18_Pos 18 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6721 #define PIO_SCHMITT_SCHMITT18_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT18_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6722 #define PIO_SCHMITT_SCHMITT18 PIO_SCHMITT_SCHMITT18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT18_Msk instead */ 6723 #define PIO_SCHMITT_SCHMITT19_Pos 19 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6724 #define PIO_SCHMITT_SCHMITT19_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT19_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6725 #define PIO_SCHMITT_SCHMITT19 PIO_SCHMITT_SCHMITT19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT19_Msk instead */ 6726 #define PIO_SCHMITT_SCHMITT20_Pos 20 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6727 #define PIO_SCHMITT_SCHMITT20_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT20_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6728 #define PIO_SCHMITT_SCHMITT20 PIO_SCHMITT_SCHMITT20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT20_Msk instead */ 6729 #define PIO_SCHMITT_SCHMITT21_Pos 21 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6730 #define PIO_SCHMITT_SCHMITT21_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT21_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6731 #define PIO_SCHMITT_SCHMITT21 PIO_SCHMITT_SCHMITT21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT21_Msk instead */ 6732 #define PIO_SCHMITT_SCHMITT22_Pos 22 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6733 #define PIO_SCHMITT_SCHMITT22_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT22_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6734 #define PIO_SCHMITT_SCHMITT22 PIO_SCHMITT_SCHMITT22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT22_Msk instead */ 6735 #define PIO_SCHMITT_SCHMITT23_Pos 23 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6736 #define PIO_SCHMITT_SCHMITT23_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT23_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6737 #define PIO_SCHMITT_SCHMITT23 PIO_SCHMITT_SCHMITT23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT23_Msk instead */ 6738 #define PIO_SCHMITT_SCHMITT24_Pos 24 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6739 #define PIO_SCHMITT_SCHMITT24_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT24_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6740 #define PIO_SCHMITT_SCHMITT24 PIO_SCHMITT_SCHMITT24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT24_Msk instead */ 6741 #define PIO_SCHMITT_SCHMITT25_Pos 25 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6742 #define PIO_SCHMITT_SCHMITT25_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT25_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6743 #define PIO_SCHMITT_SCHMITT25 PIO_SCHMITT_SCHMITT25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT25_Msk instead */ 6744 #define PIO_SCHMITT_SCHMITT26_Pos 26 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6745 #define PIO_SCHMITT_SCHMITT26_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT26_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6746 #define PIO_SCHMITT_SCHMITT26 PIO_SCHMITT_SCHMITT26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT26_Msk instead */ 6747 #define PIO_SCHMITT_SCHMITT27_Pos 27 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6748 #define PIO_SCHMITT_SCHMITT27_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT27_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6749 #define PIO_SCHMITT_SCHMITT27 PIO_SCHMITT_SCHMITT27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT27_Msk instead */ 6750 #define PIO_SCHMITT_SCHMITT28_Pos 28 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6751 #define PIO_SCHMITT_SCHMITT28_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT28_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6752 #define PIO_SCHMITT_SCHMITT28 PIO_SCHMITT_SCHMITT28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT28_Msk instead */ 6753 #define PIO_SCHMITT_SCHMITT29_Pos 29 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6754 #define PIO_SCHMITT_SCHMITT29_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT29_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6755 #define PIO_SCHMITT_SCHMITT29 PIO_SCHMITT_SCHMITT29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT29_Msk instead */ 6756 #define PIO_SCHMITT_SCHMITT30_Pos 30 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6757 #define PIO_SCHMITT_SCHMITT30_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT30_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6758 #define PIO_SCHMITT_SCHMITT30 PIO_SCHMITT_SCHMITT30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT30_Msk instead */ 6759 #define PIO_SCHMITT_SCHMITT31_Pos 31 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ 6760 #define PIO_SCHMITT_SCHMITT31_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT31_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ 6761 #define PIO_SCHMITT_SCHMITT31 PIO_SCHMITT_SCHMITT31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT31_Msk instead */ 6762 #define PIO_SCHMITT_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_SCHMITT) Register MASK (Use PIO_SCHMITT_Msk instead) */ 6763 #define PIO_SCHMITT_Msk _U_(0xFFFFFFFF) /**< (PIO_SCHMITT) Register Mask */ 6764 6765 #define PIO_SCHMITT_SCHMITT_Pos 0 /**< (PIO_SCHMITT Position) Schmitt Trigger Control */ 6766 #define PIO_SCHMITT_SCHMITT_Msk (_U_(0xFFFFFFFF) << PIO_SCHMITT_SCHMITT_Pos) /**< (PIO_SCHMITT Mask) SCHMITT */ 6767 #define PIO_SCHMITT_SCHMITT(value) (PIO_SCHMITT_SCHMITT_Msk & ((value) << PIO_SCHMITT_SCHMITT_Pos)) 6768 6769 /* -------- PIO_DRIVER : (PIO Offset: 0x118) (R/W 32) I/O Drive Register -------- */ 6770 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 6771 #if COMPONENT_TYPEDEF_STYLE == 'N' 6772 typedef union { 6773 struct { 6774 uint32_t LINE0:1; /**< bit: 0 Drive of PIO Line 0 */ 6775 uint32_t LINE1:1; /**< bit: 1 Drive of PIO Line 1 */ 6776 uint32_t LINE2:1; /**< bit: 2 Drive of PIO Line 2 */ 6777 uint32_t LINE3:1; /**< bit: 3 Drive of PIO Line 3 */ 6778 uint32_t LINE4:1; /**< bit: 4 Drive of PIO Line 4 */ 6779 uint32_t LINE5:1; /**< bit: 5 Drive of PIO Line 5 */ 6780 uint32_t LINE6:1; /**< bit: 6 Drive of PIO Line 6 */ 6781 uint32_t LINE7:1; /**< bit: 7 Drive of PIO Line 7 */ 6782 uint32_t LINE8:1; /**< bit: 8 Drive of PIO Line 8 */ 6783 uint32_t LINE9:1; /**< bit: 9 Drive of PIO Line 9 */ 6784 uint32_t LINE10:1; /**< bit: 10 Drive of PIO Line 10 */ 6785 uint32_t LINE11:1; /**< bit: 11 Drive of PIO Line 11 */ 6786 uint32_t LINE12:1; /**< bit: 12 Drive of PIO Line 12 */ 6787 uint32_t LINE13:1; /**< bit: 13 Drive of PIO Line 13 */ 6788 uint32_t LINE14:1; /**< bit: 14 Drive of PIO Line 14 */ 6789 uint32_t LINE15:1; /**< bit: 15 Drive of PIO Line 15 */ 6790 uint32_t LINE16:1; /**< bit: 16 Drive of PIO Line 16 */ 6791 uint32_t LINE17:1; /**< bit: 17 Drive of PIO Line 17 */ 6792 uint32_t LINE18:1; /**< bit: 18 Drive of PIO Line 18 */ 6793 uint32_t LINE19:1; /**< bit: 19 Drive of PIO Line 19 */ 6794 uint32_t LINE20:1; /**< bit: 20 Drive of PIO Line 20 */ 6795 uint32_t LINE21:1; /**< bit: 21 Drive of PIO Line 21 */ 6796 uint32_t LINE22:1; /**< bit: 22 Drive of PIO Line 22 */ 6797 uint32_t LINE23:1; /**< bit: 23 Drive of PIO Line 23 */ 6798 uint32_t LINE24:1; /**< bit: 24 Drive of PIO Line 24 */ 6799 uint32_t LINE25:1; /**< bit: 25 Drive of PIO Line 25 */ 6800 uint32_t LINE26:1; /**< bit: 26 Drive of PIO Line 26 */ 6801 uint32_t LINE27:1; /**< bit: 27 Drive of PIO Line 27 */ 6802 uint32_t LINE28:1; /**< bit: 28 Drive of PIO Line 28 */ 6803 uint32_t LINE29:1; /**< bit: 29 Drive of PIO Line 29 */ 6804 uint32_t LINE30:1; /**< bit: 30 Drive of PIO Line 30 */ 6805 uint32_t LINE31:1; /**< bit: 31 Drive of PIO Line 31 */ 6806 } bit; /**< Structure used for bit access */ 6807 struct { 6808 uint32_t LINE:32; /**< bit: 0..31 Drive of PIO Line 3x */ 6809 } vec; /**< Structure used for vec access */ 6810 uint32_t reg; /**< Type used for register access */ 6811 } PIO_DRIVER_Type; 6812 #endif 6813 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 6814 6815 #define PIO_DRIVER_OFFSET (0x118) /**< (PIO_DRIVER) I/O Drive Register Offset */ 6816 6817 #define PIO_DRIVER_LINE0_Pos 0 /**< (PIO_DRIVER) Drive of PIO Line 0 Position */ 6818 #define PIO_DRIVER_LINE0_Msk (_U_(0x1) << PIO_DRIVER_LINE0_Pos) /**< (PIO_DRIVER) Drive of PIO Line 0 Mask */ 6819 #define PIO_DRIVER_LINE0 PIO_DRIVER_LINE0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE0_Msk instead */ 6820 #define PIO_DRIVER_LINE0_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6821 #define PIO_DRIVER_LINE0_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6822 #define PIO_DRIVER_LINE0_LOW_DRIVE (PIO_DRIVER_LINE0_LOW_DRIVE_Val << PIO_DRIVER_LINE0_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6823 #define PIO_DRIVER_LINE0_HIGH_DRIVE (PIO_DRIVER_LINE0_HIGH_DRIVE_Val << PIO_DRIVER_LINE0_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6824 #define PIO_DRIVER_LINE1_Pos 1 /**< (PIO_DRIVER) Drive of PIO Line 1 Position */ 6825 #define PIO_DRIVER_LINE1_Msk (_U_(0x1) << PIO_DRIVER_LINE1_Pos) /**< (PIO_DRIVER) Drive of PIO Line 1 Mask */ 6826 #define PIO_DRIVER_LINE1 PIO_DRIVER_LINE1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE1_Msk instead */ 6827 #define PIO_DRIVER_LINE1_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6828 #define PIO_DRIVER_LINE1_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6829 #define PIO_DRIVER_LINE1_LOW_DRIVE (PIO_DRIVER_LINE1_LOW_DRIVE_Val << PIO_DRIVER_LINE1_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6830 #define PIO_DRIVER_LINE1_HIGH_DRIVE (PIO_DRIVER_LINE1_HIGH_DRIVE_Val << PIO_DRIVER_LINE1_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6831 #define PIO_DRIVER_LINE2_Pos 2 /**< (PIO_DRIVER) Drive of PIO Line 2 Position */ 6832 #define PIO_DRIVER_LINE2_Msk (_U_(0x1) << PIO_DRIVER_LINE2_Pos) /**< (PIO_DRIVER) Drive of PIO Line 2 Mask */ 6833 #define PIO_DRIVER_LINE2 PIO_DRIVER_LINE2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE2_Msk instead */ 6834 #define PIO_DRIVER_LINE2_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6835 #define PIO_DRIVER_LINE2_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6836 #define PIO_DRIVER_LINE2_LOW_DRIVE (PIO_DRIVER_LINE2_LOW_DRIVE_Val << PIO_DRIVER_LINE2_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6837 #define PIO_DRIVER_LINE2_HIGH_DRIVE (PIO_DRIVER_LINE2_HIGH_DRIVE_Val << PIO_DRIVER_LINE2_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6838 #define PIO_DRIVER_LINE3_Pos 3 /**< (PIO_DRIVER) Drive of PIO Line 3 Position */ 6839 #define PIO_DRIVER_LINE3_Msk (_U_(0x1) << PIO_DRIVER_LINE3_Pos) /**< (PIO_DRIVER) Drive of PIO Line 3 Mask */ 6840 #define PIO_DRIVER_LINE3 PIO_DRIVER_LINE3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE3_Msk instead */ 6841 #define PIO_DRIVER_LINE3_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6842 #define PIO_DRIVER_LINE3_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6843 #define PIO_DRIVER_LINE3_LOW_DRIVE (PIO_DRIVER_LINE3_LOW_DRIVE_Val << PIO_DRIVER_LINE3_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6844 #define PIO_DRIVER_LINE3_HIGH_DRIVE (PIO_DRIVER_LINE3_HIGH_DRIVE_Val << PIO_DRIVER_LINE3_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6845 #define PIO_DRIVER_LINE4_Pos 4 /**< (PIO_DRIVER) Drive of PIO Line 4 Position */ 6846 #define PIO_DRIVER_LINE4_Msk (_U_(0x1) << PIO_DRIVER_LINE4_Pos) /**< (PIO_DRIVER) Drive of PIO Line 4 Mask */ 6847 #define PIO_DRIVER_LINE4 PIO_DRIVER_LINE4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE4_Msk instead */ 6848 #define PIO_DRIVER_LINE4_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6849 #define PIO_DRIVER_LINE4_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6850 #define PIO_DRIVER_LINE4_LOW_DRIVE (PIO_DRIVER_LINE4_LOW_DRIVE_Val << PIO_DRIVER_LINE4_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6851 #define PIO_DRIVER_LINE4_HIGH_DRIVE (PIO_DRIVER_LINE4_HIGH_DRIVE_Val << PIO_DRIVER_LINE4_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6852 #define PIO_DRIVER_LINE5_Pos 5 /**< (PIO_DRIVER) Drive of PIO Line 5 Position */ 6853 #define PIO_DRIVER_LINE5_Msk (_U_(0x1) << PIO_DRIVER_LINE5_Pos) /**< (PIO_DRIVER) Drive of PIO Line 5 Mask */ 6854 #define PIO_DRIVER_LINE5 PIO_DRIVER_LINE5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE5_Msk instead */ 6855 #define PIO_DRIVER_LINE5_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6856 #define PIO_DRIVER_LINE5_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6857 #define PIO_DRIVER_LINE5_LOW_DRIVE (PIO_DRIVER_LINE5_LOW_DRIVE_Val << PIO_DRIVER_LINE5_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6858 #define PIO_DRIVER_LINE5_HIGH_DRIVE (PIO_DRIVER_LINE5_HIGH_DRIVE_Val << PIO_DRIVER_LINE5_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6859 #define PIO_DRIVER_LINE6_Pos 6 /**< (PIO_DRIVER) Drive of PIO Line 6 Position */ 6860 #define PIO_DRIVER_LINE6_Msk (_U_(0x1) << PIO_DRIVER_LINE6_Pos) /**< (PIO_DRIVER) Drive of PIO Line 6 Mask */ 6861 #define PIO_DRIVER_LINE6 PIO_DRIVER_LINE6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE6_Msk instead */ 6862 #define PIO_DRIVER_LINE6_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6863 #define PIO_DRIVER_LINE6_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6864 #define PIO_DRIVER_LINE6_LOW_DRIVE (PIO_DRIVER_LINE6_LOW_DRIVE_Val << PIO_DRIVER_LINE6_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6865 #define PIO_DRIVER_LINE6_HIGH_DRIVE (PIO_DRIVER_LINE6_HIGH_DRIVE_Val << PIO_DRIVER_LINE6_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6866 #define PIO_DRIVER_LINE7_Pos 7 /**< (PIO_DRIVER) Drive of PIO Line 7 Position */ 6867 #define PIO_DRIVER_LINE7_Msk (_U_(0x1) << PIO_DRIVER_LINE7_Pos) /**< (PIO_DRIVER) Drive of PIO Line 7 Mask */ 6868 #define PIO_DRIVER_LINE7 PIO_DRIVER_LINE7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE7_Msk instead */ 6869 #define PIO_DRIVER_LINE7_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6870 #define PIO_DRIVER_LINE7_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6871 #define PIO_DRIVER_LINE7_LOW_DRIVE (PIO_DRIVER_LINE7_LOW_DRIVE_Val << PIO_DRIVER_LINE7_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6872 #define PIO_DRIVER_LINE7_HIGH_DRIVE (PIO_DRIVER_LINE7_HIGH_DRIVE_Val << PIO_DRIVER_LINE7_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6873 #define PIO_DRIVER_LINE8_Pos 8 /**< (PIO_DRIVER) Drive of PIO Line 8 Position */ 6874 #define PIO_DRIVER_LINE8_Msk (_U_(0x1) << PIO_DRIVER_LINE8_Pos) /**< (PIO_DRIVER) Drive of PIO Line 8 Mask */ 6875 #define PIO_DRIVER_LINE8 PIO_DRIVER_LINE8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE8_Msk instead */ 6876 #define PIO_DRIVER_LINE8_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6877 #define PIO_DRIVER_LINE8_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6878 #define PIO_DRIVER_LINE8_LOW_DRIVE (PIO_DRIVER_LINE8_LOW_DRIVE_Val << PIO_DRIVER_LINE8_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6879 #define PIO_DRIVER_LINE8_HIGH_DRIVE (PIO_DRIVER_LINE8_HIGH_DRIVE_Val << PIO_DRIVER_LINE8_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6880 #define PIO_DRIVER_LINE9_Pos 9 /**< (PIO_DRIVER) Drive of PIO Line 9 Position */ 6881 #define PIO_DRIVER_LINE9_Msk (_U_(0x1) << PIO_DRIVER_LINE9_Pos) /**< (PIO_DRIVER) Drive of PIO Line 9 Mask */ 6882 #define PIO_DRIVER_LINE9 PIO_DRIVER_LINE9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE9_Msk instead */ 6883 #define PIO_DRIVER_LINE9_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6884 #define PIO_DRIVER_LINE9_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6885 #define PIO_DRIVER_LINE9_LOW_DRIVE (PIO_DRIVER_LINE9_LOW_DRIVE_Val << PIO_DRIVER_LINE9_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6886 #define PIO_DRIVER_LINE9_HIGH_DRIVE (PIO_DRIVER_LINE9_HIGH_DRIVE_Val << PIO_DRIVER_LINE9_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6887 #define PIO_DRIVER_LINE10_Pos 10 /**< (PIO_DRIVER) Drive of PIO Line 10 Position */ 6888 #define PIO_DRIVER_LINE10_Msk (_U_(0x1) << PIO_DRIVER_LINE10_Pos) /**< (PIO_DRIVER) Drive of PIO Line 10 Mask */ 6889 #define PIO_DRIVER_LINE10 PIO_DRIVER_LINE10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE10_Msk instead */ 6890 #define PIO_DRIVER_LINE10_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6891 #define PIO_DRIVER_LINE10_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6892 #define PIO_DRIVER_LINE10_LOW_DRIVE (PIO_DRIVER_LINE10_LOW_DRIVE_Val << PIO_DRIVER_LINE10_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6893 #define PIO_DRIVER_LINE10_HIGH_DRIVE (PIO_DRIVER_LINE10_HIGH_DRIVE_Val << PIO_DRIVER_LINE10_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6894 #define PIO_DRIVER_LINE11_Pos 11 /**< (PIO_DRIVER) Drive of PIO Line 11 Position */ 6895 #define PIO_DRIVER_LINE11_Msk (_U_(0x1) << PIO_DRIVER_LINE11_Pos) /**< (PIO_DRIVER) Drive of PIO Line 11 Mask */ 6896 #define PIO_DRIVER_LINE11 PIO_DRIVER_LINE11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE11_Msk instead */ 6897 #define PIO_DRIVER_LINE11_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6898 #define PIO_DRIVER_LINE11_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6899 #define PIO_DRIVER_LINE11_LOW_DRIVE (PIO_DRIVER_LINE11_LOW_DRIVE_Val << PIO_DRIVER_LINE11_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6900 #define PIO_DRIVER_LINE11_HIGH_DRIVE (PIO_DRIVER_LINE11_HIGH_DRIVE_Val << PIO_DRIVER_LINE11_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6901 #define PIO_DRIVER_LINE12_Pos 12 /**< (PIO_DRIVER) Drive of PIO Line 12 Position */ 6902 #define PIO_DRIVER_LINE12_Msk (_U_(0x1) << PIO_DRIVER_LINE12_Pos) /**< (PIO_DRIVER) Drive of PIO Line 12 Mask */ 6903 #define PIO_DRIVER_LINE12 PIO_DRIVER_LINE12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE12_Msk instead */ 6904 #define PIO_DRIVER_LINE12_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6905 #define PIO_DRIVER_LINE12_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6906 #define PIO_DRIVER_LINE12_LOW_DRIVE (PIO_DRIVER_LINE12_LOW_DRIVE_Val << PIO_DRIVER_LINE12_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6907 #define PIO_DRIVER_LINE12_HIGH_DRIVE (PIO_DRIVER_LINE12_HIGH_DRIVE_Val << PIO_DRIVER_LINE12_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6908 #define PIO_DRIVER_LINE13_Pos 13 /**< (PIO_DRIVER) Drive of PIO Line 13 Position */ 6909 #define PIO_DRIVER_LINE13_Msk (_U_(0x1) << PIO_DRIVER_LINE13_Pos) /**< (PIO_DRIVER) Drive of PIO Line 13 Mask */ 6910 #define PIO_DRIVER_LINE13 PIO_DRIVER_LINE13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE13_Msk instead */ 6911 #define PIO_DRIVER_LINE13_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6912 #define PIO_DRIVER_LINE13_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6913 #define PIO_DRIVER_LINE13_LOW_DRIVE (PIO_DRIVER_LINE13_LOW_DRIVE_Val << PIO_DRIVER_LINE13_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6914 #define PIO_DRIVER_LINE13_HIGH_DRIVE (PIO_DRIVER_LINE13_HIGH_DRIVE_Val << PIO_DRIVER_LINE13_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6915 #define PIO_DRIVER_LINE14_Pos 14 /**< (PIO_DRIVER) Drive of PIO Line 14 Position */ 6916 #define PIO_DRIVER_LINE14_Msk (_U_(0x1) << PIO_DRIVER_LINE14_Pos) /**< (PIO_DRIVER) Drive of PIO Line 14 Mask */ 6917 #define PIO_DRIVER_LINE14 PIO_DRIVER_LINE14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE14_Msk instead */ 6918 #define PIO_DRIVER_LINE14_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6919 #define PIO_DRIVER_LINE14_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6920 #define PIO_DRIVER_LINE14_LOW_DRIVE (PIO_DRIVER_LINE14_LOW_DRIVE_Val << PIO_DRIVER_LINE14_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6921 #define PIO_DRIVER_LINE14_HIGH_DRIVE (PIO_DRIVER_LINE14_HIGH_DRIVE_Val << PIO_DRIVER_LINE14_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6922 #define PIO_DRIVER_LINE15_Pos 15 /**< (PIO_DRIVER) Drive of PIO Line 15 Position */ 6923 #define PIO_DRIVER_LINE15_Msk (_U_(0x1) << PIO_DRIVER_LINE15_Pos) /**< (PIO_DRIVER) Drive of PIO Line 15 Mask */ 6924 #define PIO_DRIVER_LINE15 PIO_DRIVER_LINE15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE15_Msk instead */ 6925 #define PIO_DRIVER_LINE15_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6926 #define PIO_DRIVER_LINE15_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6927 #define PIO_DRIVER_LINE15_LOW_DRIVE (PIO_DRIVER_LINE15_LOW_DRIVE_Val << PIO_DRIVER_LINE15_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6928 #define PIO_DRIVER_LINE15_HIGH_DRIVE (PIO_DRIVER_LINE15_HIGH_DRIVE_Val << PIO_DRIVER_LINE15_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6929 #define PIO_DRIVER_LINE16_Pos 16 /**< (PIO_DRIVER) Drive of PIO Line 16 Position */ 6930 #define PIO_DRIVER_LINE16_Msk (_U_(0x1) << PIO_DRIVER_LINE16_Pos) /**< (PIO_DRIVER) Drive of PIO Line 16 Mask */ 6931 #define PIO_DRIVER_LINE16 PIO_DRIVER_LINE16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE16_Msk instead */ 6932 #define PIO_DRIVER_LINE16_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6933 #define PIO_DRIVER_LINE16_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6934 #define PIO_DRIVER_LINE16_LOW_DRIVE (PIO_DRIVER_LINE16_LOW_DRIVE_Val << PIO_DRIVER_LINE16_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6935 #define PIO_DRIVER_LINE16_HIGH_DRIVE (PIO_DRIVER_LINE16_HIGH_DRIVE_Val << PIO_DRIVER_LINE16_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6936 #define PIO_DRIVER_LINE17_Pos 17 /**< (PIO_DRIVER) Drive of PIO Line 17 Position */ 6937 #define PIO_DRIVER_LINE17_Msk (_U_(0x1) << PIO_DRIVER_LINE17_Pos) /**< (PIO_DRIVER) Drive of PIO Line 17 Mask */ 6938 #define PIO_DRIVER_LINE17 PIO_DRIVER_LINE17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE17_Msk instead */ 6939 #define PIO_DRIVER_LINE17_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6940 #define PIO_DRIVER_LINE17_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6941 #define PIO_DRIVER_LINE17_LOW_DRIVE (PIO_DRIVER_LINE17_LOW_DRIVE_Val << PIO_DRIVER_LINE17_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6942 #define PIO_DRIVER_LINE17_HIGH_DRIVE (PIO_DRIVER_LINE17_HIGH_DRIVE_Val << PIO_DRIVER_LINE17_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6943 #define PIO_DRIVER_LINE18_Pos 18 /**< (PIO_DRIVER) Drive of PIO Line 18 Position */ 6944 #define PIO_DRIVER_LINE18_Msk (_U_(0x1) << PIO_DRIVER_LINE18_Pos) /**< (PIO_DRIVER) Drive of PIO Line 18 Mask */ 6945 #define PIO_DRIVER_LINE18 PIO_DRIVER_LINE18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE18_Msk instead */ 6946 #define PIO_DRIVER_LINE18_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6947 #define PIO_DRIVER_LINE18_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6948 #define PIO_DRIVER_LINE18_LOW_DRIVE (PIO_DRIVER_LINE18_LOW_DRIVE_Val << PIO_DRIVER_LINE18_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6949 #define PIO_DRIVER_LINE18_HIGH_DRIVE (PIO_DRIVER_LINE18_HIGH_DRIVE_Val << PIO_DRIVER_LINE18_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6950 #define PIO_DRIVER_LINE19_Pos 19 /**< (PIO_DRIVER) Drive of PIO Line 19 Position */ 6951 #define PIO_DRIVER_LINE19_Msk (_U_(0x1) << PIO_DRIVER_LINE19_Pos) /**< (PIO_DRIVER) Drive of PIO Line 19 Mask */ 6952 #define PIO_DRIVER_LINE19 PIO_DRIVER_LINE19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE19_Msk instead */ 6953 #define PIO_DRIVER_LINE19_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6954 #define PIO_DRIVER_LINE19_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6955 #define PIO_DRIVER_LINE19_LOW_DRIVE (PIO_DRIVER_LINE19_LOW_DRIVE_Val << PIO_DRIVER_LINE19_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6956 #define PIO_DRIVER_LINE19_HIGH_DRIVE (PIO_DRIVER_LINE19_HIGH_DRIVE_Val << PIO_DRIVER_LINE19_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6957 #define PIO_DRIVER_LINE20_Pos 20 /**< (PIO_DRIVER) Drive of PIO Line 20 Position */ 6958 #define PIO_DRIVER_LINE20_Msk (_U_(0x1) << PIO_DRIVER_LINE20_Pos) /**< (PIO_DRIVER) Drive of PIO Line 20 Mask */ 6959 #define PIO_DRIVER_LINE20 PIO_DRIVER_LINE20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE20_Msk instead */ 6960 #define PIO_DRIVER_LINE20_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6961 #define PIO_DRIVER_LINE20_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6962 #define PIO_DRIVER_LINE20_LOW_DRIVE (PIO_DRIVER_LINE20_LOW_DRIVE_Val << PIO_DRIVER_LINE20_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6963 #define PIO_DRIVER_LINE20_HIGH_DRIVE (PIO_DRIVER_LINE20_HIGH_DRIVE_Val << PIO_DRIVER_LINE20_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6964 #define PIO_DRIVER_LINE21_Pos 21 /**< (PIO_DRIVER) Drive of PIO Line 21 Position */ 6965 #define PIO_DRIVER_LINE21_Msk (_U_(0x1) << PIO_DRIVER_LINE21_Pos) /**< (PIO_DRIVER) Drive of PIO Line 21 Mask */ 6966 #define PIO_DRIVER_LINE21 PIO_DRIVER_LINE21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE21_Msk instead */ 6967 #define PIO_DRIVER_LINE21_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6968 #define PIO_DRIVER_LINE21_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6969 #define PIO_DRIVER_LINE21_LOW_DRIVE (PIO_DRIVER_LINE21_LOW_DRIVE_Val << PIO_DRIVER_LINE21_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6970 #define PIO_DRIVER_LINE21_HIGH_DRIVE (PIO_DRIVER_LINE21_HIGH_DRIVE_Val << PIO_DRIVER_LINE21_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6971 #define PIO_DRIVER_LINE22_Pos 22 /**< (PIO_DRIVER) Drive of PIO Line 22 Position */ 6972 #define PIO_DRIVER_LINE22_Msk (_U_(0x1) << PIO_DRIVER_LINE22_Pos) /**< (PIO_DRIVER) Drive of PIO Line 22 Mask */ 6973 #define PIO_DRIVER_LINE22 PIO_DRIVER_LINE22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE22_Msk instead */ 6974 #define PIO_DRIVER_LINE22_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6975 #define PIO_DRIVER_LINE22_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6976 #define PIO_DRIVER_LINE22_LOW_DRIVE (PIO_DRIVER_LINE22_LOW_DRIVE_Val << PIO_DRIVER_LINE22_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6977 #define PIO_DRIVER_LINE22_HIGH_DRIVE (PIO_DRIVER_LINE22_HIGH_DRIVE_Val << PIO_DRIVER_LINE22_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6978 #define PIO_DRIVER_LINE23_Pos 23 /**< (PIO_DRIVER) Drive of PIO Line 23 Position */ 6979 #define PIO_DRIVER_LINE23_Msk (_U_(0x1) << PIO_DRIVER_LINE23_Pos) /**< (PIO_DRIVER) Drive of PIO Line 23 Mask */ 6980 #define PIO_DRIVER_LINE23 PIO_DRIVER_LINE23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE23_Msk instead */ 6981 #define PIO_DRIVER_LINE23_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6982 #define PIO_DRIVER_LINE23_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6983 #define PIO_DRIVER_LINE23_LOW_DRIVE (PIO_DRIVER_LINE23_LOW_DRIVE_Val << PIO_DRIVER_LINE23_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6984 #define PIO_DRIVER_LINE23_HIGH_DRIVE (PIO_DRIVER_LINE23_HIGH_DRIVE_Val << PIO_DRIVER_LINE23_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6985 #define PIO_DRIVER_LINE24_Pos 24 /**< (PIO_DRIVER) Drive of PIO Line 24 Position */ 6986 #define PIO_DRIVER_LINE24_Msk (_U_(0x1) << PIO_DRIVER_LINE24_Pos) /**< (PIO_DRIVER) Drive of PIO Line 24 Mask */ 6987 #define PIO_DRIVER_LINE24 PIO_DRIVER_LINE24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE24_Msk instead */ 6988 #define PIO_DRIVER_LINE24_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6989 #define PIO_DRIVER_LINE24_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6990 #define PIO_DRIVER_LINE24_LOW_DRIVE (PIO_DRIVER_LINE24_LOW_DRIVE_Val << PIO_DRIVER_LINE24_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6991 #define PIO_DRIVER_LINE24_HIGH_DRIVE (PIO_DRIVER_LINE24_HIGH_DRIVE_Val << PIO_DRIVER_LINE24_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6992 #define PIO_DRIVER_LINE25_Pos 25 /**< (PIO_DRIVER) Drive of PIO Line 25 Position */ 6993 #define PIO_DRIVER_LINE25_Msk (_U_(0x1) << PIO_DRIVER_LINE25_Pos) /**< (PIO_DRIVER) Drive of PIO Line 25 Mask */ 6994 #define PIO_DRIVER_LINE25 PIO_DRIVER_LINE25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE25_Msk instead */ 6995 #define PIO_DRIVER_LINE25_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 6996 #define PIO_DRIVER_LINE25_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 6997 #define PIO_DRIVER_LINE25_LOW_DRIVE (PIO_DRIVER_LINE25_LOW_DRIVE_Val << PIO_DRIVER_LINE25_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 6998 #define PIO_DRIVER_LINE25_HIGH_DRIVE (PIO_DRIVER_LINE25_HIGH_DRIVE_Val << PIO_DRIVER_LINE25_Pos) /**< (PIO_DRIVER) Highest drive Position */ 6999 #define PIO_DRIVER_LINE26_Pos 26 /**< (PIO_DRIVER) Drive of PIO Line 26 Position */ 7000 #define PIO_DRIVER_LINE26_Msk (_U_(0x1) << PIO_DRIVER_LINE26_Pos) /**< (PIO_DRIVER) Drive of PIO Line 26 Mask */ 7001 #define PIO_DRIVER_LINE26 PIO_DRIVER_LINE26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE26_Msk instead */ 7002 #define PIO_DRIVER_LINE26_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 7003 #define PIO_DRIVER_LINE26_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 7004 #define PIO_DRIVER_LINE26_LOW_DRIVE (PIO_DRIVER_LINE26_LOW_DRIVE_Val << PIO_DRIVER_LINE26_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 7005 #define PIO_DRIVER_LINE26_HIGH_DRIVE (PIO_DRIVER_LINE26_HIGH_DRIVE_Val << PIO_DRIVER_LINE26_Pos) /**< (PIO_DRIVER) Highest drive Position */ 7006 #define PIO_DRIVER_LINE27_Pos 27 /**< (PIO_DRIVER) Drive of PIO Line 27 Position */ 7007 #define PIO_DRIVER_LINE27_Msk (_U_(0x1) << PIO_DRIVER_LINE27_Pos) /**< (PIO_DRIVER) Drive of PIO Line 27 Mask */ 7008 #define PIO_DRIVER_LINE27 PIO_DRIVER_LINE27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE27_Msk instead */ 7009 #define PIO_DRIVER_LINE27_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 7010 #define PIO_DRIVER_LINE27_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 7011 #define PIO_DRIVER_LINE27_LOW_DRIVE (PIO_DRIVER_LINE27_LOW_DRIVE_Val << PIO_DRIVER_LINE27_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 7012 #define PIO_DRIVER_LINE27_HIGH_DRIVE (PIO_DRIVER_LINE27_HIGH_DRIVE_Val << PIO_DRIVER_LINE27_Pos) /**< (PIO_DRIVER) Highest drive Position */ 7013 #define PIO_DRIVER_LINE28_Pos 28 /**< (PIO_DRIVER) Drive of PIO Line 28 Position */ 7014 #define PIO_DRIVER_LINE28_Msk (_U_(0x1) << PIO_DRIVER_LINE28_Pos) /**< (PIO_DRIVER) Drive of PIO Line 28 Mask */ 7015 #define PIO_DRIVER_LINE28 PIO_DRIVER_LINE28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE28_Msk instead */ 7016 #define PIO_DRIVER_LINE28_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 7017 #define PIO_DRIVER_LINE28_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 7018 #define PIO_DRIVER_LINE28_LOW_DRIVE (PIO_DRIVER_LINE28_LOW_DRIVE_Val << PIO_DRIVER_LINE28_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 7019 #define PIO_DRIVER_LINE28_HIGH_DRIVE (PIO_DRIVER_LINE28_HIGH_DRIVE_Val << PIO_DRIVER_LINE28_Pos) /**< (PIO_DRIVER) Highest drive Position */ 7020 #define PIO_DRIVER_LINE29_Pos 29 /**< (PIO_DRIVER) Drive of PIO Line 29 Position */ 7021 #define PIO_DRIVER_LINE29_Msk (_U_(0x1) << PIO_DRIVER_LINE29_Pos) /**< (PIO_DRIVER) Drive of PIO Line 29 Mask */ 7022 #define PIO_DRIVER_LINE29 PIO_DRIVER_LINE29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE29_Msk instead */ 7023 #define PIO_DRIVER_LINE29_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 7024 #define PIO_DRIVER_LINE29_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 7025 #define PIO_DRIVER_LINE29_LOW_DRIVE (PIO_DRIVER_LINE29_LOW_DRIVE_Val << PIO_DRIVER_LINE29_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 7026 #define PIO_DRIVER_LINE29_HIGH_DRIVE (PIO_DRIVER_LINE29_HIGH_DRIVE_Val << PIO_DRIVER_LINE29_Pos) /**< (PIO_DRIVER) Highest drive Position */ 7027 #define PIO_DRIVER_LINE30_Pos 30 /**< (PIO_DRIVER) Drive of PIO Line 30 Position */ 7028 #define PIO_DRIVER_LINE30_Msk (_U_(0x1) << PIO_DRIVER_LINE30_Pos) /**< (PIO_DRIVER) Drive of PIO Line 30 Mask */ 7029 #define PIO_DRIVER_LINE30 PIO_DRIVER_LINE30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE30_Msk instead */ 7030 #define PIO_DRIVER_LINE30_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 7031 #define PIO_DRIVER_LINE30_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 7032 #define PIO_DRIVER_LINE30_LOW_DRIVE (PIO_DRIVER_LINE30_LOW_DRIVE_Val << PIO_DRIVER_LINE30_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 7033 #define PIO_DRIVER_LINE30_HIGH_DRIVE (PIO_DRIVER_LINE30_HIGH_DRIVE_Val << PIO_DRIVER_LINE30_Pos) /**< (PIO_DRIVER) Highest drive Position */ 7034 #define PIO_DRIVER_LINE31_Pos 31 /**< (PIO_DRIVER) Drive of PIO Line 31 Position */ 7035 #define PIO_DRIVER_LINE31_Msk (_U_(0x1) << PIO_DRIVER_LINE31_Pos) /**< (PIO_DRIVER) Drive of PIO Line 31 Mask */ 7036 #define PIO_DRIVER_LINE31 PIO_DRIVER_LINE31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE31_Msk instead */ 7037 #define PIO_DRIVER_LINE31_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ 7038 #define PIO_DRIVER_LINE31_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ 7039 #define PIO_DRIVER_LINE31_LOW_DRIVE (PIO_DRIVER_LINE31_LOW_DRIVE_Val << PIO_DRIVER_LINE31_Pos) /**< (PIO_DRIVER) Lowest drive Position */ 7040 #define PIO_DRIVER_LINE31_HIGH_DRIVE (PIO_DRIVER_LINE31_HIGH_DRIVE_Val << PIO_DRIVER_LINE31_Pos) /**< (PIO_DRIVER) Highest drive Position */ 7041 #define PIO_DRIVER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_DRIVER) Register MASK (Use PIO_DRIVER_Msk instead) */ 7042 #define PIO_DRIVER_Msk _U_(0xFFFFFFFF) /**< (PIO_DRIVER) Register Mask */ 7043 7044 #define PIO_DRIVER_LINE_Pos 0 /**< (PIO_DRIVER Position) Drive of PIO Line 3x */ 7045 #define PIO_DRIVER_LINE_Msk (_U_(0xFFFFFFFF) << PIO_DRIVER_LINE_Pos) /**< (PIO_DRIVER Mask) LINE */ 7046 #define PIO_DRIVER_LINE(value) (PIO_DRIVER_LINE_Msk & ((value) << PIO_DRIVER_LINE_Pos)) 7047 7048 /* -------- PIO_PCMR : (PIO Offset: 0x150) (R/W 32) Parallel Capture Mode Register -------- */ 7049 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 7050 #if COMPONENT_TYPEDEF_STYLE == 'N' 7051 typedef union { 7052 struct { 7053 uint32_t PCEN:1; /**< bit: 0 Parallel Capture Mode Enable */ 7054 uint32_t :3; /**< bit: 1..3 Reserved */ 7055 uint32_t DSIZE:2; /**< bit: 4..5 Parallel Capture Mode Data Size */ 7056 uint32_t :3; /**< bit: 6..8 Reserved */ 7057 uint32_t ALWYS:1; /**< bit: 9 Parallel Capture Mode Always Sampling */ 7058 uint32_t HALFS:1; /**< bit: 10 Parallel Capture Mode Half Sampling */ 7059 uint32_t FRSTS:1; /**< bit: 11 Parallel Capture Mode First Sample */ 7060 uint32_t :20; /**< bit: 12..31 Reserved */ 7061 } bit; /**< Structure used for bit access */ 7062 uint32_t reg; /**< Type used for register access */ 7063 } PIO_PCMR_Type; 7064 #endif 7065 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 7066 7067 #define PIO_PCMR_OFFSET (0x150) /**< (PIO_PCMR) Parallel Capture Mode Register Offset */ 7068 7069 #define PIO_PCMR_PCEN_Pos 0 /**< (PIO_PCMR) Parallel Capture Mode Enable Position */ 7070 #define PIO_PCMR_PCEN_Msk (_U_(0x1) << PIO_PCMR_PCEN_Pos) /**< (PIO_PCMR) Parallel Capture Mode Enable Mask */ 7071 #define PIO_PCMR_PCEN PIO_PCMR_PCEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCMR_PCEN_Msk instead */ 7072 #define PIO_PCMR_DSIZE_Pos 4 /**< (PIO_PCMR) Parallel Capture Mode Data Size Position */ 7073 #define PIO_PCMR_DSIZE_Msk (_U_(0x3) << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) Parallel Capture Mode Data Size Mask */ 7074 #define PIO_PCMR_DSIZE(value) (PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos)) 7075 #define PIO_PCMR_DSIZE_BYTE_Val _U_(0x0) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ 7076 #define PIO_PCMR_DSIZE_HALFWORD_Val _U_(0x1) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ 7077 #define PIO_PCMR_DSIZE_WORD_Val _U_(0x2) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ 7078 #define PIO_PCMR_DSIZE_BYTE (PIO_PCMR_DSIZE_BYTE_Val << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) Position */ 7079 #define PIO_PCMR_DSIZE_HALFWORD (PIO_PCMR_DSIZE_HALFWORD_Val << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) Position */ 7080 #define PIO_PCMR_DSIZE_WORD (PIO_PCMR_DSIZE_WORD_Val << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) Position */ 7081 #define PIO_PCMR_ALWYS_Pos 9 /**< (PIO_PCMR) Parallel Capture Mode Always Sampling Position */ 7082 #define PIO_PCMR_ALWYS_Msk (_U_(0x1) << PIO_PCMR_ALWYS_Pos) /**< (PIO_PCMR) Parallel Capture Mode Always Sampling Mask */ 7083 #define PIO_PCMR_ALWYS PIO_PCMR_ALWYS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCMR_ALWYS_Msk instead */ 7084 #define PIO_PCMR_HALFS_Pos 10 /**< (PIO_PCMR) Parallel Capture Mode Half Sampling Position */ 7085 #define PIO_PCMR_HALFS_Msk (_U_(0x1) << PIO_PCMR_HALFS_Pos) /**< (PIO_PCMR) Parallel Capture Mode Half Sampling Mask */ 7086 #define PIO_PCMR_HALFS PIO_PCMR_HALFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCMR_HALFS_Msk instead */ 7087 #define PIO_PCMR_FRSTS_Pos 11 /**< (PIO_PCMR) Parallel Capture Mode First Sample Position */ 7088 #define PIO_PCMR_FRSTS_Msk (_U_(0x1) << PIO_PCMR_FRSTS_Pos) /**< (PIO_PCMR) Parallel Capture Mode First Sample Mask */ 7089 #define PIO_PCMR_FRSTS PIO_PCMR_FRSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCMR_FRSTS_Msk instead */ 7090 #define PIO_PCMR_MASK _U_(0xE31) /**< \deprecated (PIO_PCMR) Register MASK (Use PIO_PCMR_Msk instead) */ 7091 #define PIO_PCMR_Msk _U_(0xE31) /**< (PIO_PCMR) Register Mask */ 7092 7093 7094 /* -------- PIO_PCIER : (PIO Offset: 0x154) (/W 32) Parallel Capture Interrupt Enable Register -------- */ 7095 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 7096 #if COMPONENT_TYPEDEF_STYLE == 'N' 7097 typedef union { 7098 struct { 7099 uint32_t DRDY:1; /**< bit: 0 Parallel Capture Mode Data Ready Interrupt Enable */ 7100 uint32_t OVRE:1; /**< bit: 1 Parallel Capture Mode Overrun Error Interrupt Enable */ 7101 uint32_t ENDRX:1; /**< bit: 2 End of Reception Transfer Interrupt Enable */ 7102 uint32_t RXBUFF:1; /**< bit: 3 Reception Buffer Full Interrupt Enable */ 7103 uint32_t :28; /**< bit: 4..31 Reserved */ 7104 } bit; /**< Structure used for bit access */ 7105 uint32_t reg; /**< Type used for register access */ 7106 } PIO_PCIER_Type; 7107 #endif 7108 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 7109 7110 #define PIO_PCIER_OFFSET (0x154) /**< (PIO_PCIER) Parallel Capture Interrupt Enable Register Offset */ 7111 7112 #define PIO_PCIER_DRDY_Pos 0 /**< (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable Position */ 7113 #define PIO_PCIER_DRDY_Msk (_U_(0x1) << PIO_PCIER_DRDY_Pos) /**< (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable Mask */ 7114 #define PIO_PCIER_DRDY PIO_PCIER_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIER_DRDY_Msk instead */ 7115 #define PIO_PCIER_OVRE_Pos 1 /**< (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable Position */ 7116 #define PIO_PCIER_OVRE_Msk (_U_(0x1) << PIO_PCIER_OVRE_Pos) /**< (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable Mask */ 7117 #define PIO_PCIER_OVRE PIO_PCIER_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIER_OVRE_Msk instead */ 7118 #define PIO_PCIER_ENDRX_Pos 2 /**< (PIO_PCIER) End of Reception Transfer Interrupt Enable Position */ 7119 #define PIO_PCIER_ENDRX_Msk (_U_(0x1) << PIO_PCIER_ENDRX_Pos) /**< (PIO_PCIER) End of Reception Transfer Interrupt Enable Mask */ 7120 #define PIO_PCIER_ENDRX PIO_PCIER_ENDRX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIER_ENDRX_Msk instead */ 7121 #define PIO_PCIER_RXBUFF_Pos 3 /**< (PIO_PCIER) Reception Buffer Full Interrupt Enable Position */ 7122 #define PIO_PCIER_RXBUFF_Msk (_U_(0x1) << PIO_PCIER_RXBUFF_Pos) /**< (PIO_PCIER) Reception Buffer Full Interrupt Enable Mask */ 7123 #define PIO_PCIER_RXBUFF PIO_PCIER_RXBUFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIER_RXBUFF_Msk instead */ 7124 #define PIO_PCIER_MASK _U_(0x0F) /**< \deprecated (PIO_PCIER) Register MASK (Use PIO_PCIER_Msk instead) */ 7125 #define PIO_PCIER_Msk _U_(0x0F) /**< (PIO_PCIER) Register Mask */ 7126 7127 7128 /* -------- PIO_PCIDR : (PIO Offset: 0x158) (/W 32) Parallel Capture Interrupt Disable Register -------- */ 7129 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 7130 #if COMPONENT_TYPEDEF_STYLE == 'N' 7131 typedef union { 7132 struct { 7133 uint32_t DRDY:1; /**< bit: 0 Parallel Capture Mode Data Ready Interrupt Disable */ 7134 uint32_t OVRE:1; /**< bit: 1 Parallel Capture Mode Overrun Error Interrupt Disable */ 7135 uint32_t ENDRX:1; /**< bit: 2 End of Reception Transfer Interrupt Disable */ 7136 uint32_t RXBUFF:1; /**< bit: 3 Reception Buffer Full Interrupt Disable */ 7137 uint32_t :28; /**< bit: 4..31 Reserved */ 7138 } bit; /**< Structure used for bit access */ 7139 uint32_t reg; /**< Type used for register access */ 7140 } PIO_PCIDR_Type; 7141 #endif 7142 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 7143 7144 #define PIO_PCIDR_OFFSET (0x158) /**< (PIO_PCIDR) Parallel Capture Interrupt Disable Register Offset */ 7145 7146 #define PIO_PCIDR_DRDY_Pos 0 /**< (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable Position */ 7147 #define PIO_PCIDR_DRDY_Msk (_U_(0x1) << PIO_PCIDR_DRDY_Pos) /**< (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable Mask */ 7148 #define PIO_PCIDR_DRDY PIO_PCIDR_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIDR_DRDY_Msk instead */ 7149 #define PIO_PCIDR_OVRE_Pos 1 /**< (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable Position */ 7150 #define PIO_PCIDR_OVRE_Msk (_U_(0x1) << PIO_PCIDR_OVRE_Pos) /**< (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable Mask */ 7151 #define PIO_PCIDR_OVRE PIO_PCIDR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIDR_OVRE_Msk instead */ 7152 #define PIO_PCIDR_ENDRX_Pos 2 /**< (PIO_PCIDR) End of Reception Transfer Interrupt Disable Position */ 7153 #define PIO_PCIDR_ENDRX_Msk (_U_(0x1) << PIO_PCIDR_ENDRX_Pos) /**< (PIO_PCIDR) End of Reception Transfer Interrupt Disable Mask */ 7154 #define PIO_PCIDR_ENDRX PIO_PCIDR_ENDRX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIDR_ENDRX_Msk instead */ 7155 #define PIO_PCIDR_RXBUFF_Pos 3 /**< (PIO_PCIDR) Reception Buffer Full Interrupt Disable Position */ 7156 #define PIO_PCIDR_RXBUFF_Msk (_U_(0x1) << PIO_PCIDR_RXBUFF_Pos) /**< (PIO_PCIDR) Reception Buffer Full Interrupt Disable Mask */ 7157 #define PIO_PCIDR_RXBUFF PIO_PCIDR_RXBUFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIDR_RXBUFF_Msk instead */ 7158 #define PIO_PCIDR_MASK _U_(0x0F) /**< \deprecated (PIO_PCIDR) Register MASK (Use PIO_PCIDR_Msk instead) */ 7159 #define PIO_PCIDR_Msk _U_(0x0F) /**< (PIO_PCIDR) Register Mask */ 7160 7161 7162 /* -------- PIO_PCIMR : (PIO Offset: 0x15c) (R/ 32) Parallel Capture Interrupt Mask Register -------- */ 7163 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 7164 #if COMPONENT_TYPEDEF_STYLE == 'N' 7165 typedef union { 7166 struct { 7167 uint32_t DRDY:1; /**< bit: 0 Parallel Capture Mode Data Ready Interrupt Mask */ 7168 uint32_t OVRE:1; /**< bit: 1 Parallel Capture Mode Overrun Error Interrupt Mask */ 7169 uint32_t ENDRX:1; /**< bit: 2 End of Reception Transfer Interrupt Mask */ 7170 uint32_t RXBUFF:1; /**< bit: 3 Reception Buffer Full Interrupt Mask */ 7171 uint32_t :28; /**< bit: 4..31 Reserved */ 7172 } bit; /**< Structure used for bit access */ 7173 uint32_t reg; /**< Type used for register access */ 7174 } PIO_PCIMR_Type; 7175 #endif 7176 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 7177 7178 #define PIO_PCIMR_OFFSET (0x15C) /**< (PIO_PCIMR) Parallel Capture Interrupt Mask Register Offset */ 7179 7180 #define PIO_PCIMR_DRDY_Pos 0 /**< (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask Position */ 7181 #define PIO_PCIMR_DRDY_Msk (_U_(0x1) << PIO_PCIMR_DRDY_Pos) /**< (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask Mask */ 7182 #define PIO_PCIMR_DRDY PIO_PCIMR_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIMR_DRDY_Msk instead */ 7183 #define PIO_PCIMR_OVRE_Pos 1 /**< (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask Position */ 7184 #define PIO_PCIMR_OVRE_Msk (_U_(0x1) << PIO_PCIMR_OVRE_Pos) /**< (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask Mask */ 7185 #define PIO_PCIMR_OVRE PIO_PCIMR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIMR_OVRE_Msk instead */ 7186 #define PIO_PCIMR_ENDRX_Pos 2 /**< (PIO_PCIMR) End of Reception Transfer Interrupt Mask Position */ 7187 #define PIO_PCIMR_ENDRX_Msk (_U_(0x1) << PIO_PCIMR_ENDRX_Pos) /**< (PIO_PCIMR) End of Reception Transfer Interrupt Mask Mask */ 7188 #define PIO_PCIMR_ENDRX PIO_PCIMR_ENDRX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIMR_ENDRX_Msk instead */ 7189 #define PIO_PCIMR_RXBUFF_Pos 3 /**< (PIO_PCIMR) Reception Buffer Full Interrupt Mask Position */ 7190 #define PIO_PCIMR_RXBUFF_Msk (_U_(0x1) << PIO_PCIMR_RXBUFF_Pos) /**< (PIO_PCIMR) Reception Buffer Full Interrupt Mask Mask */ 7191 #define PIO_PCIMR_RXBUFF PIO_PCIMR_RXBUFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIMR_RXBUFF_Msk instead */ 7192 #define PIO_PCIMR_MASK _U_(0x0F) /**< \deprecated (PIO_PCIMR) Register MASK (Use PIO_PCIMR_Msk instead) */ 7193 #define PIO_PCIMR_Msk _U_(0x0F) /**< (PIO_PCIMR) Register Mask */ 7194 7195 7196 /* -------- PIO_PCISR : (PIO Offset: 0x160) (R/ 32) Parallel Capture Interrupt Status Register -------- */ 7197 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 7198 #if COMPONENT_TYPEDEF_STYLE == 'N' 7199 typedef union { 7200 struct { 7201 uint32_t DRDY:1; /**< bit: 0 Parallel Capture Mode Data Ready */ 7202 uint32_t OVRE:1; /**< bit: 1 Parallel Capture Mode Overrun Error */ 7203 uint32_t :30; /**< bit: 2..31 Reserved */ 7204 } bit; /**< Structure used for bit access */ 7205 uint32_t reg; /**< Type used for register access */ 7206 } PIO_PCISR_Type; 7207 #endif 7208 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 7209 7210 #define PIO_PCISR_OFFSET (0x160) /**< (PIO_PCISR) Parallel Capture Interrupt Status Register Offset */ 7211 7212 #define PIO_PCISR_DRDY_Pos 0 /**< (PIO_PCISR) Parallel Capture Mode Data Ready Position */ 7213 #define PIO_PCISR_DRDY_Msk (_U_(0x1) << PIO_PCISR_DRDY_Pos) /**< (PIO_PCISR) Parallel Capture Mode Data Ready Mask */ 7214 #define PIO_PCISR_DRDY PIO_PCISR_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCISR_DRDY_Msk instead */ 7215 #define PIO_PCISR_OVRE_Pos 1 /**< (PIO_PCISR) Parallel Capture Mode Overrun Error Position */ 7216 #define PIO_PCISR_OVRE_Msk (_U_(0x1) << PIO_PCISR_OVRE_Pos) /**< (PIO_PCISR) Parallel Capture Mode Overrun Error Mask */ 7217 #define PIO_PCISR_OVRE PIO_PCISR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCISR_OVRE_Msk instead */ 7218 #define PIO_PCISR_MASK _U_(0x03) /**< \deprecated (PIO_PCISR) Register MASK (Use PIO_PCISR_Msk instead) */ 7219 #define PIO_PCISR_Msk _U_(0x03) /**< (PIO_PCISR) Register Mask */ 7220 7221 7222 /* -------- PIO_PCRHR : (PIO Offset: 0x164) (R/ 32) Parallel Capture Reception Holding Register -------- */ 7223 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 7224 #if COMPONENT_TYPEDEF_STYLE == 'N' 7225 typedef union { 7226 struct { 7227 uint32_t RDATA:32; /**< bit: 0..31 Parallel Capture Mode Reception Data */ 7228 } bit; /**< Structure used for bit access */ 7229 uint32_t reg; /**< Type used for register access */ 7230 } PIO_PCRHR_Type; 7231 #endif 7232 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 7233 7234 #define PIO_PCRHR_OFFSET (0x164) /**< (PIO_PCRHR) Parallel Capture Reception Holding Register Offset */ 7235 7236 #define PIO_PCRHR_RDATA_Pos 0 /**< (PIO_PCRHR) Parallel Capture Mode Reception Data Position */ 7237 #define PIO_PCRHR_RDATA_Msk (_U_(0xFFFFFFFF) << PIO_PCRHR_RDATA_Pos) /**< (PIO_PCRHR) Parallel Capture Mode Reception Data Mask */ 7238 #define PIO_PCRHR_RDATA(value) (PIO_PCRHR_RDATA_Msk & ((value) << PIO_PCRHR_RDATA_Pos)) 7239 #define PIO_PCRHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PCRHR) Register MASK (Use PIO_PCRHR_Msk instead) */ 7240 #define PIO_PCRHR_Msk _U_(0xFFFFFFFF) /**< (PIO_PCRHR) Register Mask */ 7241 7242 7243 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 7244 #if COMPONENT_TYPEDEF_STYLE == 'R' 7245 /** \brief PIO hardware registers */ 7246 typedef struct { 7247 __O uint32_t PIO_PER; /**< (PIO Offset: 0x00) PIO Enable Register */ 7248 __O uint32_t PIO_PDR; /**< (PIO Offset: 0x04) PIO Disable Register */ 7249 __I uint32_t PIO_PSR; /**< (PIO Offset: 0x08) PIO Status Register */ 7250 __I uint8_t Reserved1[4]; 7251 __O uint32_t PIO_OER; /**< (PIO Offset: 0x10) Output Enable Register */ 7252 __O uint32_t PIO_ODR; /**< (PIO Offset: 0x14) Output Disable Register */ 7253 __I uint32_t PIO_OSR; /**< (PIO Offset: 0x18) Output Status Register */ 7254 __I uint8_t Reserved2[4]; 7255 __O uint32_t PIO_IFER; /**< (PIO Offset: 0x20) Glitch Input Filter Enable Register */ 7256 __O uint32_t PIO_IFDR; /**< (PIO Offset: 0x24) Glitch Input Filter Disable Register */ 7257 __I uint32_t PIO_IFSR; /**< (PIO Offset: 0x28) Glitch Input Filter Status Register */ 7258 __I uint8_t Reserved3[4]; 7259 __O uint32_t PIO_SODR; /**< (PIO Offset: 0x30) Set Output Data Register */ 7260 __O uint32_t PIO_CODR; /**< (PIO Offset: 0x34) Clear Output Data Register */ 7261 __IO uint32_t PIO_ODSR; /**< (PIO Offset: 0x38) Output Data Status Register */ 7262 __I uint32_t PIO_PDSR; /**< (PIO Offset: 0x3C) Pin Data Status Register */ 7263 __O uint32_t PIO_IER; /**< (PIO Offset: 0x40) Interrupt Enable Register */ 7264 __O uint32_t PIO_IDR; /**< (PIO Offset: 0x44) Interrupt Disable Register */ 7265 __I uint32_t PIO_IMR; /**< (PIO Offset: 0x48) Interrupt Mask Register */ 7266 __I uint32_t PIO_ISR; /**< (PIO Offset: 0x4C) Interrupt Status Register */ 7267 __O uint32_t PIO_MDER; /**< (PIO Offset: 0x50) Multi-driver Enable Register */ 7268 __O uint32_t PIO_MDDR; /**< (PIO Offset: 0x54) Multi-driver Disable Register */ 7269 __I uint32_t PIO_MDSR; /**< (PIO Offset: 0x58) Multi-driver Status Register */ 7270 __I uint8_t Reserved4[4]; 7271 __O uint32_t PIO_PUDR; /**< (PIO Offset: 0x60) Pull-up Disable Register */ 7272 __O uint32_t PIO_PUER; /**< (PIO Offset: 0x64) Pull-up Enable Register */ 7273 __I uint32_t PIO_PUSR; /**< (PIO Offset: 0x68) Pad Pull-up Status Register */ 7274 __I uint8_t Reserved5[4]; 7275 __IO uint32_t PIO_ABCDSR[2]; /**< (PIO Offset: 0x70) Peripheral ABCD Select Register 0 */ 7276 __I uint8_t Reserved6[8]; 7277 __O uint32_t PIO_IFSCDR; /**< (PIO Offset: 0x80) Input Filter Slow Clock Disable Register */ 7278 __O uint32_t PIO_IFSCER; /**< (PIO Offset: 0x84) Input Filter Slow Clock Enable Register */ 7279 __I uint32_t PIO_IFSCSR; /**< (PIO Offset: 0x88) Input Filter Slow Clock Status Register */ 7280 __IO uint32_t PIO_SCDR; /**< (PIO Offset: 0x8C) Slow Clock Divider Debouncing Register */ 7281 __O uint32_t PIO_PPDDR; /**< (PIO Offset: 0x90) Pad Pull-down Disable Register */ 7282 __O uint32_t PIO_PPDER; /**< (PIO Offset: 0x94) Pad Pull-down Enable Register */ 7283 __I uint32_t PIO_PPDSR; /**< (PIO Offset: 0x98) Pad Pull-down Status Register */ 7284 __I uint8_t Reserved7[4]; 7285 __O uint32_t PIO_OWER; /**< (PIO Offset: 0xA0) Output Write Enable */ 7286 __O uint32_t PIO_OWDR; /**< (PIO Offset: 0xA4) Output Write Disable */ 7287 __I uint32_t PIO_OWSR; /**< (PIO Offset: 0xA8) Output Write Status Register */ 7288 __I uint8_t Reserved8[4]; 7289 __O uint32_t PIO_AIMER; /**< (PIO Offset: 0xB0) Additional Interrupt Modes Enable Register */ 7290 __O uint32_t PIO_AIMDR; /**< (PIO Offset: 0xB4) Additional Interrupt Modes Disable Register */ 7291 __I uint32_t PIO_AIMMR; /**< (PIO Offset: 0xB8) Additional Interrupt Modes Mask Register */ 7292 __I uint8_t Reserved9[4]; 7293 __O uint32_t PIO_ESR; /**< (PIO Offset: 0xC0) Edge Select Register */ 7294 __O uint32_t PIO_LSR; /**< (PIO Offset: 0xC4) Level Select Register */ 7295 __I uint32_t PIO_ELSR; /**< (PIO Offset: 0xC8) Edge/Level Status Register */ 7296 __I uint8_t Reserved10[4]; 7297 __O uint32_t PIO_FELLSR; /**< (PIO Offset: 0xD0) Falling Edge/Low-Level Select Register */ 7298 __O uint32_t PIO_REHLSR; /**< (PIO Offset: 0xD4) Rising Edge/High-Level Select Register */ 7299 __I uint32_t PIO_FRLHSR; /**< (PIO Offset: 0xD8) Fall/Rise - Low/High Status Register */ 7300 __I uint8_t Reserved11[4]; 7301 __I uint32_t PIO_LOCKSR; /**< (PIO Offset: 0xE0) Lock Status */ 7302 __IO uint32_t PIO_WPMR; /**< (PIO Offset: 0xE4) Write Protection Mode Register */ 7303 __I uint32_t PIO_WPSR; /**< (PIO Offset: 0xE8) Write Protection Status Register */ 7304 __I uint8_t Reserved12[20]; 7305 __IO uint32_t PIO_SCHMITT; /**< (PIO Offset: 0x100) Schmitt Trigger Register */ 7306 __I uint8_t Reserved13[20]; 7307 __IO uint32_t PIO_DRIVER; /**< (PIO Offset: 0x118) I/O Drive Register */ 7308 __I uint8_t Reserved14[52]; 7309 __IO uint32_t PIO_PCMR; /**< (PIO Offset: 0x150) Parallel Capture Mode Register */ 7310 __O uint32_t PIO_PCIER; /**< (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register */ 7311 __O uint32_t PIO_PCIDR; /**< (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register */ 7312 __I uint32_t PIO_PCIMR; /**< (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register */ 7313 __I uint32_t PIO_PCISR; /**< (PIO Offset: 0x160) Parallel Capture Interrupt Status Register */ 7314 __I uint32_t PIO_PCRHR; /**< (PIO Offset: 0x164) Parallel Capture Reception Holding Register */ 7315 } Pio; 7316 7317 #elif COMPONENT_TYPEDEF_STYLE == 'N' 7318 /** \brief PIO hardware registers */ 7319 typedef struct { 7320 __O PIO_PER_Type PIO_PER; /**< Offset: 0x00 ( /W 32) PIO Enable Register */ 7321 __O PIO_PDR_Type PIO_PDR; /**< Offset: 0x04 ( /W 32) PIO Disable Register */ 7322 __I PIO_PSR_Type PIO_PSR; /**< Offset: 0x08 (R/ 32) PIO Status Register */ 7323 __I uint8_t Reserved1[4]; 7324 __O PIO_OER_Type PIO_OER; /**< Offset: 0x10 ( /W 32) Output Enable Register */ 7325 __O PIO_ODR_Type PIO_ODR; /**< Offset: 0x14 ( /W 32) Output Disable Register */ 7326 __I PIO_OSR_Type PIO_OSR; /**< Offset: 0x18 (R/ 32) Output Status Register */ 7327 __I uint8_t Reserved2[4]; 7328 __O PIO_IFER_Type PIO_IFER; /**< Offset: 0x20 ( /W 32) Glitch Input Filter Enable Register */ 7329 __O PIO_IFDR_Type PIO_IFDR; /**< Offset: 0x24 ( /W 32) Glitch Input Filter Disable Register */ 7330 __I PIO_IFSR_Type PIO_IFSR; /**< Offset: 0x28 (R/ 32) Glitch Input Filter Status Register */ 7331 __I uint8_t Reserved3[4]; 7332 __O PIO_SODR_Type PIO_SODR; /**< Offset: 0x30 ( /W 32) Set Output Data Register */ 7333 __O PIO_CODR_Type PIO_CODR; /**< Offset: 0x34 ( /W 32) Clear Output Data Register */ 7334 __IO PIO_ODSR_Type PIO_ODSR; /**< Offset: 0x38 (R/W 32) Output Data Status Register */ 7335 __I PIO_PDSR_Type PIO_PDSR; /**< Offset: 0x3C (R/ 32) Pin Data Status Register */ 7336 __O PIO_IER_Type PIO_IER; /**< Offset: 0x40 ( /W 32) Interrupt Enable Register */ 7337 __O PIO_IDR_Type PIO_IDR; /**< Offset: 0x44 ( /W 32) Interrupt Disable Register */ 7338 __I PIO_IMR_Type PIO_IMR; /**< Offset: 0x48 (R/ 32) Interrupt Mask Register */ 7339 __I PIO_ISR_Type PIO_ISR; /**< Offset: 0x4C (R/ 32) Interrupt Status Register */ 7340 __O PIO_MDER_Type PIO_MDER; /**< Offset: 0x50 ( /W 32) Multi-driver Enable Register */ 7341 __O PIO_MDDR_Type PIO_MDDR; /**< Offset: 0x54 ( /W 32) Multi-driver Disable Register */ 7342 __I PIO_MDSR_Type PIO_MDSR; /**< Offset: 0x58 (R/ 32) Multi-driver Status Register */ 7343 __I uint8_t Reserved4[4]; 7344 __O PIO_PUDR_Type PIO_PUDR; /**< Offset: 0x60 ( /W 32) Pull-up Disable Register */ 7345 __O PIO_PUER_Type PIO_PUER; /**< Offset: 0x64 ( /W 32) Pull-up Enable Register */ 7346 __I PIO_PUSR_Type PIO_PUSR; /**< Offset: 0x68 (R/ 32) Pad Pull-up Status Register */ 7347 __I uint8_t Reserved5[4]; 7348 __IO PIO_ABCDSR_Type PIO_ABCDSR[2]; /**< Offset: 0x70 (R/W 32) Peripheral ABCD Select Register 0 */ 7349 __I uint8_t Reserved6[8]; 7350 __O PIO_IFSCDR_Type PIO_IFSCDR; /**< Offset: 0x80 ( /W 32) Input Filter Slow Clock Disable Register */ 7351 __O PIO_IFSCER_Type PIO_IFSCER; /**< Offset: 0x84 ( /W 32) Input Filter Slow Clock Enable Register */ 7352 __I PIO_IFSCSR_Type PIO_IFSCSR; /**< Offset: 0x88 (R/ 32) Input Filter Slow Clock Status Register */ 7353 __IO PIO_SCDR_Type PIO_SCDR; /**< Offset: 0x8C (R/W 32) Slow Clock Divider Debouncing Register */ 7354 __O PIO_PPDDR_Type PIO_PPDDR; /**< Offset: 0x90 ( /W 32) Pad Pull-down Disable Register */ 7355 __O PIO_PPDER_Type PIO_PPDER; /**< Offset: 0x94 ( /W 32) Pad Pull-down Enable Register */ 7356 __I PIO_PPDSR_Type PIO_PPDSR; /**< Offset: 0x98 (R/ 32) Pad Pull-down Status Register */ 7357 __I uint8_t Reserved7[4]; 7358 __O PIO_OWER_Type PIO_OWER; /**< Offset: 0xA0 ( /W 32) Output Write Enable */ 7359 __O PIO_OWDR_Type PIO_OWDR; /**< Offset: 0xA4 ( /W 32) Output Write Disable */ 7360 __I PIO_OWSR_Type PIO_OWSR; /**< Offset: 0xA8 (R/ 32) Output Write Status Register */ 7361 __I uint8_t Reserved8[4]; 7362 __O PIO_AIMER_Type PIO_AIMER; /**< Offset: 0xB0 ( /W 32) Additional Interrupt Modes Enable Register */ 7363 __O PIO_AIMDR_Type PIO_AIMDR; /**< Offset: 0xB4 ( /W 32) Additional Interrupt Modes Disable Register */ 7364 __I PIO_AIMMR_Type PIO_AIMMR; /**< Offset: 0xB8 (R/ 32) Additional Interrupt Modes Mask Register */ 7365 __I uint8_t Reserved9[4]; 7366 __O PIO_ESR_Type PIO_ESR; /**< Offset: 0xC0 ( /W 32) Edge Select Register */ 7367 __O PIO_LSR_Type PIO_LSR; /**< Offset: 0xC4 ( /W 32) Level Select Register */ 7368 __I PIO_ELSR_Type PIO_ELSR; /**< Offset: 0xC8 (R/ 32) Edge/Level Status Register */ 7369 __I uint8_t Reserved10[4]; 7370 __O PIO_FELLSR_Type PIO_FELLSR; /**< Offset: 0xD0 ( /W 32) Falling Edge/Low-Level Select Register */ 7371 __O PIO_REHLSR_Type PIO_REHLSR; /**< Offset: 0xD4 ( /W 32) Rising Edge/High-Level Select Register */ 7372 __I PIO_FRLHSR_Type PIO_FRLHSR; /**< Offset: 0xD8 (R/ 32) Fall/Rise - Low/High Status Register */ 7373 __I uint8_t Reserved11[4]; 7374 __I PIO_LOCKSR_Type PIO_LOCKSR; /**< Offset: 0xE0 (R/ 32) Lock Status */ 7375 __IO PIO_WPMR_Type PIO_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 7376 __I PIO_WPSR_Type PIO_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ 7377 __I uint8_t Reserved12[20]; 7378 __IO PIO_SCHMITT_Type PIO_SCHMITT; /**< Offset: 0x100 (R/W 32) Schmitt Trigger Register */ 7379 __I uint8_t Reserved13[20]; 7380 __IO PIO_DRIVER_Type PIO_DRIVER; /**< Offset: 0x118 (R/W 32) I/O Drive Register */ 7381 __I uint8_t Reserved14[52]; 7382 __IO PIO_PCMR_Type PIO_PCMR; /**< Offset: 0x150 (R/W 32) Parallel Capture Mode Register */ 7383 __O PIO_PCIER_Type PIO_PCIER; /**< Offset: 0x154 ( /W 32) Parallel Capture Interrupt Enable Register */ 7384 __O PIO_PCIDR_Type PIO_PCIDR; /**< Offset: 0x158 ( /W 32) Parallel Capture Interrupt Disable Register */ 7385 __I PIO_PCIMR_Type PIO_PCIMR; /**< Offset: 0x15C (R/ 32) Parallel Capture Interrupt Mask Register */ 7386 __I PIO_PCISR_Type PIO_PCISR; /**< Offset: 0x160 (R/ 32) Parallel Capture Interrupt Status Register */ 7387 __I PIO_PCRHR_Type PIO_PCRHR; /**< Offset: 0x164 (R/ 32) Parallel Capture Reception Holding Register */ 7388 } Pio; 7389 7390 #else /* COMPONENT_TYPEDEF_STYLE */ 7391 #error Unknown component typedef style 7392 #endif /* COMPONENT_TYPEDEF_STYLE */ 7393 7394 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 7395 /** @} end of Parallel Input/Output Controller */ 7396 7397 #endif /* _SAMV71_PIO_COMPONENT_H_ */ 7398
