Lines Matching full:additional
5053 /* -------- PIO_AIMER : (PIO Offset: 0xb0) (/W 32) Additional Interrupt Modes Enable Register -----…
5058 … uint32_t P0:1; /**< bit: 0 Additional Interrupt Modes Enable */
5059 … uint32_t P1:1; /**< bit: 1 Additional Interrupt Modes Enable */
5060 … uint32_t P2:1; /**< bit: 2 Additional Interrupt Modes Enable */
5061 … uint32_t P3:1; /**< bit: 3 Additional Interrupt Modes Enable */
5062 … uint32_t P4:1; /**< bit: 4 Additional Interrupt Modes Enable */
5063 … uint32_t P5:1; /**< bit: 5 Additional Interrupt Modes Enable */
5064 … uint32_t P6:1; /**< bit: 6 Additional Interrupt Modes Enable */
5065 … uint32_t P7:1; /**< bit: 7 Additional Interrupt Modes Enable */
5066 … uint32_t P8:1; /**< bit: 8 Additional Interrupt Modes Enable */
5067 … uint32_t P9:1; /**< bit: 9 Additional Interrupt Modes Enable */
5068 … uint32_t P10:1; /**< bit: 10 Additional Interrupt Modes Enable */
5069 … uint32_t P11:1; /**< bit: 11 Additional Interrupt Modes Enable */
5070 … uint32_t P12:1; /**< bit: 12 Additional Interrupt Modes Enable */
5071 … uint32_t P13:1; /**< bit: 13 Additional Interrupt Modes Enable */
5072 … uint32_t P14:1; /**< bit: 14 Additional Interrupt Modes Enable */
5073 … uint32_t P15:1; /**< bit: 15 Additional Interrupt Modes Enable */
5074 … uint32_t P16:1; /**< bit: 16 Additional Interrupt Modes Enable */
5075 … uint32_t P17:1; /**< bit: 17 Additional Interrupt Modes Enable */
5076 … uint32_t P18:1; /**< bit: 18 Additional Interrupt Modes Enable */
5077 … uint32_t P19:1; /**< bit: 19 Additional Interrupt Modes Enable */
5078 … uint32_t P20:1; /**< bit: 20 Additional Interrupt Modes Enable */
5079 … uint32_t P21:1; /**< bit: 21 Additional Interrupt Modes Enable */
5080 … uint32_t P22:1; /**< bit: 22 Additional Interrupt Modes Enable */
5081 … uint32_t P23:1; /**< bit: 23 Additional Interrupt Modes Enable */
5082 … uint32_t P24:1; /**< bit: 24 Additional Interrupt Modes Enable */
5083 … uint32_t P25:1; /**< bit: 25 Additional Interrupt Modes Enable */
5084 … uint32_t P26:1; /**< bit: 26 Additional Interrupt Modes Enable */
5085 … uint32_t P27:1; /**< bit: 27 Additional Interrupt Modes Enable */
5086 … uint32_t P28:1; /**< bit: 28 Additional Interrupt Modes Enable */
5087 … uint32_t P29:1; /**< bit: 29 Additional Interrupt Modes Enable */
5088 … uint32_t P30:1; /**< bit: 30 Additional Interrupt Modes Enable */
5089 … uint32_t P31:1; /**< bit: 31 Additional Interrupt Modes Enable */
5092 … uint32_t P:32; /**< bit: 0..31 Additional Interrupt Modes Enable */
5099 … (0xB0) /**< (PIO_AIMER) Additional Interrupt Modes …
5101 … 0 /**< (PIO_AIMER) Additional Interrupt Modes …
5102 … (_U_(0x1) << PIO_AIMER_P0_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5104 … 1 /**< (PIO_AIMER) Additional Interrupt Modes …
5105 … (_U_(0x1) << PIO_AIMER_P1_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5107 … 2 /**< (PIO_AIMER) Additional Interrupt Modes …
5108 … (_U_(0x1) << PIO_AIMER_P2_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5110 … 3 /**< (PIO_AIMER) Additional Interrupt Modes …
5111 … (_U_(0x1) << PIO_AIMER_P3_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5113 … 4 /**< (PIO_AIMER) Additional Interrupt Modes …
5114 … (_U_(0x1) << PIO_AIMER_P4_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5116 … 5 /**< (PIO_AIMER) Additional Interrupt Modes …
5117 … (_U_(0x1) << PIO_AIMER_P5_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5119 … 6 /**< (PIO_AIMER) Additional Interrupt Modes …
5120 … (_U_(0x1) << PIO_AIMER_P6_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5122 … 7 /**< (PIO_AIMER) Additional Interrupt Modes …
5123 … (_U_(0x1) << PIO_AIMER_P7_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5125 … 8 /**< (PIO_AIMER) Additional Interrupt Modes …
5126 … (_U_(0x1) << PIO_AIMER_P8_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5128 … 9 /**< (PIO_AIMER) Additional Interrupt Modes …
5129 … (_U_(0x1) << PIO_AIMER_P9_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5131 … 10 /**< (PIO_AIMER) Additional Interrupt Modes …
5132 … (_U_(0x1) << PIO_AIMER_P10_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5134 … 11 /**< (PIO_AIMER) Additional Interrupt Modes …
5135 … (_U_(0x1) << PIO_AIMER_P11_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5137 … 12 /**< (PIO_AIMER) Additional Interrupt Modes …
5138 … (_U_(0x1) << PIO_AIMER_P12_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5140 … 13 /**< (PIO_AIMER) Additional Interrupt Modes …
5141 … (_U_(0x1) << PIO_AIMER_P13_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5143 … 14 /**< (PIO_AIMER) Additional Interrupt Modes …
5144 … (_U_(0x1) << PIO_AIMER_P14_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5146 … 15 /**< (PIO_AIMER) Additional Interrupt Modes …
5147 … (_U_(0x1) << PIO_AIMER_P15_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5149 … 16 /**< (PIO_AIMER) Additional Interrupt Modes …
5150 … (_U_(0x1) << PIO_AIMER_P16_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5152 … 17 /**< (PIO_AIMER) Additional Interrupt Modes …
5153 … (_U_(0x1) << PIO_AIMER_P17_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5155 … 18 /**< (PIO_AIMER) Additional Interrupt Modes …
5156 … (_U_(0x1) << PIO_AIMER_P18_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5158 … 19 /**< (PIO_AIMER) Additional Interrupt Modes …
5159 … (_U_(0x1) << PIO_AIMER_P19_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5161 … 20 /**< (PIO_AIMER) Additional Interrupt Modes …
5162 … (_U_(0x1) << PIO_AIMER_P20_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5164 … 21 /**< (PIO_AIMER) Additional Interrupt Modes …
5165 … (_U_(0x1) << PIO_AIMER_P21_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5167 … 22 /**< (PIO_AIMER) Additional Interrupt Modes …
5168 … (_U_(0x1) << PIO_AIMER_P22_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5170 … 23 /**< (PIO_AIMER) Additional Interrupt Modes …
5171 … (_U_(0x1) << PIO_AIMER_P23_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5173 … 24 /**< (PIO_AIMER) Additional Interrupt Modes …
5174 … (_U_(0x1) << PIO_AIMER_P24_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5176 … 25 /**< (PIO_AIMER) Additional Interrupt Modes …
5177 … (_U_(0x1) << PIO_AIMER_P25_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5179 … 26 /**< (PIO_AIMER) Additional Interrupt Modes …
5180 … (_U_(0x1) << PIO_AIMER_P26_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5182 … 27 /**< (PIO_AIMER) Additional Interrupt Modes …
5183 … (_U_(0x1) << PIO_AIMER_P27_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5185 … 28 /**< (PIO_AIMER) Additional Interrupt Modes …
5186 … (_U_(0x1) << PIO_AIMER_P28_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5188 … 29 /**< (PIO_AIMER) Additional Interrupt Modes …
5189 … (_U_(0x1) << PIO_AIMER_P29_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5191 … 30 /**< (PIO_AIMER) Additional Interrupt Modes …
5192 … (_U_(0x1) << PIO_AIMER_P30_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5194 … 31 /**< (PIO_AIMER) Additional Interrupt Modes …
5195 … (_U_(0x1) << PIO_AIMER_P31_Pos) /**< (PIO_AIMER) Additional Interrupt Modes …
5200 … /**< (PIO_AIMER Position) Additional Interrupt Modes …
5204 /* -------- PIO_AIMDR : (PIO Offset: 0xb4) (/W 32) Additional Interrupt Modes Disable Register ----…
5209 … uint32_t P0:1; /**< bit: 0 Additional Interrupt Modes Disable */
5210 … uint32_t P1:1; /**< bit: 1 Additional Interrupt Modes Disable */
5211 … uint32_t P2:1; /**< bit: 2 Additional Interrupt Modes Disable */
5212 … uint32_t P3:1; /**< bit: 3 Additional Interrupt Modes Disable */
5213 … uint32_t P4:1; /**< bit: 4 Additional Interrupt Modes Disable */
5214 … uint32_t P5:1; /**< bit: 5 Additional Interrupt Modes Disable */
5215 … uint32_t P6:1; /**< bit: 6 Additional Interrupt Modes Disable */
5216 … uint32_t P7:1; /**< bit: 7 Additional Interrupt Modes Disable */
5217 … uint32_t P8:1; /**< bit: 8 Additional Interrupt Modes Disable */
5218 … uint32_t P9:1; /**< bit: 9 Additional Interrupt Modes Disable */
5219 … uint32_t P10:1; /**< bit: 10 Additional Interrupt Modes Disable */
5220 … uint32_t P11:1; /**< bit: 11 Additional Interrupt Modes Disable */
5221 … uint32_t P12:1; /**< bit: 12 Additional Interrupt Modes Disable */
5222 … uint32_t P13:1; /**< bit: 13 Additional Interrupt Modes Disable */
5223 … uint32_t P14:1; /**< bit: 14 Additional Interrupt Modes Disable */
5224 … uint32_t P15:1; /**< bit: 15 Additional Interrupt Modes Disable */
5225 … uint32_t P16:1; /**< bit: 16 Additional Interrupt Modes Disable */
5226 … uint32_t P17:1; /**< bit: 17 Additional Interrupt Modes Disable */
5227 … uint32_t P18:1; /**< bit: 18 Additional Interrupt Modes Disable */
5228 … uint32_t P19:1; /**< bit: 19 Additional Interrupt Modes Disable */
5229 … uint32_t P20:1; /**< bit: 20 Additional Interrupt Modes Disable */
5230 … uint32_t P21:1; /**< bit: 21 Additional Interrupt Modes Disable */
5231 … uint32_t P22:1; /**< bit: 22 Additional Interrupt Modes Disable */
5232 … uint32_t P23:1; /**< bit: 23 Additional Interrupt Modes Disable */
5233 … uint32_t P24:1; /**< bit: 24 Additional Interrupt Modes Disable */
5234 … uint32_t P25:1; /**< bit: 25 Additional Interrupt Modes Disable */
5235 … uint32_t P26:1; /**< bit: 26 Additional Interrupt Modes Disable */
5236 … uint32_t P27:1; /**< bit: 27 Additional Interrupt Modes Disable */
5237 … uint32_t P28:1; /**< bit: 28 Additional Interrupt Modes Disable */
5238 … uint32_t P29:1; /**< bit: 29 Additional Interrupt Modes Disable */
5239 … uint32_t P30:1; /**< bit: 30 Additional Interrupt Modes Disable */
5240 … uint32_t P31:1; /**< bit: 31 Additional Interrupt Modes Disable */
5243 … uint32_t P:32; /**< bit: 0..31 Additional Interrupt Modes Disable */
5250 … (0xB4) /**< (PIO_AIMDR) Additional Interrupt Modes …
5252 … 0 /**< (PIO_AIMDR) Additional Interrupt Modes …
5253 … (_U_(0x1) << PIO_AIMDR_P0_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5255 … 1 /**< (PIO_AIMDR) Additional Interrupt Modes …
5256 … (_U_(0x1) << PIO_AIMDR_P1_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5258 … 2 /**< (PIO_AIMDR) Additional Interrupt Modes …
5259 … (_U_(0x1) << PIO_AIMDR_P2_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5261 … 3 /**< (PIO_AIMDR) Additional Interrupt Modes …
5262 … (_U_(0x1) << PIO_AIMDR_P3_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5264 … 4 /**< (PIO_AIMDR) Additional Interrupt Modes …
5265 … (_U_(0x1) << PIO_AIMDR_P4_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5267 … 5 /**< (PIO_AIMDR) Additional Interrupt Modes …
5268 … (_U_(0x1) << PIO_AIMDR_P5_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5270 … 6 /**< (PIO_AIMDR) Additional Interrupt Modes …
5271 … (_U_(0x1) << PIO_AIMDR_P6_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5273 … 7 /**< (PIO_AIMDR) Additional Interrupt Modes …
5274 … (_U_(0x1) << PIO_AIMDR_P7_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5276 … 8 /**< (PIO_AIMDR) Additional Interrupt Modes …
5277 … (_U_(0x1) << PIO_AIMDR_P8_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5279 … 9 /**< (PIO_AIMDR) Additional Interrupt Modes …
5280 … (_U_(0x1) << PIO_AIMDR_P9_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5282 … 10 /**< (PIO_AIMDR) Additional Interrupt Modes …
5283 … (_U_(0x1) << PIO_AIMDR_P10_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5285 … 11 /**< (PIO_AIMDR) Additional Interrupt Modes …
5286 … (_U_(0x1) << PIO_AIMDR_P11_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5288 … 12 /**< (PIO_AIMDR) Additional Interrupt Modes …
5289 … (_U_(0x1) << PIO_AIMDR_P12_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5291 … 13 /**< (PIO_AIMDR) Additional Interrupt Modes …
5292 … (_U_(0x1) << PIO_AIMDR_P13_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5294 … 14 /**< (PIO_AIMDR) Additional Interrupt Modes …
5295 … (_U_(0x1) << PIO_AIMDR_P14_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5297 … 15 /**< (PIO_AIMDR) Additional Interrupt Modes …
5298 … (_U_(0x1) << PIO_AIMDR_P15_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5300 … 16 /**< (PIO_AIMDR) Additional Interrupt Modes …
5301 … (_U_(0x1) << PIO_AIMDR_P16_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5303 … 17 /**< (PIO_AIMDR) Additional Interrupt Modes …
5304 … (_U_(0x1) << PIO_AIMDR_P17_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5306 … 18 /**< (PIO_AIMDR) Additional Interrupt Modes …
5307 … (_U_(0x1) << PIO_AIMDR_P18_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5309 … 19 /**< (PIO_AIMDR) Additional Interrupt Modes …
5310 … (_U_(0x1) << PIO_AIMDR_P19_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5312 … 20 /**< (PIO_AIMDR) Additional Interrupt Modes …
5313 … (_U_(0x1) << PIO_AIMDR_P20_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5315 … 21 /**< (PIO_AIMDR) Additional Interrupt Modes …
5316 … (_U_(0x1) << PIO_AIMDR_P21_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5318 … 22 /**< (PIO_AIMDR) Additional Interrupt Modes …
5319 … (_U_(0x1) << PIO_AIMDR_P22_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5321 … 23 /**< (PIO_AIMDR) Additional Interrupt Modes …
5322 … (_U_(0x1) << PIO_AIMDR_P23_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5324 … 24 /**< (PIO_AIMDR) Additional Interrupt Modes …
5325 … (_U_(0x1) << PIO_AIMDR_P24_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5327 … 25 /**< (PIO_AIMDR) Additional Interrupt Modes …
5328 … (_U_(0x1) << PIO_AIMDR_P25_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5330 … 26 /**< (PIO_AIMDR) Additional Interrupt Modes …
5331 … (_U_(0x1) << PIO_AIMDR_P26_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5333 … 27 /**< (PIO_AIMDR) Additional Interrupt Modes …
5334 … (_U_(0x1) << PIO_AIMDR_P27_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5336 … 28 /**< (PIO_AIMDR) Additional Interrupt Modes …
5337 … (_U_(0x1) << PIO_AIMDR_P28_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5339 … 29 /**< (PIO_AIMDR) Additional Interrupt Modes …
5340 … (_U_(0x1) << PIO_AIMDR_P29_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5342 … 30 /**< (PIO_AIMDR) Additional Interrupt Modes …
5343 … (_U_(0x1) << PIO_AIMDR_P30_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5345 … 31 /**< (PIO_AIMDR) Additional Interrupt Modes …
5346 … (_U_(0x1) << PIO_AIMDR_P31_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes …
5351 … /**< (PIO_AIMDR Position) Additional Interrupt Modes …
5355 /* -------- PIO_AIMMR : (PIO Offset: 0xb8) (R/ 32) Additional Interrupt Modes Mask Register -------…
5401 … (0xB8) /**< (PIO_AIMMR) Additional Interrupt Modes …
7289 …__O uint32_t PIO_AIMER; /**< (PIO Offset: 0xB0) Additional Interrupt Modes Enable Register */
7290 …__O uint32_t PIO_AIMDR; /**< (PIO Offset: 0xB4) Additional Interrupt Modes Disable Register …
7291 __I uint32_t PIO_AIMMR; /**< (PIO Offset: 0xB8) Additional Interrupt Modes Mask Register */
7362 …__O PIO_AIMER_Type PIO_AIMER; /**< Offset: 0xB0 ( /W 32) Additional Interru…
7363 …__O PIO_AIMDR_Type PIO_AIMDR; /**< Offset: 0xB4 ( /W 32) Additional Interru…
7364 …__I PIO_AIMMR_Type PIO_AIMMR; /**< Offset: 0xB8 (R/ 32) Additional Interru…