1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4E_PWM_INSTANCE_ 31 #define _SAM4E_PWM_INSTANCE_ 32 33 /* ========== Register definition for PWM peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_PWM_CLK (0x40000000U) /**< \brief (PWM) PWM Clock Register */ 36 #define REG_PWM_ENA (0x40000004U) /**< \brief (PWM) PWM Enable Register */ 37 #define REG_PWM_DIS (0x40000008U) /**< \brief (PWM) PWM Disable Register */ 38 #define REG_PWM_SR (0x4000000CU) /**< \brief (PWM) PWM Status Register */ 39 #define REG_PWM_IER1 (0x40000010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ 40 #define REG_PWM_IDR1 (0x40000014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ 41 #define REG_PWM_IMR1 (0x40000018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ 42 #define REG_PWM_ISR1 (0x4000001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ 43 #define REG_PWM_SCM (0x40000020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ 44 #define REG_PWM_SCUC (0x40000028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ 45 #define REG_PWM_SCUP (0x4000002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ 46 #define REG_PWM_SCUPUPD (0x40000030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ 47 #define REG_PWM_IER2 (0x40000034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ 48 #define REG_PWM_IDR2 (0x40000038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ 49 #define REG_PWM_IMR2 (0x4000003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ 50 #define REG_PWM_ISR2 (0x40000040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ 51 #define REG_PWM_OOV (0x40000044U) /**< \brief (PWM) PWM Output Override Value Register */ 52 #define REG_PWM_OS (0x40000048U) /**< \brief (PWM) PWM Output Selection Register */ 53 #define REG_PWM_OSS (0x4000004CU) /**< \brief (PWM) PWM Output Selection Set Register */ 54 #define REG_PWM_OSC (0x40000050U) /**< \brief (PWM) PWM Output Selection Clear Register */ 55 #define REG_PWM_OSSUPD (0x40000054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ 56 #define REG_PWM_OSCUPD (0x40000058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ 57 #define REG_PWM_FMR (0x4000005CU) /**< \brief (PWM) PWM Fault Mode Register */ 58 #define REG_PWM_FSR (0x40000060U) /**< \brief (PWM) PWM Fault Status Register */ 59 #define REG_PWM_FCR (0x40000064U) /**< \brief (PWM) PWM Fault Clear Register */ 60 #define REG_PWM_FPV1 (0x40000068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */ 61 #define REG_PWM_FPE (0x4000006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ 62 #define REG_PWM_ELMR (0x4000007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ 63 #define REG_PWM_SSPR (0x400000A0U) /**< \brief (PWM) PWM Spread Spectrum Register */ 64 #define REG_PWM_SSPUP (0x400000A4U) /**< \brief (PWM) PWM Spread Spectrum Update Register */ 65 #define REG_PWM_SMMR (0x400000B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ 66 #define REG_PWM_FPV2 (0x400000C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */ 67 #define REG_PWM_WPCR (0x400000E4U) /**< \brief (PWM) PWM Write Protect Control Register */ 68 #define REG_PWM_WPSR (0x400000E8U) /**< \brief (PWM) PWM Write Protect Status Register */ 69 #define REG_PWM_TPR (0x40000108U) /**< \brief (PWM) Transmit Pointer Register */ 70 #define REG_PWM_TCR (0x4000010CU) /**< \brief (PWM) Transmit Counter Register */ 71 #define REG_PWM_TNPR (0x40000118U) /**< \brief (PWM) Transmit Next Pointer Register */ 72 #define REG_PWM_TNCR (0x4000011CU) /**< \brief (PWM) Transmit Next Counter Register */ 73 #define REG_PWM_PTCR (0x40000120U) /**< \brief (PWM) Transfer Control Register */ 74 #define REG_PWM_PTSR (0x40000124U) /**< \brief (PWM) Transfer Status Register */ 75 #define REG_PWM_CMPV0 (0x40000130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ 76 #define REG_PWM_CMPVUPD0 (0x40000134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ 77 #define REG_PWM_CMPM0 (0x40000138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ 78 #define REG_PWM_CMPMUPD0 (0x4000013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ 79 #define REG_PWM_CMPV1 (0x40000140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ 80 #define REG_PWM_CMPVUPD1 (0x40000144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ 81 #define REG_PWM_CMPM1 (0x40000148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ 82 #define REG_PWM_CMPMUPD1 (0x4000014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ 83 #define REG_PWM_CMPV2 (0x40000150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ 84 #define REG_PWM_CMPVUPD2 (0x40000154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ 85 #define REG_PWM_CMPM2 (0x40000158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ 86 #define REG_PWM_CMPMUPD2 (0x4000015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ 87 #define REG_PWM_CMPV3 (0x40000160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ 88 #define REG_PWM_CMPVUPD3 (0x40000164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ 89 #define REG_PWM_CMPM3 (0x40000168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ 90 #define REG_PWM_CMPMUPD3 (0x4000016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ 91 #define REG_PWM_CMPV4 (0x40000170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ 92 #define REG_PWM_CMPVUPD4 (0x40000174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ 93 #define REG_PWM_CMPM4 (0x40000178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ 94 #define REG_PWM_CMPMUPD4 (0x4000017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ 95 #define REG_PWM_CMPV5 (0x40000180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ 96 #define REG_PWM_CMPVUPD5 (0x40000184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ 97 #define REG_PWM_CMPM5 (0x40000188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ 98 #define REG_PWM_CMPMUPD5 (0x4000018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ 99 #define REG_PWM_CMPV6 (0x40000190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ 100 #define REG_PWM_CMPVUPD6 (0x40000194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ 101 #define REG_PWM_CMPM6 (0x40000198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ 102 #define REG_PWM_CMPMUPD6 (0x4000019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ 103 #define REG_PWM_CMPV7 (0x400001A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ 104 #define REG_PWM_CMPVUPD7 (0x400001A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ 105 #define REG_PWM_CMPM7 (0x400001A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ 106 #define REG_PWM_CMPMUPD7 (0x400001ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ 107 #define REG_PWM_CMR0 (0x40000200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ 108 #define REG_PWM_CDTY0 (0x40000204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ 109 #define REG_PWM_CDTYUPD0 (0x40000208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ 110 #define REG_PWM_CPRD0 (0x4000020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ 111 #define REG_PWM_CPRDUPD0 (0x40000210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ 112 #define REG_PWM_CCNT0 (0x40000214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ 113 #define REG_PWM_DT0 (0x40000218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ 114 #define REG_PWM_DTUPD0 (0x4000021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ 115 #define REG_PWM_CMR1 (0x40000220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ 116 #define REG_PWM_CDTY1 (0x40000224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ 117 #define REG_PWM_CDTYUPD1 (0x40000228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ 118 #define REG_PWM_CPRD1 (0x4000022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ 119 #define REG_PWM_CPRDUPD1 (0x40000230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ 120 #define REG_PWM_CCNT1 (0x40000234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ 121 #define REG_PWM_DT1 (0x40000238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ 122 #define REG_PWM_DTUPD1 (0x4000023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ 123 #define REG_PWM_CMR2 (0x40000240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ 124 #define REG_PWM_CDTY2 (0x40000244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ 125 #define REG_PWM_CDTYUPD2 (0x40000248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ 126 #define REG_PWM_CPRD2 (0x4000024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ 127 #define REG_PWM_CPRDUPD2 (0x40000250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ 128 #define REG_PWM_CCNT2 (0x40000254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ 129 #define REG_PWM_DT2 (0x40000258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ 130 #define REG_PWM_DTUPD2 (0x4000025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ 131 #define REG_PWM_CMR3 (0x40000260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ 132 #define REG_PWM_CDTY3 (0x40000264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ 133 #define REG_PWM_CDTYUPD3 (0x40000268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ 134 #define REG_PWM_CPRD3 (0x4000026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ 135 #define REG_PWM_CPRDUPD3 (0x40000270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ 136 #define REG_PWM_CCNT3 (0x40000274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ 137 #define REG_PWM_DT3 (0x40000278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ 138 #define REG_PWM_DTUPD3 (0x4000027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ 139 #define REG_PWM_CMUPD0 (0x40000400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */ 140 #define REG_PWM_CAE0 (0x40000404U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 0) */ 141 #define REG_PWM_CAEUPD0 (0x40000408U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 0) */ 142 #define REG_PWM_CMUPD1 (0x40000420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */ 143 #define REG_PWM_CAE1 (0x40000424U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 1) */ 144 #define REG_PWM_CAEUPD1 (0x40000428U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 1) */ 145 #define REG_PWM_CMUPD2 (0x40000440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */ 146 #define REG_PWM_CAE2 (0x40000444U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 2) */ 147 #define REG_PWM_CAEUPD2 (0x40000448U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 2) */ 148 #define REG_PWM_CMUPD3 (0x40000460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */ 149 #define REG_PWM_CAE3 (0x40000464U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 3) */ 150 #define REG_PWM_CAEUPD3 (0x40000468U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 3) */ 151 #else 152 #define REG_PWM_CLK (*(RwReg*)0x40000000U) /**< \brief (PWM) PWM Clock Register */ 153 #define REG_PWM_ENA (*(WoReg*)0x40000004U) /**< \brief (PWM) PWM Enable Register */ 154 #define REG_PWM_DIS (*(WoReg*)0x40000008U) /**< \brief (PWM) PWM Disable Register */ 155 #define REG_PWM_SR (*(RoReg*)0x4000000CU) /**< \brief (PWM) PWM Status Register */ 156 #define REG_PWM_IER1 (*(WoReg*)0x40000010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ 157 #define REG_PWM_IDR1 (*(WoReg*)0x40000014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ 158 #define REG_PWM_IMR1 (*(RoReg*)0x40000018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ 159 #define REG_PWM_ISR1 (*(RoReg*)0x4000001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ 160 #define REG_PWM_SCM (*(RwReg*)0x40000020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ 161 #define REG_PWM_SCUC (*(RwReg*)0x40000028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ 162 #define REG_PWM_SCUP (*(RwReg*)0x4000002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ 163 #define REG_PWM_SCUPUPD (*(WoReg*)0x40000030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ 164 #define REG_PWM_IER2 (*(WoReg*)0x40000034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ 165 #define REG_PWM_IDR2 (*(WoReg*)0x40000038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ 166 #define REG_PWM_IMR2 (*(RoReg*)0x4000003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ 167 #define REG_PWM_ISR2 (*(RoReg*)0x40000040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ 168 #define REG_PWM_OOV (*(RwReg*)0x40000044U) /**< \brief (PWM) PWM Output Override Value Register */ 169 #define REG_PWM_OS (*(RwReg*)0x40000048U) /**< \brief (PWM) PWM Output Selection Register */ 170 #define REG_PWM_OSS (*(WoReg*)0x4000004CU) /**< \brief (PWM) PWM Output Selection Set Register */ 171 #define REG_PWM_OSC (*(WoReg*)0x40000050U) /**< \brief (PWM) PWM Output Selection Clear Register */ 172 #define REG_PWM_OSSUPD (*(WoReg*)0x40000054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ 173 #define REG_PWM_OSCUPD (*(WoReg*)0x40000058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ 174 #define REG_PWM_FMR (*(RwReg*)0x4000005CU) /**< \brief (PWM) PWM Fault Mode Register */ 175 #define REG_PWM_FSR (*(RoReg*)0x40000060U) /**< \brief (PWM) PWM Fault Status Register */ 176 #define REG_PWM_FCR (*(WoReg*)0x40000064U) /**< \brief (PWM) PWM Fault Clear Register */ 177 #define REG_PWM_FPV1 (*(RwReg*)0x40000068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */ 178 #define REG_PWM_FPE (*(RwReg*)0x4000006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ 179 #define REG_PWM_ELMR (*(RwReg*)0x4000007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ 180 #define REG_PWM_SSPR (*(RwReg*)0x400000A0U) /**< \brief (PWM) PWM Spread Spectrum Register */ 181 #define REG_PWM_SSPUP (*(WoReg*)0x400000A4U) /**< \brief (PWM) PWM Spread Spectrum Update Register */ 182 #define REG_PWM_SMMR (*(RwReg*)0x400000B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ 183 #define REG_PWM_FPV2 (*(RwReg*)0x400000C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */ 184 #define REG_PWM_WPCR (*(WoReg*)0x400000E4U) /**< \brief (PWM) PWM Write Protect Control Register */ 185 #define REG_PWM_WPSR (*(RoReg*)0x400000E8U) /**< \brief (PWM) PWM Write Protect Status Register */ 186 #define REG_PWM_TPR (*(RwReg*)0x40000108U) /**< \brief (PWM) Transmit Pointer Register */ 187 #define REG_PWM_TCR (*(RwReg*)0x4000010CU) /**< \brief (PWM) Transmit Counter Register */ 188 #define REG_PWM_TNPR (*(RwReg*)0x40000118U) /**< \brief (PWM) Transmit Next Pointer Register */ 189 #define REG_PWM_TNCR (*(RwReg*)0x4000011CU) /**< \brief (PWM) Transmit Next Counter Register */ 190 #define REG_PWM_PTCR (*(WoReg*)0x40000120U) /**< \brief (PWM) Transfer Control Register */ 191 #define REG_PWM_PTSR (*(RoReg*)0x40000124U) /**< \brief (PWM) Transfer Status Register */ 192 #define REG_PWM_CMPV0 (*(RwReg*)0x40000130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ 193 #define REG_PWM_CMPVUPD0 (*(WoReg*)0x40000134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ 194 #define REG_PWM_CMPM0 (*(RwReg*)0x40000138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ 195 #define REG_PWM_CMPMUPD0 (*(WoReg*)0x4000013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ 196 #define REG_PWM_CMPV1 (*(RwReg*)0x40000140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ 197 #define REG_PWM_CMPVUPD1 (*(WoReg*)0x40000144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ 198 #define REG_PWM_CMPM1 (*(RwReg*)0x40000148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ 199 #define REG_PWM_CMPMUPD1 (*(WoReg*)0x4000014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ 200 #define REG_PWM_CMPV2 (*(RwReg*)0x40000150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ 201 #define REG_PWM_CMPVUPD2 (*(WoReg*)0x40000154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ 202 #define REG_PWM_CMPM2 (*(RwReg*)0x40000158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ 203 #define REG_PWM_CMPMUPD2 (*(WoReg*)0x4000015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ 204 #define REG_PWM_CMPV3 (*(RwReg*)0x40000160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ 205 #define REG_PWM_CMPVUPD3 (*(WoReg*)0x40000164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ 206 #define REG_PWM_CMPM3 (*(RwReg*)0x40000168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ 207 #define REG_PWM_CMPMUPD3 (*(WoReg*)0x4000016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ 208 #define REG_PWM_CMPV4 (*(RwReg*)0x40000170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ 209 #define REG_PWM_CMPVUPD4 (*(WoReg*)0x40000174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ 210 #define REG_PWM_CMPM4 (*(RwReg*)0x40000178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ 211 #define REG_PWM_CMPMUPD4 (*(WoReg*)0x4000017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ 212 #define REG_PWM_CMPV5 (*(RwReg*)0x40000180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ 213 #define REG_PWM_CMPVUPD5 (*(WoReg*)0x40000184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ 214 #define REG_PWM_CMPM5 (*(RwReg*)0x40000188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ 215 #define REG_PWM_CMPMUPD5 (*(WoReg*)0x4000018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ 216 #define REG_PWM_CMPV6 (*(RwReg*)0x40000190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ 217 #define REG_PWM_CMPVUPD6 (*(WoReg*)0x40000194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ 218 #define REG_PWM_CMPM6 (*(RwReg*)0x40000198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ 219 #define REG_PWM_CMPMUPD6 (*(WoReg*)0x4000019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ 220 #define REG_PWM_CMPV7 (*(RwReg*)0x400001A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ 221 #define REG_PWM_CMPVUPD7 (*(WoReg*)0x400001A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ 222 #define REG_PWM_CMPM7 (*(RwReg*)0x400001A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ 223 #define REG_PWM_CMPMUPD7 (*(WoReg*)0x400001ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ 224 #define REG_PWM_CMR0 (*(RwReg*)0x40000200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ 225 #define REG_PWM_CDTY0 (*(RwReg*)0x40000204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ 226 #define REG_PWM_CDTYUPD0 (*(WoReg*)0x40000208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ 227 #define REG_PWM_CPRD0 (*(RwReg*)0x4000020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ 228 #define REG_PWM_CPRDUPD0 (*(WoReg*)0x40000210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ 229 #define REG_PWM_CCNT0 (*(RoReg*)0x40000214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ 230 #define REG_PWM_DT0 (*(RwReg*)0x40000218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ 231 #define REG_PWM_DTUPD0 (*(WoReg*)0x4000021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ 232 #define REG_PWM_CMR1 (*(RwReg*)0x40000220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ 233 #define REG_PWM_CDTY1 (*(RwReg*)0x40000224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ 234 #define REG_PWM_CDTYUPD1 (*(WoReg*)0x40000228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ 235 #define REG_PWM_CPRD1 (*(RwReg*)0x4000022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ 236 #define REG_PWM_CPRDUPD1 (*(WoReg*)0x40000230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ 237 #define REG_PWM_CCNT1 (*(RoReg*)0x40000234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ 238 #define REG_PWM_DT1 (*(RwReg*)0x40000238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ 239 #define REG_PWM_DTUPD1 (*(WoReg*)0x4000023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ 240 #define REG_PWM_CMR2 (*(RwReg*)0x40000240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ 241 #define REG_PWM_CDTY2 (*(RwReg*)0x40000244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ 242 #define REG_PWM_CDTYUPD2 (*(WoReg*)0x40000248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ 243 #define REG_PWM_CPRD2 (*(RwReg*)0x4000024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ 244 #define REG_PWM_CPRDUPD2 (*(WoReg*)0x40000250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ 245 #define REG_PWM_CCNT2 (*(RoReg*)0x40000254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ 246 #define REG_PWM_DT2 (*(RwReg*)0x40000258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ 247 #define REG_PWM_DTUPD2 (*(WoReg*)0x4000025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ 248 #define REG_PWM_CMR3 (*(RwReg*)0x40000260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ 249 #define REG_PWM_CDTY3 (*(RwReg*)0x40000264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ 250 #define REG_PWM_CDTYUPD3 (*(WoReg*)0x40000268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ 251 #define REG_PWM_CPRD3 (*(RwReg*)0x4000026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ 252 #define REG_PWM_CPRDUPD3 (*(WoReg*)0x40000270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ 253 #define REG_PWM_CCNT3 (*(RoReg*)0x40000274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ 254 #define REG_PWM_DT3 (*(RwReg*)0x40000278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ 255 #define REG_PWM_DTUPD3 (*(WoReg*)0x4000027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ 256 #define REG_PWM_CMUPD0 (*(WoReg*)0x40000400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */ 257 #define REG_PWM_CAE0 (*(RwReg*)0x40000404U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 0) */ 258 #define REG_PWM_CAEUPD0 (*(WoReg*)0x40000408U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 0) */ 259 #define REG_PWM_CMUPD1 (*(WoReg*)0x40000420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */ 260 #define REG_PWM_CAE1 (*(RwReg*)0x40000424U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 1) */ 261 #define REG_PWM_CAEUPD1 (*(WoReg*)0x40000428U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 1) */ 262 #define REG_PWM_CMUPD2 (*(WoReg*)0x40000440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */ 263 #define REG_PWM_CAE2 (*(RwReg*)0x40000444U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 2) */ 264 #define REG_PWM_CAEUPD2 (*(WoReg*)0x40000448U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 2) */ 265 #define REG_PWM_CMUPD3 (*(WoReg*)0x40000460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */ 266 #define REG_PWM_CAE3 (*(RwReg*)0x40000464U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 3) */ 267 #define REG_PWM_CAEUPD3 (*(WoReg*)0x40000468U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 3) */ 268 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 269 270 #endif /* _SAM4E_PWM_INSTANCE_ */ 271
