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/Zephyr-latest/dts/bindings/clock/
Dgd,gd32-cctl.yaml5 Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
14 /* cell encodes RCU register offset and control bit position */
19 Predefined RCU clock cells are available in
/Zephyr-latest/dts/bindings/reset/
Dgd,gd32-rctl.yaml5 Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
14 /* cell encodes RCU register offset and control bit position */
19 Predefined RCU reset cells are available in
Dst,stm32-rcc-rctl.yaml14 /* Cell contains information about RCU register offset and bit */
/Zephyr-latest/dts/bindings/mfd/
Dgd,gd32-rcu.yaml5 Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
9 compatible: "gd,gd32-rcu"
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dgd32-clocks-common.h11 * Encode RCU register offset and configuration bit.
17 * @param reg RCU register name (expands to GD32_{reg}_OFFSET)
/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dgd32-common.h11 * Encode RCU register offset and configuration bit.
17 * @param reg RCU register name (expands to GD32_{reg}_OFFSET)
/Zephyr-latest/drivers/clock_control/
DKconfig.gd329 Enable driver for Gigadevice Reset Clock Unit (RCU).
Dclock_control_gd32.c19 /** RCU offset (from id cell) */
21 /** RCU configuration bit (from id cell) */
/Zephyr-latest/drivers/reset/
Dreset_gd32.c14 /** RCU offset (from id field) */
16 /** RCU configuration bit (from id field) */
/Zephyr-latest/include/zephyr/dt-bindings/adc/
Dgd32f3x0.h11 * defined at GD32F3X0 RCU HAL.
/Zephyr-latest/soc/gd/gd32/gd32l23x/
Dgd32_regs.h11 /* RCU */
/Zephyr-latest/soc/gd/gd32/gd32vf103/
Dgd32_regs.h11 /* RCU */
/Zephyr-latest/soc/gd/gd32/gd32e10x/
Dgd32_regs.h11 /* RCU */
/Zephyr-latest/soc/gd/gd32/gd32e50x/
Dgd32_regs.h11 /* RCU */
/Zephyr-latest/soc/gd/gd32/gd32f3x0/
Dgd32_regs.h11 /* RCU */
/Zephyr-latest/soc/gd/gd32/gd32f403/
Dgd32_regs.h11 /* RCU */
/Zephyr-latest/soc/gd/gd32/gd32a50x/
Dgd32_regs.h11 /* RCU */
/Zephyr-latest/soc/gd/gd32/gd32f4xx/
Dgd32_regs.h11 /* RCU */
/Zephyr-latest/dts/arm/gd/gd32f3x0/
Dgd32f3x0.dtsi32 rcu: reset-clock-controller@40021000 { label
33 compatible = "gd,gd32-rcu";
87 rcu-clock-source = <GD32_RCU_ADCCK_APB2_DIV4>;
/Zephyr-latest/boards/gd/gd32f350r_eval/
Dgd32f350r_eval.dts38 rcu-clock-source = <4>;
/Zephyr-latest/dts/bindings/adc/
Dgd,gd32-adc.yaml31 rcu-clock-source:
/Zephyr-latest/dts/arm/gd/gd32l23x/
Dgd32l23x.dtsi32 rcu: reset-clock-controller@40021000 { label
33 compatible = "gd,gd32-rcu";
/Zephyr-latest/drivers/pwm/
Dpwm_gd32.c57 /** Obtain RCU register offset from RCU clock value */
/Zephyr-latest/modules/hal_gigadevice/
DKconfig199 Enable GD32 Reset and Clock Unit (RCU) HAL module driver
/Zephyr-latest/dts/arm/gd/gd32a50x/
Dgd32a50x.dtsi40 rcu: reset-clock-controller@40021000 { label
41 compatible = "gd,gd32-rcu";

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