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/Zephyr-latest/drivers/counter/
DKconfig.mcux_lptmr1 # MCUXpresso SDK Low Power Timer (LPTMR)
7 bool "MCUX LPTMR driver"
12 Enable support for the MCUX Low Power Timer (LPTMR).
20 The compatible string "nxp,kinetis-lptmr" should
21 be swiched to "nxp,lptmr" in DT. The former will
Dcounter_mcux_lptmr.c179 "LPTMR resolution property should be a width between 0 and 32");\
/Zephyr-latest/dts/bindings/counter/
Dnxp,lptmr.yaml4 description: NXP LPTMR
6 compatible: "nxp,lptmr"
36 When LPTMR is in Pulse mode, this value
38 source pin" to increment the lptmr counter.
43 When LPTMR is in Pulse mode, this value
68 This value determines rather the LPTMR is configured
70 0 <- LPTMR is configured for Time Counter Mode.
71 1 <- LPTMR is configured for Pulse Mode.
Dnxp,kinetis-lptmr.yaml4 description: Deprecated compatible for NXP LPTMR
6 compatible: "nxp,kinetis-lptmr"
8 include: nxp,lptmr.yaml
/Zephyr-latest/drivers/timer/
DKconfig.mcux_lptmr7 bool "MCUX LPTMR timer"
15 Power Timer (LPTMR) and provides the standard "system clock driver"
24 The compatible string "nxp,kinetis-lptmr" should
25 be swiched to "nxp,lptmr" in DT. The former will
DKconfig.rv32m1_lptmr7 bool "RV32M1 LPTMR system timer driver"
12 This module implements a kernel device driver for using the LPTMR
Drv32m1_lptmr_timer.c21 * - system clock based on an LPTMR instance, clocked by SIRC output
76 uint32_t csr, psr, sircdiv; /* LPTMR registers */ in sys_clock_driver_init()
101 * SIRCDIV3 is the SIRC divider for LPTMR (SoC dependent). in sys_clock_driver_init()
Dmcux_lptmr_timer.c22 "No LPTMR instance enabled in devicetree");
/Zephyr-latest/dts/bindings/timer/
Dopenisa,rv32m1-lptmr.yaml1 description: OpenISA RV32M1 LPTMR peripheral
3 compatible: "openisa,rv32m1-lptmr"
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/hal/RV32M1/
Dcntr.c41 /* LPTMR config */ in cntr_init()
86 * When TEN is clear, it resets the LPTMR internal logic, in cntr_stop()
107 * When the LPTMR is enabled, the first increment will take an in cntr_cmp_set()
117 * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be in cntr_cmp_set()
Dticker.h26 * When the LPTMR is enabled, the first increment will take an additional
/Zephyr-latest/soc/nxp/kinetis/ke1xz/
DKconfig.defconfig17 default $(dt_node_int_prop_int,/soc/lptmr@40040000,clock-frequency) if MCUX_LPTMR_TIMER
/Zephyr-latest/soc/nxp/kinetis/ke1xf/
DKconfig.defconfig17 default $(dt_node_int_prop_int,/soc/lptmr@40040000,clock-frequency) if MCUX_LPTMR_TIMER
/Zephyr-latest/boards/nxp/frdm_mcxn236/
Dboard.c275 * Clock Select Decides what input source the lptmr will clock from in frdm_mcxn236_init()
289 /* Value here should not exceed 25MHZ when using lptmr */ in frdm_mcxn236_init()
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt118x.dtsi635 lptmr1: lptmr@4300000 {
636 compatible = "nxp,lptmr";
646 lptmr2: lptmr@24d0000 {
647 compatible = "nxp,lptmr";
657 lptmr3: lptmr@2cd0000 {
658 compatible = "nxp,lptmr";
Dnxp_mcxc_common.dtsi280 lptmr0: lptmr@40040000 {
281 compatible = "nxp,lptmr";
Dnxp_mcxa156.dtsi394 lptmr0: lptmr@400ab000 {
395 compatible = "nxp,lptmr";
Dnxp_mcxw71.dtsi288 compatible = "nxp,lptmr";
299 compatible = "nxp,lptmr";
Dnxp_mcxn23x_common.dtsi789 lptmr0: lptmr@4a000 {
790 compatible = "nxp,lptmr";
799 lptmr1: lptmr@4b000 {
800 compatible = "nxp,lptmr";
Dnxp_ke1xz.dtsi179 lptmr0: lptmr@40040000 {
180 compatible = "nxp,lptmr";
/Zephyr-latest/dts/riscv/openisa/
Drv32m1.dtsi271 compatible = "openisa,rv32m1-lptmr";
276 compatible = "openisa,rv32m1-lptmr";
281 compatible = "openisa,rv32m1-lptmr";
Drv32m1_ri5cy.dtsi11 system-lptmr = &lptmr0;
Drv32m1_zero_riscy.dtsi11 system-lptmr = &lptmr2;
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dboard.c340 * Clock Select Decides what input source the lptmr will clock from in frdm_mcxn947_init()
354 /* Value here should not exceed 25MHZ when using lptmr */ in frdm_mcxn947_init()
/Zephyr-latest/boards/nxp/frdm_mcxa156/
Dboard.c188 * Clock Select Decides what input source the lptmr will clock from in frdm_mcxa156_init()

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