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/Zephyr-Core-3.6.0/tests/cmake/zephyr_get/
DCMakeLists.txt22 set(ASSERT_FAIL_COUNT 0 CACHE INTERNAL "")
28 if($CACHE{ASSERT_FAIL_COUNT} GREATER 0)
34 message(${mode} "$CACHE{ASSERT_FAIL_COUNT} assertion(s) failed")
80 math(EXPR ASSERT_FAIL_COUNT "$CACHE{ASSERT_FAIL_COUNT} + 1")
81 set(ASSERT_FAIL_COUNT ${ASSERT_FAIL_COUNT} CACHE INTERNAL "")
89 set(VARIABLE "cmake cache" CACHE INTERNAL "")
92 # CMake cache value has the highest precedence.
94 assert_equal(VARIABLE "cmake cache")
97 unset(VARIABLE CACHE)
104 assert_equal(CACHE{VARIABLE} "environment")
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/Zephyr-Core-3.6.0/include/zephyr/drivers/
Dcache.h9 * Public APIs for external cache controller drivers
18 * @brief External Cache Controller Interface
19 * @defgroup cache_external_interface External Cache Controller Interface
31 * @brief Enable the d-cache
33 * Enable the data cache.
38 * @brief Disable the d-cache
40 * Disable the data cache.
45 * @brief Flush the d-cache
47 * Flush the whole data cache.
56 * @brief Invalidate the d-cache
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/Zephyr-Core-3.6.0/doc/hardware/cache/
Dindex.rst3 Cache Interface
6 This is a high-level guide to cache interface and Kconfig options related to
7 cache controllers. See :ref:`cache_api` for API reference material.
9 Zephyr has different Kconfig options to control how the cache controller is
15 instruction cache. The cache controller can be in the core or can be an
16 external cache controller for which a driver is provided.
22 options must be selected when support for data or instruction cache is
25 All the code paths related to cache control must be conditionally enabled
26 depending on these symbols. When the symbol is set the cache is considered
30 For example a platform using the data cache can enable the
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/Zephyr-Core-3.6.0/include/zephyr/arch/
Dcache.h9 * Public APIs for architectural cache controller drivers
16 * @brief Cache Controller Interface
17 * @defgroup cache_arch_interface Cache Controller Interface
23 #include <zephyr/arch/arm64/cache.h>
25 #include <zephyr/arch/xtensa/cache.h>
31 * @brief Enable the d-cache
33 * Enable the data cache.
40 * @brief Disable the d-cache
42 * Disable the data cache.
49 * @brief Flush the d-cache
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/Zephyr-Core-3.6.0/subsys/logging/
Dlog_cache.h39 int log_cache_init(struct log_cache *cache, const struct log_cache_config *config);
43 * @param[in] cache Cache object.
50 bool log_cache_get(struct log_cache *cache, uintptr_t id, uint8_t **data);
52 /** @brief Put new entry into cache.
54 * @param cache Cache object.
58 void log_cache_put(struct log_cache *cache, uint8_t *data);
63 * not found in the cache. Releasing puts entry in idle list.
65 * @param cache Cache object.
68 void log_cache_release(struct log_cache *cache, uint8_t *data);
72 * @param cache Cache object.
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Dlog_cache.c22 int log_cache_init(struct log_cache *cache, const struct log_cache_config *config) in log_cache_init() argument
24 sys_slist_init(&cache->active); in log_cache_init()
25 sys_slist_init(&cache->idle); in log_cache_init()
34 sys_slist_append(&cache->idle, &entry->node); in log_cache_init()
38 cache->cmp = config->cmp; in log_cache_init()
39 cache->item_size = config->item_size; in log_cache_init()
40 cache->hit = 0; in log_cache_init()
41 cache->miss = 0; in log_cache_init()
46 bool log_cache_get(struct log_cache *cache, uintptr_t id, uint8_t **data) in log_cache_get() argument
53 SYS_SLIST_FOR_EACH_CONTAINER(&cache->active, entry, node) { in log_cache_get()
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/Zephyr-Core-3.6.0/tests/subsys/logging/log_cache/src/
Dmain.c61 static void cache_get(struct log_cache *cache, uintptr_t id, in cache_get() argument
64 uint32_t hit = log_cache_get_hit(cache); in cache_get()
65 uint32_t miss = log_cache_get_miss(cache); in cache_get()
68 res = log_cache_get(cache, id, buf); in cache_get()
71 zassert_equal(hit + 1, log_cache_get_hit(cache), "line %u\n", line); in cache_get()
72 zassert_equal(miss, log_cache_get_miss(cache), "line %u\n", line); in cache_get()
74 zassert_equal(hit, log_cache_get_hit(cache), "line %u\n", line); in cache_get()
75 zassert_equal(miss + 1, log_cache_get_miss(cache), "line %u\n", line); in cache_get()
91 struct log_cache cache; in ZTEST() local
105 err = log_cache_init(&cache, &config); in ZTEST()
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/Zephyr-Core-3.6.0/drivers/cache/
DKconfig4 menuconfig CACHE config
5 bool "External cache controller drivers"
8 Enable support for external cache controllers drivers
10 if CACHE
15 module = CACHE
16 module-str = cache
21 source "drivers/cache/Kconfig.aspeed"
22 source "drivers/cache/Kconfig.nrf"
24 endif # CACHE
Dcache_nrf.c7 #include <zephyr/drivers/cache.h>
46 static inline bool is_cache_busy(NRF_CACHE_Type *cache) in is_cache_busy() argument
49 return nrf_cache_busy_check(cache); in is_cache_busy()
55 static inline void wait_for_cache(NRF_CACHE_Type *cache) in wait_for_cache() argument
57 while (is_cache_busy(cache)) { in wait_for_cache()
62 static inline int _cache_all(NRF_CACHE_Type *cache, enum k_nrf_cache_op op) in _cache_all() argument
65 * We really do not want to invalidate the whole cache. in _cache_all()
74 * Invalidating the whole cache is dangerous. For good measure in _cache_all()
75 * disable the cache. in _cache_all()
77 nrf_cache_disable(cache); in _cache_all()
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/Zephyr-Core-3.6.0/include/zephyr/
Dcache.h13 * @brief cache API interface
25 #include <zephyr/drivers/cache.h>
28 #include <zephyr/arch/cache.h>
33 * @defgroup cache_interface Cache Interface
48 * @brief Enable the d-cache
50 * Enable the data cache
61 * @brief Disable the d-cache
63 * Disable the data cache
74 * @brief Enable the i-cache
76 * Enable the instruction cache
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/Zephyr-Core-3.6.0/cmake/modules/
Duser_cache.cmake5 # Configure user cache directory.
7 # The user cache can be used for caching of data that should be persistent
11 # Only data that can be safely re-generated should be placed in this cache.
13 # Zephyr build system uses this user cache to store Zephyr compiler check
20 # - USER_CACHE_DIR: User cache directory in use.
33 set(env_suffix_LOCALAPPDATA .cache)
36 # On macOS, ~/Library/Caches is the preferred cache directory.
39 set(env_suffix_HOME .cache)
51 # that is defined and defaulting to $HOME/.cache otherwise.
83 # Zephyr's cache files go in the "zephyr" subdirectory of the
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/Zephyr-Core-3.6.0/soc/xtensa/espressif_esp32/esp32s3/
DKconfig.soc171 menu "Cache config"
174 prompt "Instruction cache size"
177 Instruction cache size to be set on application startup.
178 If you use 16KB instruction cache rather than 32KB instruction cache,
193 prompt "Instruction cache associated ways"
196 Instruction cache associated ways to be set on application startup.
210 prompt "Instruction cache line size"
213 Instruction cache line size to be set on application startup.
228 bool "Define instruction cache wrap mode"
230 If enabled, instruction cache will use wrap mode to read spi flash or spi ram.
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/Zephyr-Core-3.6.0/dts/riscv/starfive/
Dstarfive_jh7100_beagle_v.dtsi23 d-cache-block-size = <64>;
24 d-cache-sets = <64>;
25 d-cache-size = <32768>;
29 i-cache-block-size = <64>;
30 i-cache-sets = <64>;
31 i-cache-size = <32768>;
35 next-level-cache = <&cachectrl>;
52 d-cache-block-size = <64>;
53 d-cache-sets = <64>;
54 d-cache-size = <32768>;
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/Zephyr-Core-3.6.0/subsys/fs/nvs/
DKconfig15 bool "Non-volatile Storage lookup cache"
17 Enable Non-volatile Storage cache, used to reduce the NVS data lookup
18 time. Each cache entry holds an address of the most recent allocation
19 table entry (ATE) for all NVS IDs that fall into that cache position.
22 int "Non-volatile Storage lookup cache size"
27 Number of entries in Non-volatile Storage lookup cache.
/Zephyr-Core-3.6.0/lib/os/
DKconfig40 prompt "Cache handling"
46 bool "Use cache flag"
48 Use instance specific configuration flag for cache handling.
51 bool "Always handle cache"
53 Handle cache writeback and invalidation for all instances. Option used
57 bool "Never handle cache"
59 Discar cache handling for all instances. Option used to avoid runtime
73 int "Remote cache line size"
77 this value should be set to the data cache line size of the remote core.
78 If local data cache line is detected at runtime then it should be
/Zephyr-Core-3.6.0/arch/nios2/core/
Dcache.c12 * Flush the entire instruction cache and pipeline.
16 * new text was written with instructions that do not bypass cache memories,
22 * information on cache considerations.
39 * Flush the entire data cache.
42 * after flushing the instruction cache.
44 * The Nios II does not support hardware cache coherency for multi-master
47 * in Zephyr additional APIs for flushing ranges of the data cache will need
51 * information on cache considerations.
65 * z_nios2_dcache_flush_no_writeback() is called to flush the data cache for a
68 * Any dirty lines in the data cache are NOT written back to memory.
/Zephyr-Core-3.6.0/scripts/tests/twister/
Dtest_cmakecache.py182 cache = CMakeCache.from_file('dummy/path/CMakeCache.txt')
184 assert cache.cache_file == 'dummy/path/CMakeCache.txt'
193 item = cache._entries.popitem()
204 cache = CMakeCache.from_file('dummy/path/CMakeCache.txt')
206 good_val = cache.get('DUMMY_NAME')
210 bad_val = cache.get('ANOTHER_NAME')
214 bad_val = cache.get('ANOTHER_NAME', default='No such value')
237 cache = CMakeCache.from_file('dummy/path/CMakeCache.txt')
242 res = cache.get_list('DUMMY_NAME') if \
243 correct_get else cache.get_list('ANOTHER_NAME')
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/Zephyr-Core-3.6.0/tests/lib/spsc_pbuf/
Dtestcase.yaml5 # Exclude platform which does not link with cache functions
9 libraries.spsc_pbuf.cache:
12 # Exclude platform which does not link with cache functions
21 # Exclude platform which does not link with cache functions
30 # Exclude platform which does not link with cache functions
/Zephyr-Core-3.6.0/.github/workflows/
Ddevicetree_checks.yml43 - name: cache-pip-linux
45 uses: actions/cache@v4
47 path: ~/.cache/pip
51 - name: cache-pip-mac
53 uses: actions/cache@v4
56 # Trailing '-' was just to get a different cache name
60 - name: cache-pip-win
62 uses: actions/cache@v4
64 path: ~\AppData\Local\pip\Cache
Dclang.yaml17 - /repo-cache/zephyrproject:/github/cache/zephyrproject
40 git clone --shared /github/cache/zephyrproject/zephyr .
66cache /github/cache/zephyrproject 2>&1 1> west.log || west update --path-cache /github/cache/zephy…
86 - name: use cache
87 id: cache-ccache
88 uses: zephyrproject-rtos/action-s3-cache@v1.2.0
91 path: /github/home/.cache/ccache
99 mkdir -p /github/home/.cache
100 …test -d github/home/.cache/ccache && rm -rf /github/home/.cache/ccache && mv github/home/.cache/cc…
Dwest_cmds.yml44 - name: cache-pip-linux
46 uses: actions/cache@v4
48 path: ~/.cache/pip
52 - name: cache-pip-mac
54 uses: actions/cache@v4
57 # Trailing '-' was just to get a different cache name
61 - name: cache-pip-win
63 uses: actions/cache@v4
65 path: ~\AppData\Local\pip\Cache
/Zephyr-Core-3.6.0/subsys/fs/
DKconfig.littlefs46 Each cache buffers a portion of a block in RAM. The littlefs
47 needs a read cache, a program cache, and one additional cache
73 int "Enable flexible file cache sizes for littlefs"
76 littlefs requires a per-file buffer to cache data.
79 different cache sizes for different partitions this preallocation is
81 using a large cache size and a larger number of files using a
82 smaller cache size. In that case application should provide a
99 For the purpose of heap size calculation the size of each cache block
/Zephyr-Core-3.6.0/tests/kernel/cache/
Dtestcase.yaml2 kernel.cache.api:
5 - cache
17 kernel.cache.api.minimallibc:
20 - cache
/Zephyr-Core-3.6.0/arch/arc/core/
Dprep_c.c27 /* XXX - keep for future use in full-featured cache APIs */
30 * @brief Disable the i-cache if present
32 * For those ARC CPUs that have a i-cache present,
33 * invalidate the i-cache and then disable it.
43 return; /* skip if i-cache is not present */
51 * @brief Invalidate the data cache if present
53 * For those ARC CPUs that have a data cache present,
54 * invalidate the data cache.
64 return; /* skip if d-cache is not present */
82 /* Check that we have shared cache in cluster */ in arc_cluster_scm_enable()
/Zephyr-Core-3.6.0/drivers/flash/
Dflash_stm32wbax.c33 LOG_DBG("I-cache Disable"); in stm32_icache_disable()
34 /* Clear BSYENDF flag first and then disable the instruction cache in stm32_icache_disable()
35 * that starts a cache invalidation procedure in stm32_icache_disable()
44 /* Wait for instruction cache to get disabled */ in stm32_icache_disable()
63 LOG_DBG("I-cache Enable"); in stm32_icache_enable()
77 /* Wait for end of cache invalidation */ in icache_wait_for_invalidate_complete()
88 LOG_DBG("I-cache Invalidation complete"); in icache_wait_for_invalidate_complete()
93 LOG_ERR("I-cache Invalidation timeout"); in icache_wait_for_invalidate_complete()
99 LOG_ERR("I-cache error"); in icache_wait_for_invalidate_complete()
208 * i-cache is disabled. A write to flash performed without in flash_stm32_block_erase_loop()
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