1 /*
2 * Copyright (c) 2023 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define LOG_DOMAIN flash_stm32wba
8 #define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
9 #include <zephyr/logging/log.h>
10 LOG_MODULE_REGISTER(LOG_DOMAIN);
11
12 #include <zephyr/kernel.h>
13 #include <zephyr/device.h>
14 #include <string.h>
15 #include <zephyr/drivers/flash.h>
16 #include <zephyr/init.h>
17 #include <soc.h>
18 #include <stm32_ll_icache.h>
19 #include <stm32_ll_system.h>
20
21 #include "flash_stm32.h"
22
23 #define STM32_SERIES_MAX_FLASH 1024
24
25 #define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
26 #define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */
27
stm32_icache_disable(void)28 static int stm32_icache_disable(void)
29 {
30 int status = 0;
31 uint32_t tickstart;
32
33 LOG_DBG("I-cache Disable");
34 /* Clear BSYENDF flag first and then disable the instruction cache
35 * that starts a cache invalidation procedure
36 */
37 CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
38
39 LL_ICACHE_Disable();
40
41 /* Get tick */
42 tickstart = k_uptime_get_32();
43
44 /* Wait for instruction cache to get disabled */
45 while (LL_ICACHE_IsEnabled()) {
46 if ((k_uptime_get_32() - tickstart) >
47 ICACHE_DISABLE_TIMEOUT_VALUE) {
48 /* New check to avoid false timeout detection in case
49 * of preemption.
50 */
51 if (LL_ICACHE_IsEnabled()) {
52 status = -ETIMEDOUT;
53 break;
54 }
55 }
56 }
57
58 return status;
59 }
60
stm32_icache_enable(void)61 static void stm32_icache_enable(void)
62 {
63 LOG_DBG("I-cache Enable");
64 LL_ICACHE_Enable();
65 }
66
icache_wait_for_invalidate_complete(void)67 static int icache_wait_for_invalidate_complete(void)
68 {
69 int status = -EIO;
70 uint32_t tickstart;
71
72 /* Check if ongoing invalidation operation */
73 if (LL_ICACHE_IsActiveFlag_BUSY()) {
74 /* Get tick */
75 tickstart = k_uptime_get_32();
76
77 /* Wait for end of cache invalidation */
78 while (!LL_ICACHE_IsActiveFlag_BSYEND()) {
79 if ((k_uptime_get_32() - tickstart) >
80 ICACHE_INVALIDATE_TIMEOUT_VALUE) {
81 break;
82 }
83 }
84 }
85
86 /* Clear any pending flags */
87 if (LL_ICACHE_IsActiveFlag_BSYEND()) {
88 LOG_DBG("I-cache Invalidation complete");
89
90 LL_ICACHE_ClearFlag_BSYEND();
91 status = 0;
92 } else {
93 LOG_ERR("I-cache Invalidation timeout");
94
95 status = -ETIMEDOUT;
96 }
97
98 if (LL_ICACHE_IsActiveFlag_ERR()) {
99 LOG_ERR("I-cache error");
100
101 LL_ICACHE_ClearFlag_ERR();
102 status = -EIO;
103 }
104
105 return status;
106 }
107
write_qword(const struct device * dev,off_t offset,const uint32_t * buff)108 static int write_qword(const struct device *dev, off_t offset, const uint32_t *buff)
109 {
110 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
111 volatile uint32_t *flash = (uint32_t *)(offset
112 + FLASH_STM32_BASE_ADDRESS);
113 uint32_t tmp;
114 int rc;
115
116 /* if the non-secure control register is locked, do not fail silently */
117 if (regs->NSCR & FLASH_STM32_NSLOCK) {
118 LOG_ERR("NSCR locked\n");
119 return -EIO;
120 }
121
122 /* Check that no Flash main memory operation is ongoing */
123 rc = flash_stm32_wait_flash_idle(dev);
124 if (rc < 0) {
125 return rc;
126 }
127
128 /* Check if this double word is erased */
129 if ((flash[0] != 0xFFFFFFFFUL) || (flash[1] != 0xFFFFFFFFUL) ||
130 (flash[2] != 0xFFFFFFFFUL) || (flash[3] != 0xFFFFFFFFUL)) {
131 LOG_ERR("Word at offs %ld not erased", (long)offset);
132 return -EIO;
133 }
134
135 /* Set the NSPG bit */
136 regs->NSCR |= FLASH_STM32_NSPG;
137
138 /* Flush the register write */
139 tmp = regs->NSCR;
140
141 /* Perform the data write operation at the desired memory address */
142 flash[0] = buff[0];
143 flash[1] = buff[1];
144 flash[2] = buff[2];
145 flash[3] = buff[3];
146
147 /* Wait until the NSBSY bit is cleared */
148 rc = flash_stm32_wait_flash_idle(dev);
149
150 /* Clear the NSPG bit */
151 regs->NSCR &= (~FLASH_STM32_NSPG);
152
153 return rc;
154 }
155
erase_page(const struct device * dev,unsigned int offset)156 static int erase_page(const struct device *dev, unsigned int offset)
157 {
158 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
159 uint32_t tmp;
160 int rc;
161 int page;
162
163 /* if the non-secure control register is locked,do not fail silently */
164 if (regs->NSCR & FLASH_STM32_NSLOCK) {
165 LOG_ERR("NSCR locked\n");
166 return -EIO;
167 }
168
169 /* Check that no Flash memory operation is ongoing */
170 rc = flash_stm32_wait_flash_idle(dev);
171 if (rc < 0) {
172 return rc;
173 }
174
175 page = offset / FLASH_PAGE_SIZE;
176 LOG_DBG("Erase page %d\n", page);
177
178 /* Set the NSPER bit and select the page you wish to erase */
179 regs->NSCR |= FLASH_STM32_NSPER;
180 regs->NSCR &= ~FLASH_STM32_NSPNB_MSK;
181 regs->NSCR |= (page << FLASH_STM32_NSPNB_POS);
182
183 /* Set the NSSTRT bit */
184 regs->NSCR |= FLASH_STM32_NSSTRT;
185
186 /* flush the register write */
187 tmp = regs->NSCR;
188
189 /* Wait for the NSBSY bit */
190 rc = flash_stm32_wait_flash_idle(dev);
191
192 regs->NSCR &= ~(FLASH_STM32_NSPER);
193
194 return rc;
195 }
196
flash_stm32_block_erase_loop(const struct device * dev,unsigned int offset,unsigned int len)197 int flash_stm32_block_erase_loop(const struct device *dev,
198 unsigned int offset,
199 unsigned int len)
200 {
201 unsigned int address = offset;
202 int rc = 0;
203 bool icache_enabled = LL_ICACHE_IsEnabled();
204
205 if (icache_enabled) {
206 /* Disable icache, this will start the invalidation procedure.
207 * All changes(erase/write) to flash memory should happen when
208 * i-cache is disabled. A write to flash performed without
209 * disabling i-cache will set ERRF error flag in SR register.
210 */
211 rc = stm32_icache_disable();
212 if (rc != 0) {
213 return rc;
214 }
215 }
216
217 for (; address <= offset + len - 1 ; address += FLASH_PAGE_SIZE) {
218 rc = erase_page(dev, address);
219 if (rc < 0) {
220 break;
221 }
222 }
223
224 if (icache_enabled) {
225 /* Since i-cache was disabled, this would start the
226 * invalidation procedure, so wait for completion.
227 */
228 rc = icache_wait_for_invalidate_complete();
229
230 /* I-cache should be enabled only after the
231 * invalidation is complete.
232 */
233 stm32_icache_enable();
234 }
235
236 return rc;
237 }
238
flash_stm32_write_range(const struct device * dev,unsigned int offset,const void * data,unsigned int len)239 int flash_stm32_write_range(const struct device *dev, unsigned int offset,
240 const void *data, unsigned int len)
241 {
242 int i, rc = 0;
243 bool icache_enabled = LL_ICACHE_IsEnabled();
244
245 if (icache_enabled) {
246 /* Disable icache, this will start the invalidation procedure.
247 * All changes(erase/write) to flash memory should happen when
248 * i-cache is disabled. A write to flash performed without
249 * disabling i-cache will set ERRF error flag in SR register.
250 */
251 rc = stm32_icache_disable();
252 if (rc != 0) {
253 return rc;
254 }
255 }
256
257 for (i = 0; i < len; i += 16) {
258 rc = write_qword(dev, offset + i, ((const uint32_t *) data + (i>>2)));
259 if (rc < 0) {
260 break;
261 }
262 }
263
264 if (icache_enabled) {
265 /* Since i-cache was disabled, this would start the
266 * invalidation procedure, so wait for completion.
267 */
268 rc = icache_wait_for_invalidate_complete();
269
270 /* I-cache should be enabled only after the
271 * invalidation is complete.
272 */
273 stm32_icache_enable();
274 }
275
276 return rc;
277 }
278
flash_stm32_page_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)279 void flash_stm32_page_layout(const struct device *dev,
280 const struct flash_pages_layout **layout,
281 size_t *layout_size)
282 {
283 static struct flash_pages_layout stm32wba_flash_layout = {
284 .pages_count = 0,
285 .pages_size = 0,
286 };
287
288 ARG_UNUSED(dev);
289
290 if (stm32wba_flash_layout.pages_count == 0) {
291 stm32wba_flash_layout.pages_count = FLASH_SIZE / FLASH_PAGE_SIZE;
292 stm32wba_flash_layout.pages_size = FLASH_PAGE_SIZE;
293 }
294
295 *layout = &stm32wba_flash_layout;
296 *layout_size = 1;
297 }
298
