Lines Matching full:cache

9  * Public APIs for architectural cache controller drivers
16  * @brief Cache Controller Interface
17  * @defgroup cache_arch_interface Cache Controller Interface
23 #include <zephyr/arch/arm64/cache.h>
25 #include <zephyr/arch/xtensa/cache.h>
31  * @brief Enable the d-cache
33  * Enable the data cache.
40  * @brief Disable the d-cache
42  * Disable the data cache.
49  * @brief Flush the d-cache
51  * Flush the whole data cache.
62  * @brief Invalidate the d-cache
64  * Invalidate the whole data cache.
75  * @brief Flush and Invalidate the d-cache
77  * Flush and Invalidate the whole data cache.
88  * @brief Flush an address range in the d-cache
90  * Flush the specified address range of the data cache.
92  * @note the cache operations act on cache line. When multiple data structures
93  *       share the same cache line being flushed, all the portions of the
111  * @brief Invalidate an address range in the d-cache
113  * Invalidate the specified address range of the data cache.
115  * @note the cache operations act on cache line. When multiple data structures
116  *       share the same cache line being invalidated, all the portions of the
119  *       data loss and/or corruption. When @p addr is not aligned to the cache
120  *       line and/or @p size is not a multiple of the cache line size the
135  * @brief Flush and Invalidate an address range in the d-cache
137  * Flush and Invalidate the specified address range of the data cache.
139  * @note the cache operations act on cache line. When multiple data structures
140  *       share the same cache line being flushed, all the portions of the
164  * @brief Get the d-cache line size.
166  * The API is provided to dynamically detect the data cache line size at run
172  * @retval size Size of the d-cache line.
173  * @retval 0 If the d-cache is not enabled.
186  * @brief Enable the i-cache
188  * Enable the instruction cache.
195  * @brief Disable the i-cache
197  * Disable the instruction cache.
204  * @brief Flush the i-cache
206  * Flush the whole instruction cache.
217  * @brief Invalidate the i-cache
219  * Invalidate the whole instruction cache.
230  * @brief Flush and Invalidate the i-cache
232  * Flush and Invalidate the whole instruction cache.
243  * @brief Flush an address range in the i-cache
245  * Flush the specified address range of the instruction cache.
247  * @note the cache operations act on cache line. When multiple data structures
248  *       share the same cache line being flushed, all the portions of the
266  * @brief Invalidate an address range in the i-cache
268  * Invalidate the specified address range of the instruction cache.
270  * @note the cache operations act on cache line. When multiple data structures
271  *       share the same cache line being invalidated, all the portions of the
274  *       data loss and/or corruption. When @p addr is not aligned to the cache
275  *       line and/or @p size is not a multiple of the cache line size the
290  * @brief Flush and Invalidate an address range in the i-cache
292  * Flush and Invalidate the specified address range of the instruction cache.
294  * @note the cache operations act on cache line. When multiple data structures
295  *       share the same cache line being flushed, all the portions of the
318  * @brief Get the i-cache line size.
320  * The API is provided to dynamically detect the instruction cache line size at
326  * @retval size Size of the d-cache line.
327  * @retval 0 If the d-cache is not enabled.