Lines Matching full:cache

13  * @brief cache API interface
25 #include <zephyr/drivers/cache.h>
28 #include <zephyr/arch/cache.h>
33  * @defgroup cache_interface Cache Interface
48  * @brief Enable the d-cache
50  * Enable the data cache
61  * @brief Disable the d-cache
63  * Disable the data cache
74  * @brief Enable the i-cache
76  * Enable the instruction cache
87  * @brief Disable the i-cache
89  * Disable the instruction cache
100  * @brief Flush the d-cache
102  * Flush the whole data cache.
117  * @brief Flush the i-cache
119  * Flush the whole instruction cache.
134  * @brief Invalidate the d-cache
136  * Invalidate the whole data cache.
151  * @brief Invalidate the i-cache
153  * Invalidate the whole instruction cache.
168  * @brief Flush and Invalidate the d-cache
170  * Flush and Invalidate the whole data cache.
185  * @brief Flush and Invalidate the i-cache
187  * Flush and Invalidate the whole instruction cache.
202  * @brief Flush an address range in the d-cache
204  * Flush the specified address range of the data cache.
206  * @note the cache operations act on cache line. When multiple data structures
207  *       share the same cache line being flushed, all the portions of the
234  * @brief Flush an address range in the i-cache
236  * Flush the specified address range of the instruction cache.
238  * @note the cache operations act on cache line. When multiple data structures
239  *       share the same cache line being flushed, all the portions of the
264  * @brief Invalidate an address range in the d-cache
266  * Invalidate the specified address range of the data cache.
268  * @note the cache operations act on cache line. When multiple data structures
269  *       share the same cache line being invalidated, all the portions of the
272  *       data loss and/or corruption. When @p addr is not aligned to the cache
273  *       line and/or @p size is not a multiple of the cache line size the
297  * @brief Invalidate an address range in the i-cache
299  * Invalidate the specified address range of the instruction cache.
301  * @note the cache operations act on cache line. When multiple data structures
302  *       share the same cache line being invalidated, all the portions of the
305  *       data loss and/or corruption. When @p addr is not aligned to the cache
306  *       line and/or @p size is not a multiple of the cache line size the
328  * @brief Flush and Invalidate an address range in the d-cache
330  * Flush and Invalidate the specified address range of the data cache.
332  * @note the cache operations act on cache line. When multiple data structures
333  *       share the same cache line being flushed, all the portions of the
361  * @brief Flush and Invalidate an address range in the i-cache
363  * Flush and Invalidate the specified address range of the instruction cache.
365  * @note the cache operations act on cache line. When multiple data structures
366  *       share the same cache line being flushed, all the portions of the
393  * @brief Get the the d-cache line size.
395  * The API is provided to get the data cache line.
397  * The cache line size is calculated (in order of priority):
401  * - At compile time using the `d-cache-line-size` CPU0 property of the DT.
404  * @retval size Size of the d-cache line.
405  * @retval 0 If the d-cache is not enabled.
420  * @brief Get the the i-cache line size.
422  * The API is provided to get the instruction cache line.
424  * The cache line size is calculated (in order of priority):
428  * - At compile time using the `i-cache-line-size` CPU0 property of the DT.
431  * @retval size Size of the d-cache line.
432  * @retval 0 If the d-cache is not enabled.
498  * refer to the same memory through the L1 data cache.  Data read
501  * cache and be written back later.
525  * refer to the same memory while bypassing the L1 data cache.  Data
526  * in the L1 cache will not be inspected nor modified by the access.
553 #include <syscalls/cache.h>