Home
last modified time | relevance | path

Searched full:clk_sys (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/dts/bindings/clock/
Dst,stm32wb0-rcc.yaml47 CLK_SYS prescaler. Defines actual core clock frequency (CLK_SYS) based
49 The CLK_SYS is used to clock the CPU, AHB, APB, memories and PKA.
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_wb0.c275 uint32_t *rate, uint32_t slow_clock, uint32_t sysclk, uint32_t clk_sys) in get_apb0_periph_clkrate() argument
300 /* CLK_SYS peripherals: SYSCFG */ in get_apb0_periph_clkrate()
302 *rate = clk_sys; in get_apb0_periph_clkrate()
316 uint32_t *rate, uint32_t clk_sys) in get_apb1_periph_clkrate() argument
321 *rate = clk_sys; in get_apb1_periph_clkrate()
407 uint32_t sysclk, slow_clock, clk_sys; in stm32_clock_control_get_subsys_rate() local
423 * setting CLKSYSDIV = 1 results in 32MHz CLK_SYS, regardless of SYSCLK being 32 or 64MHZ. in stm32_clock_control_get_subsys_rate()
431 /* Obtain CLK_SYS (AHB0) frequency by using the CLKSYSDIV prescaler value. in stm32_clock_control_get_subsys_rate()
442 clk_sys = CLOCK_FREQ_64MHZ >> LL_RCC_GetRC64MPLLPrescaler(); in stm32_clock_control_get_subsys_rate()
464 /* All peripherals on AHB0 are clocked by CLK_SYS. */ in stm32_clock_control_get_subsys_rate()
[all …]
Dclock_control_rpi_pico.c87 #define CLOCK_FREQ_clk_sys DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_sys), clock_frequency)
108 #define AUXSRC_clk_sys CLK_SYS
815 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_sys) >= CLOCK_FREQ_clk_sys,
816 "clk_sys: clock divider is out of range");
878 #if CLK_SRC_IS(clk_sys, clk_ref)
883 .aux_source = CLOCK_AUX_SOURCE(clk_sys),
885 .source_rate = SRC_CLOCK_FREQ(clk_sys),
886 .rate = CLOCK_FREQ(clk_sys),
/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2040.dtsi88 clk_sys: clk-sys { label
122 clocks = <&clk_sys>;
123 clock-names = "clk_sys";
230 <&clk_ref>, <&clk_sys>, <&clk_peri>,
235 "clk_ref", "clk_sys", "clk_peri",
Drp2350.dtsi92 clk_sys: clk-sys { label
118 clocks = <&clk_sys>;
119 clock-names = "clk_sys";
227 <&clk_hstx>, <&clk_ref>, <&clk_sys>, <&clk_peri>,
232 "clk_hstx", "clk_ref", "clk_sys", "clk_peri",
/Zephyr-latest/soc/st/stm32/stm32wb0x/
Dsoc.c156 /* Update CMSIS SystemCoreClock variable (CLK_SYS) */ in stm32wb0_init()
159 * CLK_SYS being equal to 16MHz. in stm32wb0_init()
/Zephyr-latest/drivers/usb/udc/
Dudc_rpi_pico.c36 clock_control_subsys_t clk_sys; member
216 * By default, clk_sys runs at 125MHz, wait 3 nop instructions before in rpi_pico_prep_rx()
253 * By default, clk_sys runs at 125MHz, wait 3 nop instructions before in rpi_pico_prep_tx()
851 * By default, clk_sys runs at 125MHz, wait 3 nop instructions in udc_rpi_pico_ep_clear_halt()
976 return clock_control_on(config->clk_dev, config->clk_sys); in udc_rpi_pico_init()
993 return clock_control_off(config->clk_dev, config->clk_sys); in udc_rpi_pico_shutdown()
1141 .clk_sys = (void *)DT_INST_PHA_BY_IDX(n, clocks, 0, clk_id), \
/Zephyr-latest/drivers/serial/
Duart_rpi_pico_pio.c154 sm_clock_div = (float)clock_get_hz(clk_sys) / (CYCLES_PER_BIT * config->baudrate); in pio_uart_init()
/Zephyr-latest/drivers/bluetooth/hci/
Dhci_stm32wb0.c264 /* If the device is configured with CLK_SYS = 64MHz in ISR_DIRECT_DECLARE()
/Zephyr-latest/drivers/usb/device/
Dusb_dc_rpi_pico.c136 * By default, clk_sys runs at 125MHz, wait 3 nop instructions before in udc_rpi_start_xfer()