1 /*
2 * Copyright (c) 2024 Nordic Semiconductor ASA
3 * Copyright (c) 2021 Pete Johanson
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include "udc_common.h"
9
10 #include <string.h>
11 #include <stdio.h>
12
13 #include <soc.h>
14 #include <hardware/structs/usb.h>
15 #include <hardware/resets.h>
16
17 #include <zephyr/kernel.h>
18 #include <zephyr/sys/mem_blocks.h>
19 #include <zephyr/drivers/usb/udc.h>
20 #include <zephyr/drivers/clock_control.h>
21
22 #include <zephyr/logging/log.h>
23 LOG_MODULE_REGISTER(udc_rpi_pico, CONFIG_UDC_DRIVER_LOG_LEVEL);
24
25 struct rpi_pico_config {
26 usb_hw_t *base;
27 usb_device_dpram_t *dpram;
28 sys_mem_blocks_t *mem_block;
29 size_t num_of_eps;
30 struct udc_ep_config *ep_cfg_in;
31 struct udc_ep_config *ep_cfg_out;
32 void (*make_thread)(const struct device *dev);
33 void (*irq_enable_func)(const struct device *dev);
34 void (*irq_disable_func)(const struct device *dev);
35 const struct device *clk_dev;
36 clock_control_subsys_t clk_sys;
37 };
38
39 struct rpi_pico_ep_data {
40 void *buf;
41 uint8_t next_pid;
42 };
43
44 struct rpi_pico_data {
45 struct k_thread thread_data;
46 struct rpi_pico_ep_data out_ep[USB_NUM_ENDPOINTS];
47 struct rpi_pico_ep_data in_ep[USB_NUM_ENDPOINTS];
48 bool rwu_pending;
49 uint8_t setup[8];
50 };
51
52 enum rpi_pico_event_type {
53 /* Trigger next transfer, must not be used for control OUT */
54 RPI_PICO_EVT_XFER,
55 /* Setup packet received */
56 RPI_PICO_EVT_SETUP,
57 /* OUT transaction for specific endpoint is finished */
58 RPI_PICO_EVT_DOUT,
59 /* IN transaction for specific endpoint is finished */
60 RPI_PICO_EVT_DIN,
61 };
62
63 struct rpi_pico_event {
64 const struct device *dev;
65 enum rpi_pico_event_type type;
66 uint8_t ep;
67 };
68
69 K_MSGQ_DEFINE(drv_msgq, sizeof(struct rpi_pico_event), 16, sizeof(void *));
70
71 /* Use Atomic Register Access to set bits */
rpi_pico_bit_set(const mm_reg_t reg,const uint32_t bit)72 static void ALWAYS_INLINE rpi_pico_bit_set(const mm_reg_t reg, const uint32_t bit)
73 {
74 sys_write32(bit, REG_ALIAS_SET_BITS | reg);
75 }
76
77 /* Use Atomic Register Access to clear bits */
rpi_pico_bit_clr(const mm_reg_t reg,const uint32_t bit)78 static void ALWAYS_INLINE rpi_pico_bit_clr(const mm_reg_t reg, const uint32_t bit)
79 {
80 sys_write32(bit, REG_ALIAS_CLR_BITS | reg);
81 }
82
sie_status_clr(const struct device * dev,const uint32_t bit)83 static void ALWAYS_INLINE sie_status_clr(const struct device *dev, const uint32_t bit)
84 {
85 const struct rpi_pico_config *config = dev->config;
86 usb_hw_t *base = config->base;
87
88 rpi_pico_bit_clr((mm_reg_t)&base->sie_status, bit);
89 }
90
get_ep_mask(const uint8_t ep)91 static inline uint32_t get_ep_mask(const uint8_t ep)
92 {
93 const int idx = USB_EP_GET_IDX(ep) * 2 + USB_EP_DIR_IS_OUT(ep);
94
95 return BIT(idx);
96 }
97
98 /* Get the address of an endpoint control register */
get_ep_ctrl_reg(const struct device * dev,const uint8_t ep)99 static mem_addr_t get_ep_ctrl_reg(const struct device *dev, const uint8_t ep)
100 {
101 const struct rpi_pico_config *config = dev->config;
102 usb_device_dpram_t *dpram = config->dpram;
103
104 if (USB_EP_GET_IDX(ep) == 0) {
105 return 0UL;
106 }
107
108 if (USB_EP_DIR_IS_OUT(ep)) {
109 return (uintptr_t)&dpram->ep_ctrl[USB_EP_GET_IDX(ep) - 1].out;
110 }
111
112 return (uintptr_t)&dpram->ep_ctrl[USB_EP_GET_IDX(ep) - 1].in;
113 }
114
115 /* Get the address of an endpoint buffer control register */
get_buf_ctrl_reg(const struct device * dev,const uint8_t ep)116 static mem_addr_t get_buf_ctrl_reg(const struct device *dev, const uint8_t ep)
117 {
118 const struct rpi_pico_config *config = dev->config;
119 usb_device_dpram_t *dpram = config->dpram;
120
121 if (USB_EP_DIR_IS_OUT(ep)) {
122 return (uintptr_t)&dpram->ep_buf_ctrl[USB_EP_GET_IDX(ep)].out;
123 }
124
125 return (uintptr_t)&dpram->ep_buf_ctrl[USB_EP_GET_IDX(ep)].in;
126 }
127
128 /* Get the address of an endpoint buffer control register */
get_ep_data(const struct device * dev,const uint8_t ep)129 static struct rpi_pico_ep_data *get_ep_data(const struct device *dev, const uint8_t ep)
130 {
131 struct rpi_pico_data *priv = udc_get_private(dev);
132
133 if (USB_EP_DIR_IS_OUT(ep)) {
134 return &priv->out_ep[USB_EP_GET_IDX(ep)];
135 }
136
137 return &priv->in_ep[USB_EP_GET_IDX(ep)];
138 }
139
read_buf_ctrl_reg(const struct device * dev,const uint8_t ep)140 static uint32_t read_buf_ctrl_reg(const struct device *dev, const uint8_t ep)
141 {
142 mm_reg_t buf_ctrl_reg = get_buf_ctrl_reg(dev, ep);
143
144 return sys_read32(buf_ctrl_reg);
145 }
146
write_buf_ctrl_reg(const struct device * dev,const uint8_t ep,const uint32_t buf_ctrl)147 static void write_buf_ctrl_reg(const struct device *dev, const uint8_t ep,
148 const uint32_t buf_ctrl)
149 {
150 mm_reg_t buf_ctrl_reg = get_buf_ctrl_reg(dev, ep);
151
152 sys_write32(buf_ctrl, buf_ctrl_reg);
153 }
154
write_ep_ctrl_reg(const struct device * dev,const uint8_t ep,const uint32_t ep_ctrl)155 static void write_ep_ctrl_reg(const struct device *dev, const uint8_t ep,
156 const uint32_t ep_ctrl)
157 {
158 mm_reg_t ep_ctrl_reg = get_ep_ctrl_reg(dev, ep);
159
160 sys_write32(ep_ctrl, ep_ctrl_reg);
161 }
162
rpi_pico_ep_cancel(const struct device * dev,const uint8_t ep)163 static void rpi_pico_ep_cancel(const struct device *dev, const uint8_t ep)
164 {
165 bool abort_handshake_supported = rp2040_chip_version() >= 2;
166 const struct rpi_pico_config *config = dev->config;
167 usb_hw_t *base = config->base;
168 mm_reg_t abort_done_reg = (mm_reg_t)&base->abort_done;
169 mm_reg_t abort_reg = (mm_reg_t)&base->abort;
170 const uint32_t ep_mask = get_ep_mask(ep);
171 uint32_t buf_ctrl;
172
173 buf_ctrl = read_buf_ctrl_reg(dev, ep);
174 if (!(buf_ctrl & USB_BUF_CTRL_AVAIL)) {
175 /* The buffer is not used by the controller */
176 return;
177 }
178
179 if (abort_handshake_supported) {
180 rpi_pico_bit_set(abort_reg, ep_mask);
181 while ((sys_read32(abort_done_reg) & ep_mask) != ep_mask) {
182 }
183 }
184
185 buf_ctrl &= ~USB_BUF_CTRL_AVAIL;
186 write_buf_ctrl_reg(dev, ep, buf_ctrl);
187
188 if (abort_handshake_supported) {
189 rpi_pico_bit_clr(abort_reg, ep_mask);
190 }
191
192 LOG_INF("Canceled ep 0x%02x transaction", ep);
193 }
194
rpi_pico_prep_rx(const struct device * dev,struct net_buf * const buf,struct udc_ep_config * const cfg)195 static int rpi_pico_prep_rx(const struct device *dev,
196 struct net_buf *const buf, struct udc_ep_config *const cfg)
197 {
198 struct rpi_pico_ep_data *const ep_data = get_ep_data(dev, cfg->addr);
199 uint32_t buf_ctrl;
200
201 buf_ctrl = read_buf_ctrl_reg(dev, cfg->addr);
202 if (buf_ctrl & USB_BUF_CTRL_AVAIL) {
203 LOG_ERR("ep 0x%02x buffer is used by the controller", cfg->addr);
204 return -EBUSY;
205 }
206
207 LOG_DBG("Prepare RX ep 0x%02x len %u pid: %u",
208 cfg->addr, net_buf_tailroom(buf), ep_data->next_pid);
209
210 buf_ctrl = cfg->mps;
211 buf_ctrl |= ep_data->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
212 ep_data->next_pid ^= 1U;
213
214 write_buf_ctrl_reg(dev, cfg->addr, buf_ctrl);
215 /*
216 * By default, clk_sys runs at 125MHz, wait 3 nop instructions before
217 * setting the AVAILABLE bit. See 4.1.2.5.1. Concurrent access.
218 */
219 arch_nop();
220 arch_nop();
221 arch_nop();
222 write_buf_ctrl_reg(dev, cfg->addr, buf_ctrl | USB_BUF_CTRL_AVAIL);
223
224 return 0;
225 }
226
rpi_pico_prep_tx(const struct device * dev,struct net_buf * const buf,struct udc_ep_config * const cfg)227 static int rpi_pico_prep_tx(const struct device *dev,
228 struct net_buf *const buf, struct udc_ep_config *const cfg)
229 {
230 struct rpi_pico_ep_data *const ep_data = get_ep_data(dev, cfg->addr);
231 uint32_t buf_ctrl;
232 size_t len;
233
234 buf_ctrl = read_buf_ctrl_reg(dev, cfg->addr);
235 if (buf_ctrl & USB_BUF_CTRL_AVAIL) {
236 LOG_ERR("ep 0x%02x buffer is used by the controller", cfg->addr);
237 return -EBUSY;
238 }
239
240 len = MIN(cfg->mps, buf->len);
241 memcpy(ep_data->buf, buf->data, len);
242
243 LOG_DBG("Prepare TX ep 0x%02x len %u pid: %u",
244 cfg->addr, len, ep_data->next_pid);
245
246 buf_ctrl = len;
247 buf_ctrl |= ep_data->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
248 buf_ctrl |= USB_BUF_CTRL_FULL;
249 ep_data->next_pid ^= 1U;
250
251 write_buf_ctrl_reg(dev, cfg->addr, buf_ctrl);
252 /*
253 * By default, clk_sys runs at 125MHz, wait 3 nop instructions before
254 * setting the AVAILABLE bit. See 4.1.2.5.1. Concurrent access.
255 */
256 arch_nop();
257 arch_nop();
258 arch_nop();
259 write_buf_ctrl_reg(dev, cfg->addr, buf_ctrl | USB_BUF_CTRL_AVAIL);
260
261 return 0;
262 }
263
rpi_pico_ctrl_feed_dout(const struct device * dev,const size_t length)264 static int rpi_pico_ctrl_feed_dout(const struct device *dev, const size_t length)
265 {
266 struct udc_ep_config *ep_cfg = udc_get_ep_cfg(dev, USB_CONTROL_EP_OUT);
267 struct net_buf *buf;
268
269 buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT, length);
270 if (buf == NULL) {
271 return -ENOMEM;
272 }
273
274 udc_buf_put(ep_cfg, buf);
275
276 return rpi_pico_prep_rx(dev, buf, ep_cfg);
277 }
278
drop_control_transfers(const struct device * dev)279 static void drop_control_transfers(const struct device *dev)
280 {
281 struct net_buf *buf;
282
283 buf = udc_buf_get_all(dev, USB_CONTROL_EP_OUT);
284 if (buf != NULL) {
285 net_buf_unref(buf);
286 }
287
288 buf = udc_buf_get_all(dev, USB_CONTROL_EP_IN);
289 if (buf != NULL) {
290 net_buf_unref(buf);
291 }
292 }
293
rpi_pico_handle_evt_setup(const struct device * dev)294 static int rpi_pico_handle_evt_setup(const struct device *dev)
295 {
296 struct rpi_pico_data *priv = udc_get_private(dev);
297 struct net_buf *buf;
298 int err;
299
300 drop_control_transfers(dev);
301
302 buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT, 8);
303 if (buf == NULL) {
304 udc_submit_event(dev, UDC_EVT_ERROR, -ENOBUFS);
305 return -ENOMEM;
306 }
307
308 net_buf_add_mem(buf, priv->setup, sizeof(priv->setup));
309 udc_ep_buf_set_setup(buf);
310 LOG_HEXDUMP_DBG(buf->data, buf->len, "setup");
311
312 /* Update to next stage of control transfer */
313 udc_ctrl_update_stage(dev, buf);
314
315 if (udc_ctrl_stage_is_data_out(dev)) {
316 /* Allocate and feed buffer for data OUT stage */
317 LOG_DBG("s:%p|feed for -out-", buf);
318
319 err = rpi_pico_ctrl_feed_dout(dev, udc_data_stage_length(buf));
320 if (err != 0) {
321 err = udc_submit_ep_event(dev, buf, err);
322 }
323 } else if (udc_ctrl_stage_is_data_in(dev)) {
324 LOG_DBG("s:%p|feed for -in-status", buf);
325 err = udc_ctrl_submit_s_in_status(dev);
326 } else {
327 LOG_DBG("s:%p|no data", buf);
328 err = udc_ctrl_submit_s_status(dev);
329 }
330
331 return err;
332 }
333
rpi_pico_handle_evt_dout(const struct device * dev,struct udc_ep_config * const cfg)334 static inline int rpi_pico_handle_evt_dout(const struct device *dev,
335 struct udc_ep_config *const cfg)
336 {
337 struct net_buf *buf;
338 int err = 0;
339
340 buf = udc_buf_get(dev, cfg->addr);
341 if (buf == NULL) {
342 LOG_ERR("No buffer for OUT ep 0x%02x", cfg->addr);
343 udc_submit_event(dev, UDC_EVT_ERROR, -ENOBUFS);
344 return -ENODATA;
345 }
346
347 udc_ep_set_busy(dev, cfg->addr, false);
348
349 if (cfg->addr == USB_CONTROL_EP_OUT) {
350 if (udc_ctrl_stage_is_status_out(dev)) {
351 LOG_DBG("dout:%p|status, feed >s", buf);
352
353 /* Status stage finished, notify upper layer */
354 udc_ctrl_submit_status(dev, buf);
355 }
356
357 /* Update to next stage of control transfer */
358 udc_ctrl_update_stage(dev, buf);
359
360 if (udc_ctrl_stage_is_status_in(dev)) {
361 err = udc_ctrl_submit_s_out_status(dev, buf);
362 }
363 } else {
364 err = udc_submit_ep_event(dev, buf, 0);
365 }
366
367 return err;
368 }
369
rpi_pico_handle_evt_din(const struct device * dev,struct udc_ep_config * const cfg)370 static int rpi_pico_handle_evt_din(const struct device *dev,
371 struct udc_ep_config *const cfg)
372 {
373 struct net_buf *buf;
374 int err;
375
376 buf = udc_buf_peek(dev, cfg->addr);
377 if (buf == NULL) {
378 LOG_ERR("No buffer for ep 0x%02x", cfg->addr);
379 udc_submit_event(dev, UDC_EVT_ERROR, -ENOBUFS);
380 return -ENOBUFS;
381 }
382
383 buf = udc_buf_get(dev, cfg->addr);
384 udc_ep_set_busy(dev, cfg->addr, false);
385
386 if (cfg->addr == USB_CONTROL_EP_IN) {
387 if (udc_ctrl_stage_is_status_in(dev) ||
388 udc_ctrl_stage_is_no_data(dev)) {
389 /* Status stage finished, notify upper layer */
390 udc_ctrl_submit_status(dev, buf);
391 }
392
393 /* Update to next stage of control transfer */
394 udc_ctrl_update_stage(dev, buf);
395
396 if (udc_ctrl_stage_is_status_out(dev)) {
397 /* IN transfer finished, submit buffer for status stage */
398 net_buf_unref(buf);
399
400 err = rpi_pico_ctrl_feed_dout(dev, 0);
401 if (err == -ENOMEM) {
402 err = udc_submit_ep_event(dev, buf, err);
403 }
404 }
405
406 return 0;
407 }
408
409 return udc_submit_ep_event(dev, buf, 0);
410 }
411
rpi_pico_handle_xfer_next(const struct device * dev,struct udc_ep_config * const cfg)412 static void rpi_pico_handle_xfer_next(const struct device *dev,
413 struct udc_ep_config *const cfg)
414 {
415 struct net_buf *buf;
416 int err;
417
418 buf = udc_buf_peek(dev, cfg->addr);
419 if (buf == NULL) {
420 return;
421 }
422
423 if (USB_EP_DIR_IS_OUT(cfg->addr)) {
424 err = rpi_pico_prep_rx(dev, buf, cfg);
425 } else {
426 err = rpi_pico_prep_tx(dev, buf, cfg);
427 }
428
429 if (err != 0) {
430 udc_submit_ep_event(dev, buf, -ECONNREFUSED);
431 } else {
432 udc_ep_set_busy(dev, cfg->addr, true);
433 }
434 }
435
rpi_pico_thread_handler(void * const arg)436 static ALWAYS_INLINE void rpi_pico_thread_handler(void *const arg)
437 {
438 const struct device *dev = (const struct device *)arg;
439 struct udc_ep_config *ep_cfg;
440 struct rpi_pico_event evt;
441
442 k_msgq_get(&drv_msgq, &evt, K_FOREVER);
443 ep_cfg = udc_get_ep_cfg(dev, evt.ep);
444
445 switch (evt.type) {
446 case RPI_PICO_EVT_XFER:
447 LOG_DBG("New transfer in the queue");
448 break;
449 case RPI_PICO_EVT_SETUP:
450 LOG_DBG("SETUP event");
451 rpi_pico_handle_evt_setup(dev);
452 break;
453 case RPI_PICO_EVT_DOUT:
454 LOG_DBG("DOUT event ep 0x%02x", ep_cfg->addr);
455 rpi_pico_handle_evt_dout(dev, ep_cfg);
456 break;
457 case RPI_PICO_EVT_DIN:
458 LOG_DBG("DIN event");
459 rpi_pico_handle_evt_din(dev, ep_cfg);
460 break;
461 }
462
463 if (ep_cfg->addr != USB_CONTROL_EP_OUT && !udc_ep_is_busy(dev, ep_cfg->addr)) {
464 rpi_pico_handle_xfer_next(dev, ep_cfg);
465 }
466 }
467
rpi_pico_handle_setup(const struct device * dev)468 static void rpi_pico_handle_setup(const struct device *dev)
469 {
470 const struct rpi_pico_config *config = dev->config;
471 struct rpi_pico_data *priv = udc_get_private(dev);
472 usb_device_dpram_t *dpram = config->dpram;
473 struct rpi_pico_event evt = {
474 .type = RPI_PICO_EVT_SETUP,
475 .ep = USB_CONTROL_EP_OUT,
476 };
477
478 /*
479 * Host may issue a new setup packet even if the previous control transfer
480 * did not complete. Cancel any active transaction.
481 */
482 rpi_pico_ep_cancel(dev, USB_CONTROL_EP_IN);
483 rpi_pico_ep_cancel(dev, USB_CONTROL_EP_OUT);
484
485 sys_put_le32(sys_read32((uintptr_t)&dpram->setup_packet[0]), &priv->setup[0]);
486 sys_put_le32(sys_read32((uintptr_t)&dpram->setup_packet[4]), &priv->setup[4]);
487
488 /* Set DATA1 PID for the next (data or status) stage */
489 get_ep_data(dev, USB_CONTROL_EP_IN)->next_pid = 1;
490 get_ep_data(dev, USB_CONTROL_EP_OUT)->next_pid = 1;
491
492 k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
493 }
494
rpi_pico_handle_buff_status_in(const struct device * dev,const uint8_t ep)495 static void rpi_pico_handle_buff_status_in(const struct device *dev, const uint8_t ep)
496 {
497 struct udc_ep_config *ep_cfg = udc_get_ep_cfg(dev, ep);
498 struct rpi_pico_event evt = {
499 .ep = ep,
500 .type = RPI_PICO_EVT_DIN,
501 };
502 __maybe_unused int err;
503 struct net_buf *buf;
504 size_t len;
505
506 buf = udc_buf_peek(dev, ep);
507 if (buf == NULL) {
508 LOG_ERR("No buffer for ep 0x%02x", ep);
509 udc_submit_event(dev, UDC_EVT_ERROR, -ENOBUFS);
510 return;
511 }
512
513 len = read_buf_ctrl_reg(dev, ep) & USB_BUF_CTRL_LEN_MASK;
514 net_buf_pull(buf, len);
515
516 if (buf->len) {
517 err = rpi_pico_prep_tx(dev, buf, ep_cfg);
518 __ASSERT(err == 0, "Failed to start new IN transaction");
519 } else {
520 if (udc_ep_buf_has_zlp(buf)) {
521 err = rpi_pico_prep_tx(dev, buf, ep_cfg);
522 __ASSERT(err == 0, "Failed to start new IN transaction");
523 udc_ep_buf_clear_zlp(buf);
524 } else {
525 k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
526 }
527 }
528 }
529
rpi_pico_handle_buff_status_out(const struct device * dev,const uint8_t ep)530 static void rpi_pico_handle_buff_status_out(const struct device *dev, const uint8_t ep)
531 {
532 struct rpi_pico_ep_data *ep_data = get_ep_data(dev, ep);
533 struct udc_ep_config *ep_cfg = udc_get_ep_cfg(dev, ep);
534 struct rpi_pico_event evt = {
535 .ep = ep,
536 .type = RPI_PICO_EVT_DOUT,
537 };
538 struct net_buf *buf;
539 size_t len;
540
541 buf = udc_buf_peek(dev, ep);
542 if (buf == NULL) {
543 LOG_ERR("No buffer for ep 0x%02x", ep);
544 udc_submit_event(dev, UDC_EVT_ERROR, -ENOBUFS);
545 return;
546 }
547
548 len = read_buf_ctrl_reg(dev, ep) & USB_BUF_CTRL_LEN_MASK;
549 net_buf_add_mem(buf, ep_data->buf, MIN(len, net_buf_tailroom(buf)));
550
551 if (net_buf_tailroom(buf) >= udc_mps_ep_size(ep_cfg) &&
552 len == udc_mps_ep_size(ep_cfg)) {
553 __unused int err;
554
555 err = rpi_pico_prep_rx(dev, buf, ep_cfg);
556 __ASSERT(err == 0, "Failed to start new OUT transaction");
557 } else {
558 k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
559 }
560 }
561
rpi_pico_handle_buff_status(const struct device * dev)562 static void rpi_pico_handle_buff_status(const struct device *dev)
563 {
564 const struct rpi_pico_config *config = dev->config;
565 usb_hw_t *base = config->base;
566 uint32_t buf_status;
567 uint8_t ep;
568
569 buf_status = sys_read32((mm_reg_t)&base->buf_status);
570
571 for (unsigned int i = 0; buf_status && i < USB_NUM_ENDPOINTS * 2; i++) {
572 if (!(buf_status & BIT(i))) {
573 continue;
574 }
575
576 /* Odd bits in the register correspond to OUT endpoints */
577 if (i & 1U) {
578 ep = USB_EP_DIR_OUT | (i >> 1U);
579 rpi_pico_handle_buff_status_out(dev, ep);
580 } else {
581 ep = USB_EP_DIR_IN | (i >> 1U);
582 rpi_pico_handle_buff_status_in(dev, ep);
583 }
584
585 rpi_pico_bit_clr((mm_reg_t)&base->buf_status, BIT(i));
586 buf_status &= ~BIT(i);
587 }
588 }
589
rpi_pico_isr_handler(const struct device * dev)590 static void rpi_pico_isr_handler(const struct device *dev)
591 {
592 const struct rpi_pico_config *config = dev->config;
593 struct rpi_pico_data *priv = udc_get_private(dev);
594 usb_hw_t *base = config->base;
595 uint32_t status = base->ints;
596 uint32_t handled = 0;
597
598 if (status & USB_INTS_DEV_SOF_BITS) {
599 handled |= USB_INTS_DEV_SOF_BITS;
600 sys_read32((mm_reg_t)&base->sof_rd);
601 }
602
603 if (status & USB_INTS_DEV_CONN_DIS_BITS) {
604 uint32_t sie_status;
605
606 handled |= USB_INTS_DEV_CONN_DIS_BITS;
607 sie_status_clr(dev, USB_SIE_STATUS_CONNECTED_BITS);
608
609 sie_status = sys_read32((mm_reg_t)&base->sie_status);
610 if (sie_status & USB_SIE_STATUS_CONNECTED_BITS) {
611 udc_submit_event(dev, UDC_EVT_VBUS_READY, 0);
612 } else {
613 udc_submit_event(dev, UDC_EVT_VBUS_REMOVED, 0);
614 }
615 }
616
617 if ((status & (USB_INTS_BUFF_STATUS_BITS | USB_INTS_SETUP_REQ_BITS)) &&
618 priv->rwu_pending) {
619 /* The rpi pico USB device does not appear to be sending
620 * USB_INTR_DEV_RESUME_FROM_HOST interrupts when the resume is
621 * a result of a remote wakeup request sent by us.
622 * This will simulate a resume event if bus activity is observed
623 */
624
625 priv->rwu_pending = false;
626 udc_submit_event(dev, UDC_EVT_RESUME, 0);
627 }
628
629 if (status & USB_INTR_DEV_RESUME_FROM_HOST_BITS) {
630 handled |= USB_INTR_DEV_RESUME_FROM_HOST_BITS;
631 sie_status_clr(dev, USB_SIE_STATUS_RESUME_BITS);
632
633 priv->rwu_pending = false;
634 udc_submit_event(dev, UDC_EVT_RESUME, 0);
635 }
636
637 if (status & USB_INTS_DEV_SUSPEND_BITS) {
638 handled |= USB_INTS_DEV_SUSPEND_BITS;
639 sie_status_clr(dev, USB_SIE_STATUS_SUSPENDED_BITS);
640
641 udc_submit_event(dev, UDC_EVT_SUSPEND, 0);
642 }
643
644 if (status & USB_INTS_BUS_RESET_BITS) {
645 handled |= USB_INTS_BUS_RESET_BITS;
646 sie_status_clr(dev, USB_SIE_STATUS_BUS_RESET_BITS);
647
648 sys_write32(0, (mm_reg_t)&base->dev_addr_ctrl);
649 udc_submit_event(dev, UDC_EVT_RESET, 0);
650 }
651
652 if (status & USB_INTS_ERROR_DATA_SEQ_BITS) {
653 handled |= USB_INTS_ERROR_DATA_SEQ_BITS;
654 sie_status_clr(dev, USB_SIE_STATUS_DATA_SEQ_ERROR_BITS);
655
656 LOG_ERR("Data Sequence Error");
657 udc_submit_event(dev, UDC_EVT_ERROR, -EINVAL);
658 }
659
660 if (status & USB_INTS_ERROR_RX_TIMEOUT_BITS) {
661 handled |= USB_INTS_ERROR_RX_TIMEOUT_BITS;
662 sie_status_clr(dev, USB_SIE_STATUS_RX_TIMEOUT_BITS);
663
664 LOG_ERR("RX timeout");
665 udc_submit_event(dev, UDC_EVT_ERROR, -EINVAL);
666 }
667
668 if (status & USB_INTS_ERROR_RX_OVERFLOW_BITS) {
669 sie_status_clr(dev, USB_SIE_STATUS_RX_OVERFLOW_BITS);
670 handled |= USB_INTS_ERROR_RX_OVERFLOW_BITS;
671
672 LOG_ERR("RX overflow");
673 udc_submit_event(dev, UDC_EVT_ERROR, -EINVAL);
674 }
675
676 if (status & USB_INTS_ERROR_BIT_STUFF_BITS) {
677 handled |= USB_INTS_ERROR_BIT_STUFF_BITS;
678 sie_status_clr(dev, USB_SIE_STATUS_BIT_STUFF_ERROR_BITS);
679
680 LOG_ERR("Bit Stuff Error");
681 udc_submit_event(dev, UDC_EVT_ERROR, -EINVAL);
682 }
683
684 if (status & USB_INTS_ERROR_CRC_BITS) {
685 handled |= USB_INTS_ERROR_CRC_BITS;
686 sie_status_clr(dev, USB_SIE_STATUS_CRC_ERROR_BITS);
687
688 LOG_ERR("CRC Error");
689 udc_submit_event(dev, UDC_EVT_ERROR, -EINVAL);
690 }
691
692 /*
693 * Here both interrupt flags BUF_STATUS and SETUP_REQ may be set at
694 * the same time, e.g. because of the interrupt latency. Check
695 * BUF_STATUS interrupt first to get the notifications in the right
696 * order.
697 */
698 if (status & USB_INTS_BUFF_STATUS_BITS) {
699 handled |= USB_INTS_BUFF_STATUS_BITS;
700 rpi_pico_handle_buff_status(dev);
701 }
702
703 if (status & USB_INTS_SETUP_REQ_BITS) {
704 handled |= USB_INTS_SETUP_REQ_BITS;
705 sie_status_clr(dev, USB_SIE_STATUS_SETUP_REC_BITS);
706
707 rpi_pico_handle_setup(dev);
708 }
709
710 if (status ^ handled) {
711 LOG_ERR("Unhandled IRQ: 0x%x", status ^ handled);
712 }
713 }
714
udc_rpi_pico_ep_enqueue(const struct device * dev,struct udc_ep_config * const cfg,struct net_buf * buf)715 static int udc_rpi_pico_ep_enqueue(const struct device *dev,
716 struct udc_ep_config *const cfg,
717 struct net_buf *buf)
718 {
719 struct rpi_pico_event evt = {
720 .ep = cfg->addr,
721 .type = RPI_PICO_EVT_XFER,
722 };
723
724 udc_buf_put(cfg, buf);
725
726 if (!cfg->stat.halted) {
727 k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
728 }
729
730 return 0;
731 }
732
udc_rpi_pico_ep_dequeue(const struct device * dev,struct udc_ep_config * const cfg)733 static int udc_rpi_pico_ep_dequeue(const struct device *dev,
734 struct udc_ep_config *const cfg)
735 {
736 unsigned int lock_key;
737 struct net_buf *buf;
738
739 lock_key = irq_lock();
740
741 rpi_pico_ep_cancel(dev, cfg->addr);
742 buf = udc_buf_get_all(dev, cfg->addr);
743 if (buf) {
744 udc_submit_ep_event(dev, buf, -ECONNABORTED);
745 }
746
747 irq_unlock(lock_key);
748
749 return 0;
750 }
751
udc_rpi_pico_ep_enable(const struct device * dev,struct udc_ep_config * const cfg)752 static int udc_rpi_pico_ep_enable(const struct device *dev,
753 struct udc_ep_config *const cfg)
754 {
755 struct rpi_pico_ep_data *const ep_data = get_ep_data(dev, cfg->addr);
756 const struct rpi_pico_config *config = dev->config;
757 uint8_t type = cfg->attributes & USB_EP_TRANSFER_TYPE_MASK;
758 usb_device_dpram_t *dpram = config->dpram;
759 int err;
760
761 write_buf_ctrl_reg(dev, cfg->addr, USB_BUF_CTRL_DATA0_PID);
762 ep_data->next_pid = 0;
763
764 if (USB_EP_GET_IDX(cfg->addr) != 0) {
765 uint32_t ep_ctrl = EP_CTRL_ENABLE_BITS |
766 EP_CTRL_INTERRUPT_PER_BUFFER |
767 (type << EP_CTRL_BUFFER_TYPE_LSB);
768 size_t blocks = DIV_ROUND_UP(cfg->mps, 64U);
769
770 err = sys_mem_blocks_alloc(config->mem_block, blocks, &ep_data->buf);
771 if (err != 0) {
772 LOG_ERR("Failed to allocate %zu memory blocks for ep 0x%02x",
773 cfg->addr, blocks);
774 return err;
775 }
776
777 ep_ctrl |= (uintptr_t)ep_data->buf & 0xFFFFUL;
778 write_ep_ctrl_reg(dev, cfg->addr, ep_ctrl);
779 } else {
780 ep_data->buf = dpram->ep0_buf_a;
781 }
782
783 LOG_DBG("Enable ep 0x%02x", cfg->addr);
784
785 return 0;
786 }
787
udc_rpi_pico_ep_disable(const struct device * dev,struct udc_ep_config * const cfg)788 static int udc_rpi_pico_ep_disable(const struct device *dev,
789 struct udc_ep_config *const cfg)
790 {
791 struct rpi_pico_ep_data *const ep_data = get_ep_data(dev, cfg->addr);
792 const struct rpi_pico_config *config = dev->config;
793 int err;
794
795 rpi_pico_ep_cancel(dev, cfg->addr);
796
797 if (USB_EP_GET_IDX(cfg->addr) != 0) {
798 size_t blocks = DIV_ROUND_UP(cfg->mps, 64U);
799
800 write_ep_ctrl_reg(dev, cfg->addr, 0UL);
801 err = sys_mem_blocks_free(config->mem_block, blocks, &ep_data->buf);
802 if (err != 0) {
803 LOG_ERR("Failed to free memory blocks");
804 return err;
805 }
806 }
807
808 LOG_DBG("Disable ep 0x%02x", cfg->addr);
809
810 return 0;
811 }
812
udc_rpi_pico_ep_set_halt(const struct device * dev,struct udc_ep_config * const cfg)813 static int udc_rpi_pico_ep_set_halt(const struct device *dev,
814 struct udc_ep_config *const cfg)
815 {
816 const struct rpi_pico_config *config = dev->config;
817 mem_addr_t buf_ctrl_reg = get_buf_ctrl_reg(dev, cfg->addr);
818 usb_hw_t *base = config->base;
819
820 if (USB_EP_GET_IDX(cfg->addr) == 0) {
821 uint32_t bit = USB_EP_DIR_IS_OUT(cfg->addr) ?
822 USB_EP_STALL_ARM_EP0_OUT_BITS : USB_EP_STALL_ARM_EP0_IN_BITS;
823
824 rpi_pico_bit_set((mm_reg_t)&base->ep_stall_arm, bit);
825 }
826
827 rpi_pico_bit_set(buf_ctrl_reg, USB_BUF_CTRL_STALL);
828
829 LOG_INF("Set halt ep 0x%02x", cfg->addr);
830 if (USB_EP_GET_IDX(cfg->addr) != 0) {
831 cfg->stat.halted = true;
832 }
833
834 return 0;
835 }
836
udc_rpi_pico_ep_clear_halt(const struct device * dev,struct udc_ep_config * const cfg)837 static int udc_rpi_pico_ep_clear_halt(const struct device *dev,
838 struct udc_ep_config *const cfg)
839 {
840 struct rpi_pico_ep_data *const ep_data = get_ep_data(dev, cfg->addr);
841 mem_addr_t buf_ctrl_reg = get_buf_ctrl_reg(dev, cfg->addr);
842 struct rpi_pico_event evt = {
843 .ep = cfg->addr,
844 .type = RPI_PICO_EVT_XFER,
845 };
846
847 if (USB_EP_GET_IDX(cfg->addr) != 0) {
848 ep_data->next_pid = 0;
849 rpi_pico_bit_clr(buf_ctrl_reg, USB_BUF_CTRL_DATA1_PID);
850 /*
851 * By default, clk_sys runs at 125MHz, wait 3 nop instructions
852 * before clearing the CTRL_STALL bit. See 4.1.2.5.4.
853 */
854 arch_nop();
855 arch_nop();
856 arch_nop();
857 rpi_pico_bit_clr(buf_ctrl_reg, USB_BUF_CTRL_STALL);
858
859 if (udc_buf_peek(dev, cfg->addr)) {
860 k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
861 }
862 }
863
864 cfg->stat.halted = false;
865 LOG_INF("Clear halt ep 0x%02x buf_ctrl 0x%08x",
866 cfg->addr, sys_read32(buf_ctrl_reg));
867
868 return 0;
869 }
870
udc_rpi_pico_set_address(const struct device * dev,const uint8_t addr)871 static int udc_rpi_pico_set_address(const struct device *dev, const uint8_t addr)
872 {
873 const struct rpi_pico_config *config = dev->config;
874 usb_hw_t *base = config->base;
875
876 sys_write32(addr, (mm_reg_t)&base->dev_addr_ctrl);
877 LOG_DBG("Set new address %u for %s", addr, dev->name);
878
879 return 0;
880 }
881
udc_rpi_pico_host_wakeup(const struct device * dev)882 static int udc_rpi_pico_host_wakeup(const struct device *dev)
883 {
884 const struct rpi_pico_config *config = dev->config;
885 struct rpi_pico_data *priv = udc_get_private(dev);
886 usb_hw_t *base = config->base;
887
888 rpi_pico_bit_set((mm_reg_t)&base->sie_ctrl, USB_SIE_CTRL_RESUME_BITS);
889 priv->rwu_pending = true;
890
891 LOG_DBG("Remote wakeup from %s", dev->name);
892
893 return 0;
894 }
895
udc_rpi_pico_enable(const struct device * dev)896 static int udc_rpi_pico_enable(const struct device *dev)
897 {
898 const struct rpi_pico_config *config = dev->config;
899 usb_device_dpram_t *dpram = config->dpram;
900 usb_hw_t *base = config->base;
901
902 /* Reset USB controller */
903 reset_block(RESETS_RESET_USBCTRL_BITS);
904 unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
905
906 /* Clear registers and DPRAM */
907 memset(base, 0, sizeof(usb_hw_t));
908 memset(dpram, 0, sizeof(usb_device_dpram_t));
909
910 /* Connect USB controller to the onboard PHY */
911 sys_write32(USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS,
912 (mm_reg_t)&base->muxing);
913
914 /* Force VBUS detect so the device thinks it is plugged into a host */
915 sys_write32(USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS,
916 (mm_reg_t)&base->pwr);
917
918 /* Enable an interrupt per EP0 transaction */
919 sys_write32(USB_SIE_CTRL_EP0_INT_1BUF_BITS, (mm_reg_t)&base->sie_ctrl);
920
921 /* Enable interrupts */
922 sys_write32(USB_INTE_DEV_SOF_BITS |
923 USB_INTE_SETUP_REQ_BITS |
924 USB_INTE_DEV_RESUME_FROM_HOST_BITS |
925 USB_INTE_DEV_SUSPEND_BITS |
926 USB_INTE_DEV_CONN_DIS_BITS |
927 USB_INTE_BUS_RESET_BITS |
928 USB_INTE_VBUS_DETECT_BITS |
929 USB_INTE_ERROR_CRC_BITS |
930 USB_INTE_ERROR_BIT_STUFF_BITS |
931 USB_INTE_ERROR_RX_OVERFLOW_BITS |
932 USB_INTE_ERROR_RX_TIMEOUT_BITS |
933 USB_INTE_ERROR_DATA_SEQ_BITS |
934 USB_INTE_BUFF_STATUS_BITS,
935 (mm_reg_t)&base->inte);
936
937 /* Present full speed device by enabling pull up on DP */
938 rpi_pico_bit_set((mm_reg_t)&base->sie_ctrl, USB_SIE_CTRL_PULLUP_EN_BITS);
939
940 /* Enable the USB controller in device mode. */
941 sys_write32(USB_MAIN_CTRL_CONTROLLER_EN_BITS, (mm_reg_t)&base->main_ctrl);
942
943 config->irq_enable_func(dev);
944
945 LOG_DBG("Enable device %s %p", dev->name, (void *)base);
946
947 return 0;
948 }
949
udc_rpi_pico_disable(const struct device * dev)950 static int udc_rpi_pico_disable(const struct device *dev)
951 {
952 const struct rpi_pico_config *config = dev->config;
953
954 config->irq_disable_func(dev);
955 LOG_DBG("Enable device %p", dev);
956
957 return 0;
958 }
959
udc_rpi_pico_init(const struct device * dev)960 static int udc_rpi_pico_init(const struct device *dev)
961 {
962 const struct rpi_pico_config *config = dev->config;
963
964 if (udc_ep_enable_internal(dev, USB_CONTROL_EP_OUT,
965 USB_EP_TYPE_CONTROL, 64, 0)) {
966 LOG_ERR("Failed to enable control endpoint");
967 return -EIO;
968 }
969
970 if (udc_ep_enable_internal(dev, USB_CONTROL_EP_IN,
971 USB_EP_TYPE_CONTROL, 64, 0)) {
972 LOG_ERR("Failed to enable control endpoint");
973 return -EIO;
974 }
975
976 return clock_control_on(config->clk_dev, config->clk_sys);
977 }
978
udc_rpi_pico_shutdown(const struct device * dev)979 static int udc_rpi_pico_shutdown(const struct device *dev)
980 {
981 const struct rpi_pico_config *config = dev->config;
982
983 if (udc_ep_disable_internal(dev, USB_CONTROL_EP_OUT)) {
984 LOG_ERR("Failed to disable control endpoint");
985 return -EIO;
986 }
987
988 if (udc_ep_disable_internal(dev, USB_CONTROL_EP_IN)) {
989 LOG_ERR("Failed to disable control endpoint");
990 return -EIO;
991 }
992
993 return clock_control_off(config->clk_dev, config->clk_sys);
994 }
995
udc_rpi_pico_driver_preinit(const struct device * dev)996 static int udc_rpi_pico_driver_preinit(const struct device *dev)
997 {
998 const struct rpi_pico_config *config = dev->config;
999 struct udc_data *data = dev->data;
1000 uint16_t mps = 1023;
1001 int err;
1002
1003 k_mutex_init(&data->mutex);
1004
1005 data->caps.rwup = true;
1006 data->caps.mps0 = UDC_MPS0_64;
1007
1008 for (int i = 0; i < config->num_of_eps; i++) {
1009 config->ep_cfg_out[i].caps.out = 1;
1010 if (i == 0) {
1011 config->ep_cfg_out[i].caps.control = 1;
1012 config->ep_cfg_out[i].caps.mps = 64;
1013 } else {
1014 config->ep_cfg_out[i].caps.bulk = 1;
1015 config->ep_cfg_out[i].caps.interrupt = 1;
1016 config->ep_cfg_out[i].caps.iso = 1;
1017 config->ep_cfg_out[i].caps.mps = mps;
1018 }
1019
1020 config->ep_cfg_out[i].addr = USB_EP_DIR_OUT | i;
1021 err = udc_register_ep(dev, &config->ep_cfg_out[i]);
1022 if (err != 0) {
1023 LOG_ERR("Failed to register endpoint");
1024 return err;
1025 }
1026 }
1027
1028 for (int i = 0; i < config->num_of_eps; i++) {
1029 config->ep_cfg_in[i].caps.in = 1;
1030 if (i == 0) {
1031 config->ep_cfg_in[i].caps.control = 1;
1032 config->ep_cfg_in[i].caps.mps = 64;
1033 } else {
1034 config->ep_cfg_in[i].caps.bulk = 1;
1035 config->ep_cfg_in[i].caps.interrupt = 1;
1036 config->ep_cfg_in[i].caps.iso = 1;
1037 config->ep_cfg_in[i].caps.mps = mps;
1038 }
1039
1040 config->ep_cfg_in[i].addr = USB_EP_DIR_IN | i;
1041 err = udc_register_ep(dev, &config->ep_cfg_in[i]);
1042 if (err != 0) {
1043 LOG_ERR("Failed to register endpoint");
1044 return err;
1045 }
1046 }
1047
1048 config->make_thread(dev);
1049
1050 return 0;
1051 }
1052
udc_rpi_pico_lock(const struct device * dev)1053 static int udc_rpi_pico_lock(const struct device *dev)
1054 {
1055 return udc_lock_internal(dev, K_FOREVER);
1056 }
1057
udc_rpi_pico_unlock(const struct device * dev)1058 static int udc_rpi_pico_unlock(const struct device *dev)
1059 {
1060 return udc_unlock_internal(dev);
1061 }
1062
1063 static const struct udc_api udc_rpi_pico_api = {
1064 .lock = udc_rpi_pico_lock,
1065 .unlock = udc_rpi_pico_unlock,
1066 .init = udc_rpi_pico_init,
1067 .enable = udc_rpi_pico_enable,
1068 .disable = udc_rpi_pico_disable,
1069 .shutdown = udc_rpi_pico_shutdown,
1070 .set_address = udc_rpi_pico_set_address,
1071 .host_wakeup = udc_rpi_pico_host_wakeup,
1072 .ep_enable = udc_rpi_pico_ep_enable,
1073 .ep_disable = udc_rpi_pico_ep_disable,
1074 .ep_set_halt = udc_rpi_pico_ep_set_halt,
1075 .ep_clear_halt = udc_rpi_pico_ep_clear_halt,
1076 .ep_enqueue = udc_rpi_pico_ep_enqueue,
1077 .ep_dequeue = udc_rpi_pico_ep_dequeue,
1078 };
1079
1080 #define DT_DRV_COMPAT raspberrypi_pico_usbd
1081
1082 #define UDC_RPI_PICO_DEVICE_DEFINE(n) \
1083 K_THREAD_STACK_DEFINE(udc_rpi_pico_stack_##n, CONFIG_UDC_RPI_PICO_STACK_SIZE); \
1084 \
1085 SYS_MEM_BLOCKS_DEFINE_STATIC_WITH_EXT_BUF(rpi_pico_mb_##n, \
1086 64U, 58U, \
1087 usb_dpram->epx_data) \
1088 \
1089 static void udc_rpi_pico_thread_##n(void *dev, void *arg1, void *arg2) \
1090 { \
1091 while (true) { \
1092 rpi_pico_thread_handler(dev); \
1093 } \
1094 } \
1095 \
1096 static void udc_rpi_pico_make_thread_##n(const struct device *dev) \
1097 { \
1098 struct rpi_pico_data *priv = udc_get_private(dev); \
1099 \
1100 k_thread_create(&priv->thread_data, \
1101 udc_rpi_pico_stack_##n, \
1102 K_THREAD_STACK_SIZEOF(udc_rpi_pico_stack_##n), \
1103 udc_rpi_pico_thread_##n, \
1104 (void *)dev, NULL, NULL, \
1105 K_PRIO_COOP(CONFIG_UDC_RPI_PICO_THREAD_PRIORITY), \
1106 K_ESSENTIAL, \
1107 K_NO_WAIT); \
1108 k_thread_name_set(&priv->thread_data, dev->name); \
1109 } \
1110 \
1111 static void udc_rpi_pico_irq_enable_func_##n(const struct device *dev) \
1112 { \
1113 IRQ_CONNECT(DT_INST_IRQN(n), \
1114 DT_INST_IRQ(n, priority), \
1115 rpi_pico_isr_handler, \
1116 DEVICE_DT_INST_GET(n), \
1117 0); \
1118 \
1119 irq_enable(DT_INST_IRQN(n)); \
1120 } \
1121 \
1122 static void udc_rpi_pico_irq_disable_func_##n(const struct device *dev) \
1123 { \
1124 irq_disable(DT_INST_IRQN(n)); \
1125 } \
1126 \
1127 static struct udc_ep_config ep_cfg_out[USB_NUM_ENDPOINTS]; \
1128 static struct udc_ep_config ep_cfg_in[USB_NUM_ENDPOINTS]; \
1129 \
1130 static const struct rpi_pico_config rpi_pico_config_##n = { \
1131 .base = (usb_hw_t *)DT_INST_REG_ADDR(n), \
1132 .dpram = (usb_device_dpram_t *)USBCTRL_DPRAM_BASE, \
1133 .mem_block = &rpi_pico_mb_##n, \
1134 .num_of_eps = DT_INST_PROP(n, num_bidir_endpoints), \
1135 .ep_cfg_in = ep_cfg_out, \
1136 .ep_cfg_out = ep_cfg_in, \
1137 .make_thread = udc_rpi_pico_make_thread_##n, \
1138 .irq_enable_func = udc_rpi_pico_irq_enable_func_##n, \
1139 .irq_disable_func = udc_rpi_pico_irq_disable_func_##n, \
1140 .clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
1141 .clk_sys = (void *)DT_INST_PHA_BY_IDX(n, clocks, 0, clk_id), \
1142 }; \
1143 \
1144 static struct rpi_pico_data udc_priv_##n = { \
1145 }; \
1146 \
1147 static struct udc_data udc_data_##n = { \
1148 .mutex = Z_MUTEX_INITIALIZER(udc_data_##n.mutex), \
1149 .priv = &udc_priv_##n, \
1150 }; \
1151 \
1152 DEVICE_DT_INST_DEFINE(n, udc_rpi_pico_driver_preinit, NULL, \
1153 &udc_data_##n, &rpi_pico_config_##n, \
1154 POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
1155 &udc_rpi_pico_api);
1156
1157 DT_INST_FOREACH_STATUS_OKAY(UDC_RPI_PICO_DEVICE_DEFINE)
1158
