275 	uint32_t *rate, uint32_t slow_clock, uint32_t sysclk, uint32_t clk_sys)  in get_apb0_periph_clkrate()  argument
300 	/* CLK_SYS peripherals: SYSCFG */  in get_apb0_periph_clkrate()
302 		*rate = clk_sys;  in get_apb0_periph_clkrate()
316 	uint32_t *rate, uint32_t clk_sys)  in get_apb1_periph_clkrate()  argument
321 		*rate = clk_sys;  in get_apb1_periph_clkrate()
407 	uint32_t sysclk, slow_clock, clk_sys;  in stm32_clock_control_get_subsys_rate()  local
423 	 * setting CLKSYSDIV = 1 results in 32MHz CLK_SYS, regardless of SYSCLK being 32 or 64MHZ.  in stm32_clock_control_get_subsys_rate()
431 	/* Obtain CLK_SYS (AHB0) frequency by using the CLKSYSDIV prescaler value.  in stm32_clock_control_get_subsys_rate()
442 	clk_sys = CLOCK_FREQ_64MHZ >> LL_RCC_GetRC64MPLLPrescaler();  in stm32_clock_control_get_subsys_rate()
464 	/* All peripherals on AHB0 are clocked by CLK_SYS. */  in stm32_clock_control_get_subsys_rate()
465 		*rate = clk_sys;  in stm32_clock_control_get_subsys_rate()
469 					       sysclk, clk_sys);  in stm32_clock_control_get_subsys_rate()
471 		return get_apb1_periph_clkrate(pclken, rate, clk_sys);  in stm32_clock_control_get_subsys_rate()
623 	 * off RC64MPLL because CLK_SYS must be at least 1MHz  in kconfig_to_ll_prescaler()
712 	/* Set flash latency according to target CLK_SYS frequency:  in stm32_clock_control_init()
713 	 *  - 1 wait state when CLK_SYS > 32MHz (i.e., 64MHz configuration)  in stm32_clock_control_init()
714 	 *  - 0 wait states otherwise (CLK_SYS <= 32MHz)  in stm32_clock_control_init()
757 	/* Set CLK_SYS prescaler */  in stm32_clock_control_init()