| /Zephyr-latest/dts/bindings/gpio/ |
| D | sparkfun,micromod-gpio.yaml | 7 The micromod standard leverages the M.2 connector with 76 pins for
12 * An 6-pin Power Supply header. No pins on this header are exposed
15 * 2 UART buses. First with RTS and CTS pins, while the 2nd with only
17 * 2 i2c buses. Only the corresponding interrupt pin is exposed by
19 * 2 SPI buses not exposed by this binding. Only SPI CS control pin
22 * 2 analog pins (A0 and A1).
23 * 2 digital pins (D0 and D1).
29 - 00 -> A0 PIN 34
30 - 01 -> A1 PIN 38
31 - 02 -> D0 PIN 10
[all …]
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| D | quicklogic,eos-s3-gpio.yaml | 12 const: 2
14 pin-secondary-config:
19 a primary(0) or a secondary(1) pin. EOS S3 supports up to 8 GPIOs
24 "2 : 11 / 28"
30 E.g. configuring GPIO 2 as secondary results in controlling pin 28,
31 to do so set the bit on the 2nd index of this property
32 "pin-secondary-config = <0x04>;"
35 - pin
|
| D | atmel,sam0-gpio.yaml | 12 const: 2
14 "#atmel,pin-cells":
17 const: 2
21 - pin
24 atmel,pin-cells:
25 - pin
|
| D | ambiq,gpio.yaml | 5 Ambiq GPIO provides the GPIO pin mapping for GPIO child nodes.
9 This binding provides a pin mapping to solve the limitation of the maximum
30 #gpio-cells = <2>;
38 #gpio-cells = <2>;
47 #gpio-cells = <2>;
56 #gpio-cells = <2>;
65 #gpio-cells = <2>;
76 address offset. The register address of pin described in gpio-cells can be
77 obtained by: base address + child address offset + (pin << 2). For example:
78 the address of pin 20 of gpio32_63@80 node is (0x40010000 + 0x80 + (20 << 2))
[all …]
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| /Zephyr-latest/samples/drivers/clock_control_xec/ |
| D | README.rst | 20 GPIO221 alternate function 1 is 32KHZ_OUT and can be monitored on Assembly 6915 JP7 pin 5.
25 JP1 pin 2 to GND (ground MEC172x XTAL1 pin)
31 Jumper on JP1 1-2 connect crystal Y1 pin 1 to MEC172x XTAL1
32 Jumper on JP2 2-3 connect crystal Y1 pin 2 to MEC172x XTAL2
42 JP1 pin 2 to GND (ground MEC172x XTAL1 pin)
43 Jumper on JP2 1-2 connect external 32KHz signal to XTAL2
48 XTAL2_32KHZ_IN signal routed to XTAL2 MEC172x pin on Assembly 6915
50 External single-ended 32KHz waveform to MEC172x 32KHZ_IN pin
53 JP1 pin 2 to GND (ground MEC172x XTAL1 pin)
58 Jumper on JP121 pins 1-2 connect U15 32KHz output to
[all …]
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | ambiq,apollo4-pinctrl.yaml | 5 The Ambiq Apollo4 pin controller is a node responsible for controlling
6 pin function selection and pin properties, such as routing a UART0 TX
7 to pin 60 and enabling the pullup resistor on that pin.
16 All device pin configurations should be placed in child nodes of the
38 The 'uart0_default' child node encodes the pin configurations for a
42 As shown, pin configurations are organized in groups within each child node.
43 Each group can specify a list of pin function selections in the 'pinmux'
46 A group can also specify shared pin properties common to all the specified
47 pins, such as the 'input-enable' property in group 2.
75 pin number and the alternative function of the pin.
[all …]
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| D | adi,max32-pinctrl.yaml | 5 MAX32 Pin controller Node
8 Note: `bias-disable` are default pin configurations.
41 Integer array, represents gpio pin number and mux setting.
42 These defines are calculated as: (pin<<8 | port<<4 | function<<0)
45 - pin: The pin offset within the port (0, 1, 2, ...)
49 * 2 : Alternate Function 2
52 In case selected pin function is GPIO, pin is statically configured as
55 to the pin configuration.
65 P0.9 set as alernate function 2
77 GPIO Supply Voltage Select, Selects the voltage rail used for the pin.
[all …]
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| D | raspberrypi,pico-pinctrl.yaml | 6 The RPi Pico pin controller is a node responsible for controlling
7 pin function selection and pin properties, such as routing a UART0 Rx
8 to pin 1 and enabling the pullup resistor on that pin.
17 All device pin configurations should be placed in child nodes of the
35 /* group 2 */
39 /* enable input on pin 1 */
45 The 'uart0_default' child node encodes the pin configurations for a
49 As shown, pin configurations are organized in groups within each child node.
50 Each group can specify a list of pin function selections in the 'pinmux'
53 A group can also specify shared pin properties common to all the specified
[all …]
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| D | gd,gd32-pinctrl-af.yaml | 5 The GD32 pin controller (AF model) is a singleton node responsible for
6 controlling pin function selection and pin properties. For example, you can
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
8 on the pin.
17 All device pin configurations should be placed in child nodes of the
35 /* group 2 */
52 The 'usart0_default' child node encodes the pin configurations for a
54 state. Similarly, 'usart0_sleep' child node encodes the pin configurations
56 is used for low power states because it disconnects the pin pull-up/down
59 As shown, pin configurations are organized in groups within each child node.
[all …]
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| D | silabs,gecko-pinctrl.yaml | 5 The Silabs pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use this
7 node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
8 pin.
17 All device pin configurations should be placed in child nodes of the
28 /* configure P0.1 as UART_TX and P0.2 as UART_RTS */
29 psels = <GECKO_PSEL(UART_TX, A, 1)>, <GECKO_PSEL(UART_RTS, A, 2)>;
31 /* group 2 */
39 The 'usart0_default' child node encodes the pin configurations for a
44 As shown, pin configurations are organized in groups within each child node.
[all …]
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| D | nordic,nrf-pinctrl.yaml | 5 The nRF pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use this
7 node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
8 pin.
17 All device pin configurations should be placed in child nodes of the
28 /* configure P0.1 as UART_TX and P0.2 as UART_RTS */
29 psels = <NRF_PSEL(UART_TX, 0, 1)>, <NRF_PSEL(UART_RTS, 0, 2)>;
31 /* group 2 */
41 The 'uart0_default' child node encodes the pin configurations for a
46 As shown, pin configurations are organized in groups within each child node.
[all …]
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| /Zephyr-latest/tests/drivers/pinctrl/gd32/src/ |
| D | main_af.c | 9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
29 zassert_equal(GD32_AF_GET(pin), GD32_AF0); in ZTEST()
30 zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE); in ZTEST()
31 zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP); in ZTEST()
32 zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ); in ZTEST()
34 pin = scfg->pins[1]; in ZTEST()
[all …]
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| D | main_afio.c | 9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
29 zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ANALOG); in ZTEST()
30 zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP); in ZTEST()
32 pin = scfg->pins[1]; in ZTEST()
33 zassert_equal(GD32_PORT_GET(pin), 1); in ZTEST()
34 zassert_equal(GD32_PIN_GET(pin), 1); in ZTEST()
[all …]
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| /Zephyr-latest/soc/atmel/sam/common/ |
| D | soc_gpio.h | 19 * Pin flags/attributes
22 /* TODO: replace hard coded pin attribute values with defines provided
34 #define SOC_GPIO_OPENDRAIN_POS (2)
42 #define SOC_GPIO_IN_FILTER_DEGLITCH (2 << SOC_GPIO_IN_FILTER_POS)
54 #define SOC_GPIO_INT_TRIG_DOUBLE_EDGE (2 << SOC_GPIO_INT_TRIG_POS)
62 /** Connect pin to peripheral A. */
64 /** Connect pin to peripheral B. */
66 /** Connect pin to peripheral C. */
67 #define SOC_GPIO_FUNC_C (2 << SOC_GPIO_FUNC_POS)
68 /** Connect pin to peripheral D. */
[all …]
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | st,iis328dq-common.yaml | 11 INT_1 pin
13 This pin defaults to active high when produced by the sensor. The property value should ensure
19 INT_2 pin
21 This pin defaults to active high when produced by the sensor. The property value should ensure
26 enum: [1, 2]
28 Select DRDY pin number (1 or 2).
35 - 2 # drdy is generated on INT2
39 enum: [1, 2]
41 Select threshold interrupt pin number (1 or 2).
48 - 2 # threshold interrupt is generated on INT2
[all …]
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| D | nxp,fxls8974-common.yaml | 12 RST pin
13 This pin defaults to active high when consumed by the sensor.
20 INT1 pin
21 This pin defaults to active low when produced by the sensor.
28 INT2 pin
29 This pin defaults to active low when produced by the sensor.
35 default: 2
37 Range in g. Default value is 2 because it is the most sensitive setting.
38 16g (7.81 mg/LSB), 8g (3.91 mg/LSB), 4g (1.95 mg/LSB), 2g (0.98 mg/LSB).
43 - 2
|
| D | st,lis2dux12-common.yaml | 22 INT1 pin
24 This pin defaults to active high when produced by the sensor.
30 INT2 pin
32 This pin defaults to active high when produced by the sensor.
36 drdy-pin:
41 - 2 # drdy is generated from INT2
43 Select DRDY pin number (1 or 2).
57 - 2 # LIS2DUX12_DT_FS_8G
61 enum: [0, 1, 2, 3]
71 - 2 # LIS2DUX12_OPER_MODE_HIGH_RESOLUTION
[all …]
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| D | nordic,nrf-qdec.yaml | 23 enable-pin:
26 The enable pin to use, to enable a connected QDEC device
28 For pins P0.0 through P0.31, use the pin number. For example,
29 to use P0.16 for the A pin, set:
31 enable-pin = <16>;
33 For pins P1.0 through P1.31, add 32 to the pin number. For
34 example, to use P1.2 for the A pin, set:
36 enable-pin = <34>; /* 32 + 2 */
|
| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/ |
| D | pinctrl-rcar-common.h | 27 /* Arbitrary number to encode non capable gpio pin */
31 * @brief Utility macro to encode a GPIO capable pin
34 * @param pin the pin within the GPIO bank (0..31)
36 #define RCAR_GP_PIN(bank, pin) (((bank) * 32U) + (pin)) argument
39 * @brief Utility macro to encode a non capable GPIO pin
41 * @param pin the encoded pin number
43 #define RCAR_NOGP_PIN(pin) (PIN_NOGPSR_START + pin) argument
54 #define IP2SR0(shift, func) IPnSR(2, 0, shift, func)
58 #define IP2SR1(shift, func) IPnSR(2, 1, shift, func)
60 #define IP0SR2(shift, func) IPnSR(0, 2, shift, func)
[all …]
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_numicro.c | 15 #define MODE_PIN_SHIFT(pin) ((pin) * 2) argument
16 #define MODE_MASK(pin) (3 << MODE_PIN_SHIFT(pin)) argument
17 #define DINOFF_PIN_SHIFT(pin) ((pin) + 16) argument
18 #define DINOFF_MASK(pin) (1 << DINOFF_PIN_SHIFT(pin)) argument
19 #define PUSEL_PIN_SHIFT(pin) ((pin) * 2) argument
20 #define PUSEL_MASK(pin) (3 << PUSEL_PIN_SHIFT(pin)) argument
21 #define SLEWCTL_PIN_SHIFT(pin) ((pin) * 2) argument
22 #define SLEWCTL_MASK(pin) (3 << SLEWCTL_PIN_SHIFT(pin)) argument
26 #define REG_MFP(port, pin) (*(volatile uint32_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, mfp) + \ argument
28 ((pin) > 7 ? 4 : 0)))
[all …]
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| D | pinctrl_b91.c | 19 * gpio_en + 2*8: PORT_C[0-7]
24 #define reg_gpio_en(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, gpio_en) + \ argument
25 ((pin >> 8) * 8)))
32 * pin_mux + 2: PORT_B[0-3]
43 #define reg_pin_mux(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, pin_mux) + \ argument
44 (((pin >> 8) < 4) ? ((pin >> 8) * 2) : 0) + \
45 (((pin >> 8) == 4) ? 0x20 : 0) + \
46 (((pin >> 8) == 5) ? 0x26 : 0) + \
47 ((pin & 0x0f0) ? 1 : 0)))
54 * pull_up_en + 2: PORT_B[0-3]
[all …]
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| /Zephyr-latest/samples/drivers/adc/adc_dt/boards/ |
| D | lpcxpresso55s69_lpc55s69_cpu0.overlay | 11 io-channels = <&adc0 0 &adc0 1 &adc0 2>;
24 * - Connect LPADC0 CH0A signal to voltage between 0~3.3V (P19 pin 4)
25 * - Connect LPADC0 CH0B signal to voltage between 0~3.3V (P19 pin 2)
27 * - Connect LPADC0 CH4A signal to voltage between 0~3.3V (P17 pin 19)
29 * - Connect LPADC0 CH4B signal to voltage between 0~3.3V (P18 pin 1)
34 * CH0A (plus side) is routed to P19 pin 4
35 * CH0B (minus side) is routed to P19 pin 2
50 * CH4A is routed to P17 pin 19
63 * Channel 2 is used in single ended mode, with 12 bit resolution
64 * CH4B is routed to P18 pin 1
[all …]
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_renesas_rz.h | 16 #define GPIO_RZ_REG_OFFSET(port, pin) (port + (pin / 4)) argument
18 #define GPIO_RZ_P_VALUE_GET(value, pin) ((value >> pin) & 1U) argument
19 #define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U) argument
32 #define GPIO_RZ_TSSR_VAL(port, pin) (0x80 | (gpio_rz_int[port] + pin)) argument
34 #define GPIO_RZ_TITSR_OFFSET(irq) ((irq % 16) * 2)
42 #define GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET (~(0x3 << 2))
|
| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | cc13xx_cc26xx-pinctrl.h | 15 #define IOC_PORT_AUX_IO 0x00000008 /* AUX IO Pin */
16 #define IOC_PORT_MCU_SSI0_RX 0x00000009 /* MCU SSI0 Receive Pin */
17 #define IOC_PORT_MCU_SSI0_TX 0x0000000A /* MCU SSI0 Transmit Pin */
18 #define IOC_PORT_MCU_SSI0_FSS 0x0000000B /* MCU SSI0 FSS Pin */
19 #define IOC_PORT_MCU_SSI0_CLK 0x0000000C /* MCU SSI0 Clock Pin */
20 #define IOC_PORT_MCU_I2C_MSSDA 0x0000000D /* MCU I2C Data Pin */
21 #define IOC_PORT_MCU_I2C_MSSCL 0x0000000E /* MCU I2C Clock Pin */
22 #define IOC_PORT_MCU_UART0_RX 0x0000000F /* MCU UART0 Receive Pin */
23 #define IOC_PORT_MCU_UART0_TX 0x00000010 /* MCU UART0 Transmit Pin */
24 #define IOC_PORT_MCU_UART0_CTS 0x00000011 /* MCU UART0 Clear To Send Pin */
[all …]
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| /Zephyr-latest/boards/infineon/cy8cproto_062_4343w/ |
| D | cy8cproto_062_4343w-pinctrl.dtsi | 6 /* Configure pin control bias mode for uart2 pins */
23 /* Configure pin control bias mode for uart5 pins */
32 /* Configure pin control bias mode for i2c3 pins */
44 /* Configure pin control bias mode for SDIO */
46 pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_14)>;
52 pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_14)>;
58 pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_14)>;
64 pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_14)>;
70 pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_14)>;
76 pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_14)>;
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